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| author | Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com> | 2016-02-04 19:45:25 +0100 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2016-02-11 11:20:02 +0100 |
| commit | 1a1ebd5fb1e203ee8cc73508cc7a38ac4b804596 (patch) | |
| tree | 5a046e3c634ce678ac7c73e2293bc485024e8eb1 | |
| parent | irqchip/gic: Only set the EOImodeNS bit for the root controller (diff) | |
| download | linux-1a1ebd5fb1e203ee8cc73508cc7a38ac4b804596.tar.xz linux-1a1ebd5fb1e203ee8cc73508cc7a38ac4b804596.zip | |
irqchip/gic-v3: Make sure read from ICC_IAR1_EL1 is visible on redestributor
The ARM GICv3 specification mentions the need for dsb after a read
from the ICC_IAR1_EL1 register:
4.1.1 Physical CPU Interface:
The effects of reading ICC_IAR0_EL1 and ICC_IAR1_EL1
on the state of a returned INTID are not guaranteed
to be visible until after the execution of a DSB.
Not having this could result in missed interrupts, so let's add the
required barrier.
[Marc: fixed commit message]
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| -rw-r--r-- | arch/arm64/include/asm/arch_gicv3.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h index 2731d3b25ed2..8ec88e5b290f 100644 --- a/arch/arm64/include/asm/arch_gicv3.h +++ b/arch/arm64/include/asm/arch_gicv3.h @@ -103,6 +103,7 @@ static inline u64 gic_read_iar_common(void) u64 irqstat; asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat)); + dsb(sy); return irqstat; } |