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| author | Heiko Stuebner <heiko@sntech.de> | 2019-06-27 10:46:35 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2019-06-27 10:46:35 +0200 |
| commit | 92de4cecf7d1302682b04a0eb01b957830efd5bd (patch) | |
| tree | 9f6643f60f5bc907d7b8717d1ed5c3e178a2939c | |
| parent | clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro (diff) | |
| parent | clk: rockchip: add clock id for hdmi_phy special clock on rk3228 (diff) | |
| download | linux-92de4cecf7d1302682b04a0eb01b957830efd5bd.tar.xz linux-92de4cecf7d1302682b04a0eb01b957830efd5bd.zip | |
Merge branch 'v5.3-shared/clk-ids' into v5.3-clk/next
| -rw-r--r-- | include/dt-bindings/clock/rk3228-cru.h | 1 | ||||
| -rw-r--r-- | include/dt-bindings/clock/rk3328-cru.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index 55655ab0a4c4..a0422f62c040 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -73,6 +73,7 @@ #define SCLK_WIFI 141 #define SCLK_OTGPHY0 142 #define SCLK_OTGPHY1 143 +#define SCLK_HDMI_PHY 144 /* dclk gates */ #define DCLK_VOP 190 diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h index bcaa4559ab1b..6ad54c39f8da 100644 --- a/include/dt-bindings/clock/rk3328-cru.h +++ b/include/dt-bindings/clock/rk3328-cru.h @@ -173,6 +173,7 @@ #define PCLK_DCF 233 #define PCLK_SARADC 234 #define PCLK_ACODECPHY 235 +#define PCLK_WDT 236 /* hclk gates */ #define HCLK_PERI 308 |