diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2022-07-14 17:02:04 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2022-07-14 17:02:12 +0200 |
| commit | e0a592505566c82d60a2010d0976b8ae0a831fcc (patch) | |
| tree | 655f77884683bc73c1e1f9d3a339e0add6a4f48b | |
| parent | Merge tag 'qcom-dts-for-5.20' of git://git.kernel.org/pub/scm/linux/kernel/gi... (diff) | |
| parent | arm64: dts: qcom: sc8280xp: fix DP PHY node unit addresses (diff) | |
| download | linux-e0a592505566c82d60a2010d0976b8ae0a831fcc.tar.xz linux-e0a592505566c82d60a2010d0976b8ae0a831fcc.zip | |
Merge tag 'qcom-arm64-for-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt
Qualcomm ARM64 DTS updates for v5.20
This introduces initial support for Lenovo ThinkPad X13s, Qualcomm 8cx
Gen 3 Compute Reference Device, SA8295P Automotive Development Platform,
Xiaomi Mi 5s Plus, five new SC7180 Chrome OS boards, Inforce IFC6560, LG
G7 ThinQ and LG V35 ThinQ.
With IPQ8074 gaining GDSC support, this was expressed in the gcc node
and defined for the USB nodes. The SDHCI reset line was defined to get
the storage devices into a known state.
For MSM8996 interconnect providers, the second DSI interface, resets for
SDHCI are introduced. Support for the Xiaomi Mi 5s Plus is introduced
and the Dragonboard 820c gains definitions for its LEDs.
The MSM8998 platform changes consists of a various cleanup patches, the
FxTec Pro1 is split out from using the MTP dts and Sony Xperia devices
on the "Yoshino" platform gains ToF sensor.
On SC7180 five new Trogdor based boards are added and the description of
keyboard and detachables is improved.
On the SC7280-based Herobrine board DisplayPort is enabled, SPI flash
clock rate is changed, WiFi is enabled and the modem firmware path is
updated. The Villager boards gains touchscreen, and keyboard backlight.
This introduces initial support for the SC8280XP (aka 8cx Gen 3) and
related automotive platforms are introduced, with support for the
Qualcomm reference board, the Lenovo Thinkpad X13s and the SA8295P
Automotive Development Platform.
In addition to a wide range of smaller fixes on the SDM630 and SDM660
platforms, support for the secondary high speed USB controller is
introduced and the Sony Xperia "Nile" platform gains support for the RGB
status LED. Support for the Inforce IFC6560 board is introduced.
On SDM845 the bandwidth monitor for the CPU subsystem is introduced, to
scale LLCC clock rate based on profiling. CPU and cluster idle states
are switched to OSI hierarchical states. DB845c and SHIFT 6mq gains LED
support and new support for the LG G7 ThinQ and LG V35 ThinQ boards are
added.
DLL/DDR configuration for SDHCI nodes are defined for SM6125.
On SM8250 the GPU per-process page tables is enabled and for RB5 the
Light Pulse Generator-based LEDs are added.
The display clock controller is introduced for SM8350.
On SM8450 this introduces the camera clock controller and the UART
typically used for Bluetooth. The interconnect path for the crypto
engine is added to the SCM node, to ensure this is adequately clocked.
The assigned-clock-rate for the display processor is dropped from
several platforms, now that the driver derrives the min and max from the
clock.
In addition to this a wide range of fixes for stylistic issues and
issues discovered through Devicetree binding validation across many
platforms and boards are introduced.
* tag 'qcom-arm64-for-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (193 commits)
arm64: dts: qcom: sc8280xp: fix DP PHY node unit addresses
arm64: dts: qcom: sc8280xp: fix usb_0 HS PHY ref clock
arm64: dts: qcom: sc7280: fix PCIe clock reference
docs: arm: index.rst: add google/chromebook-boot-flow
arm64: dts: qcom: msm8996: clean up PCIe PHY node
arm64: dts: qcom: msm8996: use non-empty ranges for PCIe PHYs
arm64: dts: qcom: sm8450: drop UFS PHY clock-cells
arm64: dts: qcom: sm8250: drop UFS PHY clock-cells
arm64: dts: qcom: sc8280xp: drop UFS PHY clock-cells
arm64: dts: qcom: sm8450: drop USB PHY clock index
arm64: dts: qcom: sm8350: drop USB PHY clock index
arm64: dts: qcom: msm8998: drop USB PHY clock index
arm64: dts: qcom: ipq8074: drop USB PHY clock index
arm64: dts: qcom: ipq6018: drop USB PHY clock index
arm64: dts: qcom: sm8250: add missing PCIe PHY clock-cells
arm64: dts: qcom: sc7280: drop PCIe PHY clock index
Revert "arm64: dts: qcom: Fix 'reg-names' for sdhci nodes"
arm64: dts: qcom: sc7180-idp: add vdds supply to the DSI PHY
arm64: dts: qcom: sc7280: use constants for gpucc clocks and power-domains
arm64: dts: qcom: msm8996: add missing DSI clock assignments
...
Link: https://lore.kernel.org/r/20220713203939.1431054-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
163 files changed, 11368 insertions, 1628 deletions
diff --git a/Documentation/arm/google/chromebook-boot-flow.rst b/Documentation/arm/google/chromebook-boot-flow.rst new file mode 100644 index 000000000000..36da77684bba --- /dev/null +++ b/Documentation/arm/google/chromebook-boot-flow.rst @@ -0,0 +1,69 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================== +Chromebook Boot Flow +====================================== + +Most recent Chromebooks that use device tree are using the opensource +depthcharge_ bootloader. Depthcharge_ expects the OS to be packaged as a `FIT +Image`_ which contains an OS image as well as a collection of device trees. It +is up to depthcharge_ to pick the right device tree from the `FIT Image`_ and +provide it to the OS. + +The scheme that depthcharge_ uses to pick the device tree takes into account +three variables: + +- Board name, specified at depthcharge_ compile time. This is $(BOARD) below. +- Board revision number, determined at runtime (perhaps by reading GPIO + strappings, perhaps via some other method). This is $(REV) below. +- SKU number, read from GPIO strappings at boot time. This is $(SKU) below. + +For recent Chromebooks, depthcharge_ creates a match list that looks like this: + +- google,$(BOARD)-rev$(REV)-sku$(SKU) +- google,$(BOARD)-rev$(REV) +- google,$(BOARD)-sku$(SKU) +- google,$(BOARD) + +Note that some older Chromebooks use a slightly different list that may +not include SKU matching or may prioritize SKU/rev differently. + +Note that for some boards there may be extra board-specific logic to inject +extra compatibles into the list, but this is uncommon. + +Depthcharge_ will look through all device trees in the `FIT Image`_ trying to +find one that matches the most specific compatible. It will then look +through all device trees in the `FIT Image`_ trying to find the one that +matches the *second most* specific compatible, etc. + +When searching for a device tree, depthcharge_ doesn't care where the +compatible string falls within a device tree's root compatible string array. +As an example, if we're on board "lazor", rev 4, SKU 0 and we have two device +trees: + +- "google,lazor-rev5-sku0", "google,lazor-rev4-sku0", "qcom,sc7180" +- "google,lazor", "qcom,sc7180" + +Then depthcharge_ will pick the first device tree even though +"google,lazor-rev4-sku0" was the second compatible listed in that device tree. +This is because it is a more specific compatible than "google,lazor". + +It should be noted that depthcharge_ does not have any smarts to try to +match board or SKU revisions that are "close by". That is to say that +if depthcharge_ knows it's on "rev4" of a board but there is no "rev4" +device tree then depthcharge_ *won't* look for a "rev3" device tree. + +In general when any significant changes are made to a board the board +revision number is increased even if none of those changes need to +be reflected in the device tree. Thus it's fairly common to see device +trees with multiple revisions. + +It should be noted that, taking into account the above system that +depthcharge_ has, the most flexibility is achieved if the device tree +supporting the newest revision(s) of a board omits the "-rev{REV}" +compatible strings. When this is done then if you get a new board +revision and try to run old software on it then we'll at pick the +newest device tree we know about. + +.. _depthcharge: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/depthcharge/ +.. _`FIT Image`: https://doc.coreboot.org/lib/payloads/fit.html diff --git a/Documentation/arm/index.rst b/Documentation/arm/index.rst index 2bda5461a80b..495ada7915e1 100644 --- a/Documentation/arm/index.rst +++ b/Documentation/arm/index.rst @@ -31,6 +31,8 @@ SoC-specific documents .. toctree:: :maxdepth: 1 + google/chromebook-boot-flow + ixp4xx marvell diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 5c06d1bfc046..fffd596e8901 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -44,6 +44,7 @@ description: | sc7280 sc8180x sc8280xp + sda660 sdm630 sdm632 sdm660 @@ -90,6 +91,11 @@ description: | A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in foundry 2. + There are many devices in the list below that run the standard ChromeOS + bootloader setup and use the open source depthcharge bootloader to boot the + OS. These devices do not use the scheme described above. For details, see: + https://docs.kernel.org/arm/google/chromebook-boot-flow.html + properties: $nodename: const: "/" @@ -190,6 +196,7 @@ properties: - sony,kagura-row - sony,keyaki-row - xiaomi,gemini + - xiaomi,natrium - xiaomi,scorpio - const: qcom,msm8996 @@ -214,19 +221,317 @@ properties: - qcom,ipq8074-hk10-c2 - const: qcom,ipq8074 - - items: + - description: Qualcomm Technologies, Inc. SC7180 IDP + items: - enum: - qcom,sc7180-idp - const: qcom,sc7180 - - items: - - enum: - - qcom,sc7280-crd - - qcom,sc7280-idp - - qcom,sc7280-idp2 - - google,hoglin - - google,piglin - - google,senor + - description: HP Chromebook x2 11c (rev1 - 2) + items: + - const: google,coachz-rev1 + - const: google,coachz-rev2 + - const: qcom,sc7180 + + - description: HP Chromebook x2 11c (newest rev) + items: + - const: google,coachz + - const: qcom,sc7180 + + - description: HP Chromebook x2 11c with LTE (rev1 - 2) + items: + - const: google,coachz-rev1-sku0 + - const: google,coachz-rev2-sku0 + - const: qcom,sc7180 + + - description: HP Chromebook x2 11c with LTE (newest rev) + items: + - const: google,coachz-sku0 + - const: qcom,sc7180 + + - description: Lenovo Chromebook Duet 5 13 (rev2) + items: + - const: google,homestar-rev2 + - const: google,homestar-rev23 + - const: qcom,sc7180 + + - description: Lenovo Chromebook Duet 5 13 (rev3) + items: + - const: google,homestar-rev3 + - const: qcom,sc7180 + + - description: Lenovo Chromebook Duet 5 13 (newest rev) + items: + - const: google,homestar + - const: qcom,sc7180 + + - description: Google Kingoftown (rev0) + items: + - const: google,kingoftown-rev0 + - const: qcom,sc7180 + + - description: Google Kingoftown (newest rev) + items: + - const: google,kingoftown + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 (rev0) + items: + - const: google,lazor-rev0 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 (rev1 - 2) + items: + - const: google,lazor-rev1 + - const: google,lazor-rev2 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 (rev3 - 8) + items: + - const: google,lazor-rev3 + - const: google,lazor-rev4 + - const: google,lazor-rev5 + - const: google,lazor-rev6 + - const: google,lazor-rev7 + - const: google,lazor-rev8 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 (newest rev) + items: + - const: google,lazor + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 with KB Backlight (rev1 - 2) + items: + - const: google,lazor-rev1-sku2 + - const: google,lazor-rev2-sku2 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 with KB Backlight (rev3 - 8) + items: + - const: google,lazor-rev3-sku2 + - const: google,lazor-rev4-sku2 + - const: google,lazor-rev5-sku2 + - const: google,lazor-rev6-sku2 + - const: google,lazor-rev7-sku2 + - const: google,lazor-rev8-sku2 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 with KB Backlight (newest rev) + items: + - const: google,lazor-sku2 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 with LTE (rev1 - 2) + items: + - const: google,lazor-rev1-sku0 + - const: google,lazor-rev2-sku0 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 with LTE (rev3 - 8) + items: + - const: google,lazor-rev3-sku0 + - const: google,lazor-rev4-sku0 + - const: google,lazor-rev5-sku0 + - const: google,lazor-rev6-sku0 + - const: google,lazor-rev7-sku0 + - const: google,lazor-rev8-sku0 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 with LTE (newest rev) + items: + - const: google,lazor-sku0 + - const: qcom,sc7180 + + - description: Acer Chromebook 511 (rev4 - rev8) + items: + - const: google,lazor-rev4-sku4 + - const: google,lazor-rev5-sku4 + - const: google,lazor-rev6-sku4 + - const: google,lazor-rev7-sku4 + - const: google,lazor-rev8-sku4 + - const: qcom,sc7180 + + - description: Acer Chromebook 511 (newest rev) + items: + - const: google,lazor-sku4 + - const: qcom,sc7180 + + - description: Acer Chromebook 511 without Touchscreen (rev4) + items: + - const: google,lazor-rev4-sku5 + - const: qcom,sc7180 + + - description: Acer Chromebook 511 without Touchscreen (rev5 - rev8) + items: + - const: google,lazor-rev5-sku5 + - const: google,lazor-rev5-sku6 + - const: google,lazor-rev6-sku6 + - const: google,lazor-rev7-sku6 + - const: google,lazor-rev8-sku6 + - const: qcom,sc7180 + + - description: Acer Chromebook 511 without Touchscreen (newest rev) + items: + - const: google,lazor-sku6 + - const: qcom,sc7180 + + - description: Google Mrbland with AUO panel (rev0) + items: + - const: google,mrbland-rev0-sku0 + - const: qcom,sc7180 + + - description: Google Mrbland with AUO panel (newest rev) + items: + - const: google,mrbland-sku1536 + - const: qcom,sc7180 + + - description: Google Mrbland with BOE panel (rev0) + items: + - const: google,mrbland-rev0-sku16 + - const: qcom,sc7180 + + - description: Google Mrbland with BOE panel (newest rev) + items: + - const: google,mrbland-sku1024 + - const: google,mrbland-sku768 + - const: qcom,sc7180 + + - description: Google Pazquel with Parade (newest rev) + items: + - const: google,pazquel-sku5 + - const: qcom,sc7180 + + - description: Google Pazquel with TI (newest rev) + items: + - const: google,pazquel-sku1 + - const: qcom,sc7180 + + - description: Google Pazquel with LTE and Parade (newest rev) + items: + - const: google,pazquel-sku4 + - const: qcom,sc7180 + + - description: Google Pazquel with LTE and TI (newest rev) + items: + - const: google,pazquel-sku0 + - const: google,pazquel-sku2 + - const: qcom,sc7180 + + - description: Sharp Dynabook Chromebook C1 (rev1) + items: + - const: google,pompom-rev1 + - const: qcom,sc7180 + + - description: Sharp Dynabook Chromebook C1 (rev2) + items: + - const: google,pompom-rev2 + - const: qcom,sc7180 + + - description: Sharp Dynabook Chromebook C1 (newest rev) + items: + - const: google,pompom + - const: qcom,sc7180 + + - description: Sharp Dynabook Chromebook C1 with LTE (rev1) + items: + - const: google,pompom-rev1-sku0 + - const: qcom,sc7180 + + - description: Sharp Dynabook Chromebook C1 with LTE (rev2) + items: + - const: google,pompom-rev2-sku0 + - const: qcom,sc7180 + + - description: Sharp Dynabook Chromebook C1 with LTE (newest rev) + items: + - const: google,pompom-sku0 + - const: qcom,sc7180 + + - description: Google Quackingstick (newest rev) + items: + - const: google,quackingstick-sku1537 + - const: qcom,sc7180 + + - description: Google Quackingstick with LTE (newest rev) + items: + - const: google,quackingstick-sku1536 + - const: qcom,sc7180 + + - description: Google Trogdor (newest rev) + items: + - const: google,trogdor + - const: qcom,sc7180 + + - description: Google Trogdor with LTE (newest rev) + items: + - const: google,trogdor-sku0 + - const: qcom,sc7180 + + - description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel (rev0) + items: + - const: google,wormdingler-rev0-sku16 + - const: qcom,sc7180 + + - description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel (newest rev) + items: + - const: google,wormdingler-sku1024 + - const: qcom,sc7180 + + - description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel and rt5682s (newest rev) + items: + - const: google,wormdingler-sku1025 + - const: qcom,sc7180 + + - description: Lenovo IdeaPad Chromebook Duet 3 with INX panel (rev0) + items: + - const: google,wormdingler-rev0-sku0 + - const: qcom,sc7180 + + - description: Lenovo IdeaPad Chromebook Duet 3 with INX panel (newest rev) + items: + - const: google,wormdingler-sku0 + - const: qcom,sc7180 + + - description: Lenovo IdeaPad Chromebook Duet 3 with INX panel and rt5682s (newest rev) + items: + - const: google,wormdingler-sku1 + - const: qcom,sc7180 + + - description: Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4) + items: + - const: qcom,sc7280-crd + - const: google,hoglin-rev3 + - const: google,hoglin-rev4 + - const: google,piglin-rev3 + - const: google,piglin-rev4 + - const: qcom,sc7280 + + - description: Qualcomm Technologies, Inc. sc7280 CRD platform (newest rev) + items: + - const: google,hoglin + - const: qcom,sc7280 + + - description: Qualcomm Technologies, Inc. sc7280 IDP SKU1 platform + items: + - const: qcom,sc7280-idp + - const: google,senor + - const: qcom,sc7280 + + - description: Qualcomm Technologies, Inc. sc7280 IDP SKU2 platform + items: + - const: qcom,sc7280-idp2 + - const: google,piglin + - const: qcom,sc7280 + + - description: Google Herobrine (newest rev) + items: + - const: google,herobrine + - const: qcom,sc7280 + + - description: Google Villager (newest rev) + items: + - const: google,villager - const: qcom,sc7280 - items: @@ -238,11 +543,18 @@ properties: - items: - enum: + - lenovo,thinkpad-x13s + - qcom,sc8280xp-crd - qcom,sc8280xp-qrd - const: qcom,sc8280xp - items: - enum: + - inforce,ifc6560 + - const: qcom,sda660 + + - items: + - enum: - fairphone,fp3 - const: qcom,sdm632 diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 31497677e8de..7a8d375e055e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -4,18 +4,19 @@ $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350 maintainers: - Jonathan Marek <jonathan@marek.ca> description: | Qualcomm display clock control module which supports the clocks, resets and - power domains on SM8150 and SM8250. + power domains on SM8150/SM8250/SM8350. See also: dt-bindings/clock/qcom,dispcc-sm8150.h dt-bindings/clock/qcom,dispcc-sm8250.h + dt-bindings/clock/qcom,dispcc-sm8350.h properties: compatible: @@ -23,6 +24,7 @@ properties: - qcom,sc8180x-dispcc - qcom,sm8150-dispcc - qcom,sm8250-dispcc + - qcom,sm8350-dispcc clocks: items: diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml new file mode 100644 index 000000000000..0a0546c079a9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller Binding + +maintainers: + - Robert Foss <robert.foss@linaro.org> + +description: | + Qualcomm graphics clock control module which supports the clocks, resets and + power domains on Qualcomm SoCs. + + See also: + dt-bindings/clock/qcom,gpucc-sm8350.h + +properties: + compatible: + enum: + - qcom,sm8350-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm8350.h> + #include <dt-bindings/clock/qcom,rpmh.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@3d90000 { + compatible = "qcom,sm8350-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml new file mode 100644 index 000000000000..268f4c6ae0ee --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller Binding for SM8450 + +maintainers: + - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> + +description: | + Qualcomm camera clock control module which supports the clocks, resets and + power domains on SM8450. + + See also include/dt-bindings/clock/qcom,sm8450-camcc.h + +properties: + compatible: + const: qcom,sm8450-camcc + + clocks: + items: + - description: Camera AHB clock from GCC + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + + power-domains: + maxItems: 1 + description: + A phandle and PM domain specifier for the MMCX power domain. + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - power-domains + - required-opps + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm8450.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + clock-controller@ade0000 { + compatible = "qcom,sm8450-camcc"; + reg = <0xade0000 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd SM8450_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index daff820051d6..90fbc1d2c950 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2540,6 +2540,7 @@ W: http://www.armlinux.org.uk/ ARM/QUALCOMM SUPPORT M: Andy Gross <agross@kernel.org> M: Bjorn Andersson <bjorn.andersson@linaro.org> +R: Konrad Dybcio <konrad.dybcio@somainline.org> L: linux-arm-msm@vger.kernel.org S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 2f8aec2cc6db..9e2a13d75f9d 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -30,13 +30,11 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-satsuki.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-sumire.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-suzuran.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-pmi8996-sony-xperia-tone-dora.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-pmi8996-sony-xperia-tone-kagura.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-pmi8996-sony-xperia-tone-keyaki.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-dora.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-kagura.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-keyaki.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-gemini.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-natrium.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-scorpio.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-fxtec-pro1.dtb @@ -52,6 +50,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb @@ -60,6 +59,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r4.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown-r0.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb @@ -75,12 +76,28 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-r9.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r4.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r5.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r9.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev0-auo.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev0-boe.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev1-auo.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev1-boe.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-parade.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-ti.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-parade.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-ti.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev0-boe.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev0-inx.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd.dtb @@ -89,6 +106,9 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb +dtb-$(CONFIG_ARCH_QCOM) += sda660-inforce-ifc6560.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb @@ -100,6 +120,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-enchilada.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 7c1eab605c15..1b613098fb4a 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -8,6 +8,7 @@ #include "msm8916-pm8916.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/pinctrl/qcom,pmic-mpp.h> #include <dt-bindings/sound/apq8016-lpass.h> @@ -20,11 +21,11 @@ serial0 = &blsp1_uart2; serial1 = &blsp1_uart1; usid0 = &pm8916_0; - i2c0 = &blsp_i2c2; - i2c1 = &blsp_i2c6; - i2c3 = &blsp_i2c4; - spi0 = &blsp_spi5; - spi1 = &blsp_spi3; + i2c0 = &blsp_i2c2; + i2c1 = &blsp_i2c6; + i2c3 = &blsp_i2c4; + spi0 = &blsp_spi5; + spi1 = &blsp_spi3; }; chosen { @@ -92,14 +93,12 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; pinctrl-names = "default"; pinctrl-0 = <&msm_key_volp_n_default>; - button@0 { + button { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; @@ -116,6 +115,8 @@ led@1 { label = "apq8016-sbc:green:user1"; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; @@ -123,6 +124,8 @@ led@2 { label = "apq8016-sbc:green:user2"; + function = LED_FUNCTION_DISK_ACTIVITY; + color = <LED_COLOR_ID_GREEN>; gpios = <&msmgpio 120 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; @@ -130,6 +133,8 @@ led@3 { label = "apq8016-sbc:green:user3"; + function = LED_FUNCTION_DISK_ACTIVITY; + color = <LED_COLOR_ID_GREEN>; gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc1"; default-state = "off"; @@ -137,6 +142,7 @@ led@4 { label = "apq8016-sbc:green:user4"; + color = <LED_COLOR_ID_GREEN>; gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; panic-indicator; @@ -145,6 +151,8 @@ led@5 { label = "apq8016-sbc:yellow:wlan"; + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_YELLOW>; gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; default-state = "off"; @@ -152,6 +160,8 @@ led@6 { label = "apq8016-sbc:blue:bt"; + function = LED_FUNCTION_BLUETOOTH; + color = <LED_COLOR_ID_BLUE>; gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; default-state = "off"; @@ -773,7 +783,7 @@ "USB_HUB_RESET_N_PM", "USB_SW_SEL_PM"; - usb_hub_reset_pm: usb-hub-reset-pm { + usb_hub_reset_pm: usb-hub-reset-pm-state { pins = "gpio3"; function = PMIC_GPIO_FUNC_NORMAL; @@ -781,14 +791,14 @@ output-high; }; - usb_hub_reset_pm_device: usb-hub-reset-pm-device { + usb_hub_reset_pm_device: usb-hub-reset-pm-device-state { pins = "gpio3"; function = PMIC_GPIO_FUNC_NORMAL; output-low; }; - usb_sw_sel_pm: usb-sw-sel-pm { + usb_sw_sel_pm: usb-sw-sel-pm-state { pins = "gpio4"; function = PMIC_GPIO_FUNC_NORMAL; @@ -797,7 +807,7 @@ output-high; }; - usb_sw_sel_pm_device: usb-sw-sel-pm-device { + usb_sw_sel_pm_device: usb-sw-sel-pm-device-state { pins = "gpio4"; function = PMIC_GPIO_FUNC_NORMAL; @@ -806,7 +816,7 @@ output-low; }; - pm8916_gpios_leds: pm8916-gpios-leds { + pm8916_gpios_leds: pm8916-gpios-leds-state { pins = "gpio1", "gpio2"; function = PMIC_GPIO_FUNC_NORMAL; diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 49afbb1a066a..c1cb1ba5173c 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -10,6 +10,7 @@ #include "pmi8994.dtsi" #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> @@ -49,11 +50,11 @@ serial0 = &blsp2_uart2; serial1 = &blsp2_uart3; serial2 = &blsp1_uart2; - i2c0 = &blsp1_i2c3; - i2c1 = &blsp2_i2c1; - i2c2 = &blsp2_i2c1; - spi0 = &blsp1_spi1; - spi1 = &blsp2_spi6; + i2c0 = &blsp1_i2c3; + i2c1 = &blsp2_i2c1; + i2c2 = &blsp2_i2c1; + spi0 = &blsp1_spi1; + spi1 = &blsp2_spi6; }; chosen { @@ -82,16 +83,14 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; pinctrl-names = "default"; pinctrl-0 = <&volume_up_gpio>; - button@0 { + button { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; @@ -555,15 +554,16 @@ pinctrl-names = "default"; pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>; - ls_exp_gpio_f: pm8994_gpio5 { + ls_exp_gpio_f: pm8994-gpio5-state { pinconf { pins = "gpio5"; + function = PMIC_GPIO_FUNC_NORMAL; output-low; power-source = <2>; // PM8994_GPIO_S4, 1.8V }; }; - bt_en_gpios: bt_en_gpios { + bt_en_gpios: bt-en-pios-state { pinconf { pins = "gpio19"; function = PMIC_GPIO_FUNC_NORMAL; @@ -574,7 +574,7 @@ }; }; - wlan_en_gpios: wlan_en_gpios { + wlan_en_gpios: wlan-en-gpios-state { pinconf { pins = "gpio8"; function = PMIC_GPIO_FUNC_NORMAL; @@ -585,7 +585,7 @@ }; }; - audio_mclk: clk_div1 { + audio_mclk: clk-div1-state { pinconf { pins = "gpio15"; function = "func1"; @@ -593,7 +593,7 @@ }; }; - volume_up_gpio: pm8996_gpio2 { + volume_up_gpio: pm8996-gpio2-state { pinconf { pins = "gpio2"; function = "normal"; @@ -605,7 +605,7 @@ }; }; - divclk4_pin_a: divclk4 { + divclk4_pin_a: divclk4-state { pinconf { pins = "gpio18"; function = PMIC_GPIO_FUNC_FUNC2; @@ -615,7 +615,7 @@ }; }; - usb3_vbus_det_gpio: pm8996_gpio22 { + usb3_vbus_det_gpio: pm8996-gpio22-state { pinconf { pins = "gpio22"; function = PMIC_GPIO_FUNC_NORMAL; @@ -671,7 +671,7 @@ "NC", "NC"; - usb2_vbus_det_gpio: pmi8996_gpio6 { + usb2_vbus_det_gpio: pmi8996-gpio6-state { pinconf { pins = "gpio6"; function = PMIC_GPIO_FUNC_NORMAL; @@ -683,6 +683,61 @@ }; }; +&pmi8994_lpg { + qcom,power-source = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmi8994_mpp2_userled4>; + + qcom,dtest = <0 0>, + <0 0>, + <0 0>, + <4 1>; + + status = "okay"; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <1>; + + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <0>; + }; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <2>; + }; + + led@4 { + reg = <4>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <3>; + }; +}; + +&pmi8994_mpps { + pmi8994_mpp2_userled4: mpp2-userled4-state { + pins = "mpp2"; + function = "sink"; + + output-low; + qcom,dtest = <4>; + }; +}; + &pmi8994_spmi_regulators { vdd_s2-supply = <&vph_pwr>; @@ -957,7 +1012,7 @@ &sound { compatible = "qcom,apq8096-sndcard"; model = "DB820c"; - audio-routing = "RX_BIAS", "MCLK", + audio-routing = "RX_BIAS", "MCLK", "MM_DL1", "MultiMedia1 Playback", "MM_DL2", "MultiMedia2 Playback", "MultiMedia3 Capture", "MM_UL3"; diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index 821cb7c0c183..1ba2eca33c7b 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -29,13 +29,13 @@ status = "okay"; }; -&i2c_1 { +&blsp1_i2c3 { pinctrl-0 = <&i2c_1_pins>; pinctrl-names = "default"; status = "okay"; }; -&spi_0 { +&blsp1_spi1 { cs-select = <0>; status = "okay"; @@ -43,7 +43,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0>; - compatible = "n25q128a11"; + compatible = "micron,n25q128a11", "jedec,spi-nor"; spi-max-frequency = <50000000>; }; }; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index c89499e366d3..aaad7d9059f6 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -87,7 +87,7 @@ }; }; - cpu_opp_table: cpu_opp_table { + cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; @@ -125,7 +125,7 @@ firmware { scm { - compatible = "qcom,scm"; + compatible = "qcom,scm-ipq6018", "qcom,scm"; }; }; @@ -282,7 +282,7 @@ status = "disabled"; }; - spi_0: spi@78b5000 { + blsp1_spi1: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; @@ -297,7 +297,7 @@ status = "disabled"; }; - spi_1: spi@78b6000 { + blsp1_spi2: spi@78b6000 { compatible = "qcom,spi-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; @@ -312,7 +312,7 @@ status = "disabled"; }; - i2c_0: i2c@78b6000 { + blsp1_i2c2: i2c@78b6000 { compatible = "qcom,i2c-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; @@ -321,13 +321,13 @@ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - clock-frequency = <400000>; + clock-frequency = <400000>; dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; status = "disabled"; }; - i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */ + blsp1_i2c3: i2c@78b7000 { compatible = "qcom,i2c-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; @@ -336,7 +336,7 @@ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - clock-frequency = <400000>; + clock-frequency = <400000>; dmas = <&blsp_dma 16>, <&blsp_dma 17>; dma-names = "tx", "rx"; status = "disabled"; @@ -525,9 +525,9 @@ }; timer@b120000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x10000000>; compatible = "arm,armv7-timer-mem"; reg = <0x0 0x0b120000 0x0 0x1000>; @@ -535,49 +535,49 @@ frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x0b121000 0x0 0x1000>, - <0x0 0x0b122000 0x0 0x1000>; + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; }; frame@b123000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0xb123000 0x0 0x1000>; + reg = <0x0b123000 0x1000>; status = "disabled"; }; frame@b124000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x0b124000 0x0 0x1000>; + reg = <0x0b124000 0x1000>; status = "disabled"; }; frame@b125000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x0b125000 0x0 0x1000>; + reg = <0x0b125000 0x1000>; status = "disabled"; }; frame@b126000 { frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x0b126000 0x0 0x1000>; + reg = <0x0b126000 0x1000>; status = "disabled"; }; frame@b127000 { frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x0b127000 0x0 0x1000>; + reg = <0x0b127000 0x1000>; status = "disabled"; }; frame@b128000 { frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x0b128000 0x0 0x1000>; + reg = <0x0b128000 0x1000>; status = "disabled"; }; }; @@ -621,6 +621,7 @@ glink-edge { interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>; + label = "rtr"; qcom,remote-pid = <1>; mboxes = <&apcs_glb 8>; @@ -710,7 +711,7 @@ <0x0 0x00078800 0x0 0x1F8>, /* PCS */ <0x0 0x00078600 0x0 0x044>; /* PCS misc */ #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&gcc GCC_USB0_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "gcc_usb0_pipe_clk_src"; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 4c38b15c6fd4..edcb6a500175 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -119,7 +119,7 @@ <&xo>; clock-names = "aux", "cfg_ahb", "ref"; - resets = <&gcc GCC_USB1_PHY_BCR>, + resets = <&gcc GCC_USB1_PHY_BCR>, <&gcc GCC_USB3PHY_1_PHY_BCR>; reset-names = "phy","common"; status = "disabled"; @@ -130,7 +130,7 @@ <0x00058800 0x1f8>, /* PCS */ <0x00058600 0x044>; /* PCS misc*/ #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&gcc GCC_USB1_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "gcc_usb1_pipe_clk_src"; @@ -162,7 +162,7 @@ <&xo>; clock-names = "aux", "cfg_ahb", "ref"; - resets = <&gcc GCC_USB0_PHY_BCR>, + resets = <&gcc GCC_USB0_PHY_BCR>, <&gcc GCC_USB3PHY_0_PHY_BCR>; reset-names = "phy","common"; status = "disabled"; @@ -173,7 +173,7 @@ <0x00078800 0x1f8>, /* PCS */ <0x00078600 0x044>; /* PCS misc*/ #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&gcc GCC_USB0_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "gcc_usb0_pipe_clk_src"; @@ -347,6 +347,7 @@ compatible = "qcom,gcc-ipq8074"; reg = <0x01800000 0x80000>; #clock-cells = <0x1>; + #power-domain-cells = <1>; #reset-cells = <0x1>; }; @@ -375,7 +376,7 @@ cell-index = <0>; }; - sdhc_1: sdhci@7824900 { + sdhc_1: mmc@7824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0x7824900 0x500>, <0x7824000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -384,10 +385,11 @@ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&xo>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>; - clock-names = "xo", "iface", "core"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo>; + clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC1_BCR>; max-frequency = <384000000>; mmc-ddr-1_8v; mmc-hs200-1_8v; @@ -534,7 +536,7 @@ status = "disabled"; }; - qpic_nand: nand@79b0000 { + qpic_nand: nand-controller@79b0000 { compatible = "qcom,ipq8074-nand"; reg = <0x079b0000 0x10000>; #address-cells = <1>; @@ -575,6 +577,8 @@ <133330000>, <19200000>; + power-domains = <&gcc USB0_GDSC>; + resets = <&gcc GCC_USB0_BCR>; status = "disabled"; @@ -615,6 +619,8 @@ <133330000>, <19200000>; + power-domains = <&gcc USB1_GDSC>; + resets = <&gcc GCC_USB1_BCR>; status = "disabled"; @@ -648,14 +654,6 @@ }; }; - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; - watchdog: watchdog@b017000 { compatible = "qcom,kpss-wdt"; reg = <0xb017000 0x1000>; @@ -847,4 +845,12 @@ status = "disabled"; }; }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index 265e539e7e99..3dc9619fde6e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -27,7 +27,7 @@ label = "GPIO Buttons"; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts index d4d33dd3584a..dd92070a1211 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts @@ -28,14 +28,14 @@ label = "GPIO Buttons"; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; debounce-interval = <15>; }; - volume-down { + button-volume-down { label = "Volume Down"; gpios = <&msmgpio 117 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 00488afb413d..9e470c67274e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -39,7 +39,7 @@ label = "GPIO Buttons"; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index b3836dde8a54..d85e7f7c0835 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -39,7 +39,7 @@ label = "GPIO Buttons"; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index f9ce123471d4..b4812f093b17 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -28,7 +28,7 @@ label = "GPIO Buttons"; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 9b4b7de7cec2..10f6509a8709 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -31,13 +31,13 @@ label = "GPIO Buttons"; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; }; - home { + button-home { label = "Home"; gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOMEPAGE>; @@ -52,7 +52,7 @@ label = "GPIO Hall Effect Sensor"; - hall-sensor { + event-hall-sensor { label = "Hall Effect Sensor"; gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -460,10 +460,18 @@ drive-strength = <2>; bias-disable; }; + + ts_int_default: ts-int-default { + pins = "gpio13"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; }; &pm8916_gpios { - nfc_clk_req: nfc-clk-req { + nfc_clk_req: nfc-clk-req-state { pins = "gpio2"; function = "func1"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts index 4ba11b020f9b..bc198a2eea25 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts @@ -128,12 +128,4 @@ drive-strength = <2>; bias-disable; }; - - ts_int_default: ts-int-default { - pins = "gpio13"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts index d978c9ac179d..7f2ab1891d91 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts @@ -69,12 +69,4 @@ drive-strength = <2>; bias-disable; }; - - ts_int_default: ts-int-default { - pins = "gpio13"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts index 6c408d61de75..eabeed18cfaa 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts @@ -34,13 +34,13 @@ label = "GPIO Buttons"; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; }; - home-key { + button-home { label = "Home Key"; gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOMEPAGE>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index 58dfbfff4c7d..439e89cf7878 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -49,13 +49,13 @@ label = "GPIO Buttons"; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; }; - home { + button-home { label = "Home"; gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOMEPAGE>; @@ -70,7 +70,7 @@ label = "GPIO Hall Effect Sensor"; - hall-sensor { + event-hall-sensor { label = "Hall Effect Sensor"; gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index 69a44c6f57fc..84a352dcf9a2 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -29,7 +29,7 @@ label = "GPIO Buttons"; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 05472510e29d..48bc2e09128d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -216,7 +216,7 @@ }; }; - cpu_opp_table: cpu-opp-table { + cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; @@ -301,6 +301,8 @@ rpmcc: clock-controller { compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; }; rpmpd: power-controller { @@ -436,7 +438,7 @@ }; qfprom: qfprom@5c000 { - compatible = "qcom,qfprom"; + compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; reg = <0x0005c000 0x1000>; #address-cells = <1>; #size-cells = <1>; @@ -1464,7 +1466,7 @@ #sound-dai-cells = <1>; }; - sdhc_1: sdhci@7824000 { + sdhc_1: mmc@7824000 { compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07824900 0x11c>, <0x07824000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -1472,17 +1474,17 @@ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; mmc-ddr-1_8v; bus-width = <8>; non-removable; status = "disabled"; }; - sdhc_2: sdhci@7864000 { + sdhc_2: mmc@7864000 { compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07864900 0x11c>, <0x07864000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -1490,10 +1492,10 @@ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; bus-width = <4>; status = "disabled"; }; @@ -1788,8 +1790,8 @@ <&rpmpd MSM8916_VDDMX>; power-domain-names = "cx", "mx"; - qcom,state = <&wcnss_smp2p_out 0>; - qcom,state-names = "stop"; + qcom,smem-states = <&wcnss_smp2p_out 0>; + qcom,smem-state-names = "stop"; pinctrl-names = "default"; pinctrl-0 = <&wcnss_pin_a>; @@ -1858,6 +1860,8 @@ compatible = "qcom,msm8916-a53pll"; reg = <0x0b016000 0x40>; #clock-cells = <0>; + clocks = <&xo_board>; + clock-names = "xo"; }; timer@b020000 { diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index ffc3ec2cd3bc..8416a45ca4fd 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -215,7 +215,7 @@ firmware { scm: scm { - compatible = "qcom,scm-msm8953"; + compatible = "qcom,scm-msm8953", "qcom,scm"; clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; @@ -795,7 +795,7 @@ }; }; - sdhc_1: sdhci@7824900 { + sdhc_1: mmc@7824900 { compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; reg = <0x7824900 0x500>, <0x7824000 0x800>; @@ -855,7 +855,7 @@ }; }; - sdhc_2: sdhci@7864900 { + sdhc_2: mmc@7864900 { compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; reg = <0x7864900 0x500>, <0x7864000 0x800>; diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi index 3b0cc85d6674..71e373b11de9 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi @@ -74,7 +74,7 @@ vdd_l17_29-supply = <&vph_pwr>; vdd_l20_21-supply = <&vph_pwr>; vdd_l25-supply = <&pm8994_s5>; - vdd_lvs1_2 = <&pm8994_s4>; + vdd_lvs1_2-supply = <&pm8994_s4>; /* S1, S2, S6 and S12 are managed by RPMPD */ diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts index 7748b745a5df..cbe11c060df9 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts @@ -51,13 +51,11 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button { label = "Volume Up"; gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -171,7 +169,7 @@ vdd_l17_29-supply = <&vph_pwr>; vdd_l20_21-supply = <&vph_pwr>; vdd_l25-supply = <&pm8994_s5>; - vdd_lvs1_2 = <&pm8994_s4>; + vdd_lvs1_2-supply = <&pm8994_s4>; /* S1, S2, S6 and S12 are managed by RPMPD */ diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index cc038f9b641f..61ec905025b0 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -64,7 +64,7 @@ compatible = "gpio-keys"; autorepeat; - volupkey { + volup-key { label = "Volume Up"; gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -73,7 +73,7 @@ debounce-interval = <15>; }; - camsnapkey { + camsnap-key { label = "Camera Snapshot"; gpios = <&pm8994_gpios 4 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -82,7 +82,7 @@ debounce-interval = <15>; }; - camfocuskey { + camfocus-key { label = "Camera Focus"; gpios = <&pm8994_gpios 5 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -100,7 +100,7 @@ label = "GPIO Hall Effect Sensor"; - hall-front-sensor { + event-hall-front-sensor { label = "Hall Effect Front Sensor"; gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; linux,input-type = <EV_SW>; @@ -108,7 +108,7 @@ linux,can-disable; }; - hall-back-sensor { + event-hall-back-sensor { label = "Hall Effect Back Sensor"; gpios = <&tlmm 75 GPIO_ACTIVE_HIGH>; linux,input-type = <EV_SW>; @@ -470,7 +470,7 @@ }; &pm8994_gpios { - bt_en_gpios: bt_en_gpios { + bt_en_gpios: bt-en-gpios-state { pinconf { pins = "gpio19"; function = PMIC_GPIO_FUNC_NORMAL; @@ -481,7 +481,7 @@ }; }; - divclk4_pin_a: divclk4 { + divclk4_pin_a: divclk4-state { pinconf { pins = "gpio18"; function = PMIC_GPIO_FUNC_FUNC2; @@ -519,21 +519,24 @@ * TODO: remove once a driver is available * TODO: add VBUS GPIO 5 */ - hd3ss460_pol: pol_low { + hd3ss460_pol: pol-low-state { pins = "gpio8"; - drive-strength = <3>; + function = PMIC_GPIO_FUNC_NORMAL; + qcom,drive-strength = <3>; bias-pull-down; }; - hd3ss460_amsel: amsel_high { + hd3ss460_amsel: amsel-high-state { pins = "gpio9"; - drive-strength = <1>; + function = PMIC_GPIO_FUNC_NORMAL; + qcom,drive-strength = <1>; bias-pull-up; }; - hd3ss460_en: en_high { + hd3ss460_en: en-high-state { pins = "gpio10"; - drive-strength = <1>; + function = PMIC_GPIO_FUNC_NORMAL; + qcom,drive-strength = <1>; bias-pull-up; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index e5a45af0bd12..f430d797196f 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -27,13 +27,11 @@ /* Kitakami firmware doesn't support PSCI */ /delete-node/ psci; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "Volume Down"; gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -42,7 +40,7 @@ debounce-interval = <15>; }; - button@1 { + button-1 { label = "Volume Up"; gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -51,7 +49,7 @@ debounce-interval = <15>; }; - button@2 { + button-2 { label = "Camera Snapshot"; gpios = <&pm8994_gpios 4 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -60,7 +58,7 @@ debounce-interval = <15>; }; - button@3 { + button-3 { label = "Camera Focus"; gpios = <&pm8994_gpios 5 GPIO_ACTIVE_LOW>; linux,input-type = <1>; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 0318d42c5736..8bc6c070e306 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -100,7 +100,7 @@ CPU6: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; + reg = <0x0 0x102>; enable-method = "psci"; next-level-cache = <&L2_1>; }; @@ -108,7 +108,7 @@ CPU7: cpu@103 { device_type = "cpu"; compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; + reg = <0x0 0x103>; enable-method = "psci"; next-level-cache = <&L2_1>; }; @@ -461,7 +461,7 @@ }; }; - sdhc1: sdhci@f9824900 { + sdhc1: mmc@f9824900 { compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -470,10 +470,10 @@ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; @@ -484,7 +484,7 @@ status = "disabled"; }; - sdhc2: sdhci@f98a4900 { + sdhc2: mmc@f98a4900 { compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -493,10 +493,10 @@ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; @@ -1069,11 +1069,12 @@ <600000000>; }; - ocmem: ocmem@fdd00000 { + ocmem: sram@fdd00000 { compatible = "qcom,msm8974-ocmem"; reg = <0xfdd00000 0x2000>, <0xfec00000 0x200000>; reg-names = "ctrl", "mem"; + ranges = <0 0xfec00000 0x200000>; clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, <&mmcc OCMEMCX_OCMEMNOC_CLK>; clock-names = "core", "iface"; diff --git a/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dts b/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dts deleted file mode 100644 index b018693600a5..000000000000 --- a/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> - */ - -#include "msm8996-sony-xperia-tone-dora.dts" -#include "pmi8996.dtsi" - -/ { - model = "Sony Xperia X Performance (PMI8996)"; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dts b/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dts deleted file mode 100644 index 842ea3cf557e..000000000000 --- a/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> - */ - -#include "msm8996-sony-xperia-tone-kagura.dts" -#include "pmi8996.dtsi" - -/ { - model = "Sony Xperia XZ (PMI8996)"; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dts b/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dts deleted file mode 100644 index b3f9062da4b0..000000000000 --- a/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> - */ - -#include "msm8996-sony-xperia-tone-keyaki.dts" -#include "pmi8996.dtsi" - -/ { - model = "Sony Xperia XZs (PMI8996)"; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index ca3c633f5a45..e165b5e890a0 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -8,6 +8,7 @@ #include "msm8996.dtsi" #include "pm8994.dtsi" #include "pmi8994.dtsi" +#include "pmi8996.dtsi" #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> @@ -20,7 +21,6 @@ / { qcom,msm-id = <246 0x30001>; /* MSM8996 V3.1 (Final) */ - qcom,pmic-id = <0x20009 0x2000a 0 0>; /* PM8994 + PMI8994 */ qcom,board-id = <8 0>; chosen { @@ -42,11 +42,6 @@ ecc-size = <16>; }; - cont_splash_mem: memory@83401000 { - reg = <0 0x83401000 0 0x23ff000>; - no-map; - }; - adsp_mem: adsp@8ea00000 { reg = <0x0 0x8ea00000 0x0 0x1a00000>; no-map; @@ -247,14 +242,14 @@ * probably a reason for it, and just to be on the safe side, we follow suit. */ pm8994_gpios_defaults: pm8994-gpios-default-state { - pm8994-gpio1-nc { + pm8994-gpio1-nc-pins { pins = "gpio1"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; bias-high-impedance; }; - vol-down-n { + vol-down-n-pins { pins = "gpio2"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -264,7 +259,7 @@ power-source = <PM8994_GPIO_S4>; }; - vol-up-n { + vol-up-n-pins { pins = "gpio3"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -273,7 +268,7 @@ power-source = <PM8994_GPIO_S4>; }; - camera-snapshot-n { + camera-snapshot-n-pins { pins = "gpio4"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -283,7 +278,7 @@ power-source = <PM8994_GPIO_S4>; }; - camera-focus-n { + camera-focus-n-pins { pins = "gpio5"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -293,7 +288,7 @@ power-source = <PM8994_GPIO_S4>; }; - pm8994-gpio6-nc { + pm8994-gpio6-nc-pins { pins = "gpio6"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -301,7 +296,7 @@ power-source = <PM8994_GPIO_VPH>; }; - nfc-download { + nfc-download-pins { pins = "gpio7"; function = PMIC_GPIO_FUNC_NORMAL; output-low; @@ -311,7 +306,7 @@ power-source = <PM8994_GPIO_S4>; }; - pm8994-gpio8-nc { + pm8994-gpio8-nc-pins { pins = "gpio8"; function = PMIC_GPIO_FUNC_NORMAL; output-low; @@ -321,7 +316,7 @@ power-source = <PM8994_GPIO_VPH>; }; - pm8994-gpio9-nc { + pm8994-gpio9-nc-pins { pins = "gpio9"; function = PMIC_GPIO_FUNC_NORMAL; output-high; @@ -331,7 +326,7 @@ power-source = <PM8994_GPIO_VPH>; }; - nfc-clock { + nfc-clock-pins { pins = "gpio10"; function = PMIC_GPIO_FUNC_NORMAL; input-enable; @@ -341,7 +336,7 @@ power-source = <PM8994_GPIO_S4>; }; - pm8994-gpio11-nc { + pm8994-gpio11-nc-pins { pins = "gpio11"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -349,7 +344,7 @@ power-source = <PM8994_GPIO_VPH>; }; - pm8994-gpio12-nc { + pm8994-gpio12-nc-pins { pins = "gpio12"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -357,7 +352,7 @@ power-source = <PM8994_GPIO_VPH>; }; - ear-enable { + ear-enable-pins { pins = "gpio13"; function = PMIC_GPIO_FUNC_NORMAL; output-high; @@ -367,7 +362,7 @@ power-source = <PM8994_GPIO_S4>; }; - pm8994-gpio14-nc { + pm8994-gpio14-nc-pins { pins = "gpio14"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -377,7 +372,7 @@ power-source = <PM8994_GPIO_VPH>; }; - pm-divclk1-gpio { + pm-divclk1-gpio-pins { pins = "gpio15"; function = "func1"; output-high; @@ -387,13 +382,13 @@ power-source = <PM8994_GPIO_VPH>; }; - pmi-clk-gpio { + pmi-clk-gpio-pins { pins = "gpio16"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; }; - pm8994-gpio17-nc { + pm8994-gpio17-nc-pins { pins = "gpio17"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -401,7 +396,7 @@ power-source = <PM8994_GPIO_VPH>; }; - rome-sleep { + rome-sleep-pins { pins = "gpio18"; function = PMIC_GPIO_FUNC_FUNC2; output-low; @@ -411,7 +406,7 @@ power-source = <PM8994_GPIO_S4>; }; - pm8994-gpio19-nc { + pm8994-gpio19-nc-pins { pins = "gpio19"; function = PMIC_GPIO_FUNC_NORMAL; output-low; @@ -421,7 +416,7 @@ power-source = <PM8994_GPIO_VPH>; }; - pm8994-gpio22-nc { + pm8994-gpio22-nc-pins { pins = "gpio22"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -446,34 +441,34 @@ "RF_ID"; pm8994_mpps_defaults: pm8994-mpps-default-state { - lcd-id_adc-mpp { + lcd-id_adc-mpp-pins { pins = "mpp2"; function = "analog"; input-enable; qcom,amux-route = <PMIC_MPP_AMUX_ROUTE_CH6>; }; - pm-mpp4-nc { + pm-mpp4-nc-pins { pins = "mpp4"; function = "digital"; bias-high-impedance; power-source = <PM8994_GPIO_VPH>; }; - flash-therm-mpp { + flash-therm-mpp-pins { pins = "mpp5"; function = "analog"; input-enable; qcom,amux-route = <PMIC_MPP_AMUX_ROUTE_CH5>; }; - mpp6-nc { + mpp6-nc-pins { pins = "mpp6"; function = "digital"; bias-high-impedance; }; - rf-id-mpp { + rf-id-mpp-pins { pins = "mpp8"; function = "analog"; input-enable; @@ -504,7 +499,7 @@ "NC"; pmi8994_gpios_defaults: pmi8994-gpios-default-state { - vib-ldo-en-gpio { + vib-ldo-en-gpio-pins { pins = "gpio1"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -513,7 +508,7 @@ power-source = <PM8994_GPIO_S4>; }; - pmi-gpio2-nc { + pmi-gpio2-nc-pins { pins = "gpio2"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -523,7 +518,7 @@ power-source = <PM8994_GPIO_VPH>; }; - pmi-gpio3-nc { + pmi-gpio3-nc-pins { pins = "gpio3"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -533,7 +528,7 @@ power-source = <PM8994_GPIO_VPH>; }; - pmi-gpio4-nc { + pmi-gpio4-nc-pins { pins = "gpio4"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -542,7 +537,7 @@ power-source = <PM8994_GPIO_S4>; }; - pmi-gpio5-nc { + pmi-gpio5-nc-pins { pins = "gpio5"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -551,7 +546,7 @@ power-source = <PM8994_GPIO_S4>; }; - pmi-gpio6-nc { + pmi-gpio6-nc-pins { pins = "gpio6"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -560,7 +555,7 @@ power-source = <PM8994_GPIO_S4>; }; - pmi-gpio7-nc { + pmi-gpio7-nc-pins { pins = "gpio7"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -569,7 +564,7 @@ power-source = <PM8994_GPIO_S4>; }; - pmi-gpio8-nc { + pmi-gpio8-nc-pins { pins = "gpio8"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -578,13 +573,13 @@ power-source = <PM8994_GPIO_S4>; }; - usb-switch-sel { + usb-switch-sel-pins { pins = "gpio9"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; }; - pmi-gpio10-nc { + pmi-gpio10-nc-pins { pins = "gpio10"; function = PMIC_GPIO_FUNC_NORMAL; output-low; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index a7090befc16f..627649979891 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -38,10 +38,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - vol_up { + key-vol-up { label = "Volume Up"; gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -49,7 +49,7 @@ debounce-interval = <15>; }; - dome { + key-dome { label = "Home"; gpios = <&tlmm 34 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; @@ -608,7 +608,7 @@ }; &pm8994_gpios { - wlan_en_default: wlan-en-default { + wlan_en_default: wlan-en-state { pins = "gpio8"; function = PMIC_GPIO_FUNC_NORMAL; output-low; @@ -617,7 +617,7 @@ bias-disable; }; - rome_enable_default: rome-enable-default { + rome_enable_default: rome-enable-state { pins = "gpio9"; function = PMIC_GPIO_FUNC_NORMAL; output-high; @@ -625,7 +625,7 @@ power-source = <PM8994_GPIO_VPH>; }; - divclk1_default: divclk1_default { + divclk1_default: divclk1-state { pins = "gpio15"; function = PMIC_GPIO_FUNC_FUNC1; bias-disable; @@ -633,7 +633,7 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; }; - divclk4_pin_a: divclk4 { + divclk4_pin_a: divclk4-state { pins = "gpio18"; function = PMIC_GPIO_FUNC_FUNC2; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index 22978d06f85b..25f30ec277c1 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -156,7 +156,7 @@ &sound { compatible = "qcom,apq8096-sndcard"; model = "gemini"; - audio-routing = "RX_BIAS", "MCLK", + audio-routing = "RX_BIAS", "MCLK", "MM_DL1", "MultiMedia1 Playback", "MM_DL2", "MultiMedia2 Playback", "MultiMedia3 Capture", "MM_UL3"; @@ -257,7 +257,7 @@ "UIM_BATT_ALARM", /* GPIO_21 */ "NC"; /* GPIO_22 */ - divclk2_pin_a: divclk2 { + divclk2_pin_a: divclk2-state { pins = "gpio16"; function = PMIC_GPIO_FUNC_FUNC2; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts new file mode 100644 index 000000000000..ff4673ee9e81 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Alec Su <ae40515@yahoo.com.tw> + */ + +/dts-v1/; + +#include "msm8996-xiaomi-common.dtsi" +#include "pmi8996.dtsi" +#include <dt-bindings/sound/qcom,q6afe.h> +#include <dt-bindings/sound/qcom,q6asm.h> + +/ { + model = "Xiaomi Mi 5s Plus"; + compatible = "xiaomi,natrium", "qcom,msm8996"; + chassis-type = "handset"; + qcom,msm-id = <305 0x10000>; + qcom,board-id = <47 0>; +}; + +&adsp_pil { + firmware-name = "qcom/msm8996/natrium/adsp.mbn"; +}; + +&blsp2_i2c6 { + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <125 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vdd_3v2_tp>; + syna,reset-delay-ms = <200>; + syna,startup-delay-ms = <5>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touchscreen_default>; + pinctrl-1 = <&touchscreen_sleep>; + }; +}; + +&dsi0 { + status = "okay"; + + vdda-supply = <&vreg_l2a_1p25>; + vcca-supply = <&vreg_l28a_0p925>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mdss_dsi_default &mdss_te_default>; + pinctrl-1 = <&mdss_dsi_sleep &mdss_te_sleep>; + + panel: panel@0 { + compatible = "jdi,fhd-r63452"; + reg = <0>; + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + backlight = <&pmi8994_wled>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_out { + remote-endpoint = <&panel_in>; +}; + +&gpu { + zap-shader { + firmware-name = "qcom/msm8996/natrium/a530_zap.mbn"; + }; +}; + +&mss_pil { + firmware-name = "qcom/msm8996/natrium/mba.mbn", + "qcom/msm8996/natrium/modem.mbn"; +}; + +&pmi8994_wled { + status = "okay"; + + qcom,enabled-strings = <0 1>; + qcom,switching-freq = <600>; +}; + +&q6asmdai { + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; +}; + +&slpi_pil { + firmware-name = "qcom/msm8996/natrium/slpi.mbn"; +}; + +&sound { + compatible = "qcom,apq8096-sndcard"; + model = "natrium"; + audio-routing = "RX_BIAS", "MCLK"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + slim-dai-link { + link-name = "SLIM Playback"; + cpu { + sound-dai = <&q6afedai SLIMBUS_6_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9335 6>; + }; + }; + + slimcap-dai-link { + link-name = "SLIM Capture"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9335 1>; + }; + }; +}; + +&venus { + firmware-name = "qcom/msm8996/natrium/venus.mbn"; +}; + +&rpm_requests { + pm8994-regulators { + vreg_l3a_0p875: l3 { + regulator-name = "vreg_l3a_0p875"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; + vreg_l11a_1p1: l11 { + regulator-name = "vreg_l11a_1p1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + vreg_l17a_2p8: l17 { + regulator-name = "vreg_l17a_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + vreg_l18a_2p8: l18 { + regulator-name = "vreg_l18a_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + vreg_l29a_2p8: l29 { + regulator-name = "vreg_l29a_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + }; +}; + +&pm8994_gpios { + gpio-line-names = + "NC", /* GPIO_1 */ + "VOL_UP_N", /* GPIO_2 */ + "SPKR_ID", /* GPIO_3 */ + "PWM_HAPTICS", /* GPIO_4 */ + "INFARED_DRV", /* GPIO_5 */ + "NC", /* GPIO_6 */ + "KEYPAD_LED_EN_A", /* GPIO_7 */ + "WL_EN", /* GPIO_8 */ + "3P3_ENABLE", /* GPIO_9 */ + "NC", /* GPIO_10 */ + "NC", /* GPIO_11 */ + "NC", /* GPIO_12 */ + "NC", /* GPIO_13 */ + "NC", /* GPIO_14 */ + "DIVCLK1_CDC", /* GPIO_15 */ + "DIVCLK2_HAPTICS", /* GPIO_16 */ + "NC", /* GPIO_17 */ + "32KHz_CLK_IN", /* GPIO_18 */ + "BT_EN", /* GPIO_19 */ + "PMIC_SLB", /* GPIO_20 */ + "UIM_BATT_ALARM", /* GPIO_21 */ + "NC"; /* GPIO_22 */ +}; + +&pm8994_mpps { + gpio-line-names = + "NC", /* MPP_1 */ + "CCI_TIMER1", /* MPP_2 */ + "PMIC_SLB", /* MPP_3 */ + "EXT_FET_WLED_PWR_EN_N",/* MPP_4 */ + "NC", /* MPP_5 */ + "NC", /* MPP_6 */ + "NC", /* MPP_7 */ + "NC"; /* MPP_8 */ +}; + +&pmi8994_gpios { + gpio-line-names = + "NC", /* GPIO_1 */ + "SPKR_PA_EN", /* GPIO_2 */ + "NC", /* GPIO_3 */ + "NC", /* GPIO_4 */ + "NC", /* GPIO_5 */ + "NC", /* GPIO_6 */ + "NC", /* GPIO_7 */ + "NC", /* GPIO_8 */ + "NC", /* GPIO_9 */ + "NC"; /* GPIO_10 */ +}; + +&tlmm { + gpio-line-names = + "ESE_SPI_MOSI", /* GPIO_0 */ + "ESE_SPI_MISO", /* GPIO_1 */ + "NC", /* GPIO_2 */ + "ESE_SPI_CLK", /* GPIO_3 */ + "MSM_UART_TX", /* GPIO_4 */ + "MSM_UART_RX", /* GPIO_5 */ + "NFC_I2C_SDA", /* GPIO_6 */ + "NFC_I2C_SCL", /* GPIO_7 */ + "LCD0_RESET_N", /* GPIO_8 */ + "NFC_IRQ", /* GPIO_9 */ + "LCD_TE", /* GPIO_10 */ + "LCD_ID_DET1", /* GPIO_11 */ + "NFC_DISABLE", /* GPIO_12 */ + "CAM_MCLK0", /* GPIO_13 */ + "CAM_MCLK1", /* GPIO_14 */ + "CAM_MCLK2", /* GPIO_15 */ + "ESE_PWR_REQ", /* GPIO_16 */ + "CCI_I2C_SDA0", /* GPIO_17 */ + "CCI_I2C_SCL0", /* GPIO_18 */ + "CCI_I2C_SDA1", /* GPIO_19 */ + "CCI_I2C_SCL1", /* GPIO_20 */ + "NFC_DWL_REQ", /* GPIO_21 */ + "CCI_TIMER1", /* GPIO_22 */ + "WEBCAM1_RESET_N", /* GPIO_23 */ + "ESE_IRQ", /* GPIO_24 */ + "NC", /* GPIO_25 */ + "WEBCAM1_STANDBY", /* GPIO_26 */ + "NC", /* GPIO_27 */ + "NC", /* GPIO_28 */ + "NC", /* GPIO_29 */ + "CAM_VDD_1P2_EN_2", /* GPIO_30 */ + "CAM_RESET_0", /* GPIO_31 */ + "CAM_RESET_1", /* GPIO_32 */ + "NC", /* GPIO_33 */ + "NC", /* GPIO_34 */ + "PCI_E0_RST_N", /* GPIO_35 */ + "PCI_E0_CLKREQ_N", /* GPIO_36 */ + "PCI_E0_WAKE", /* GPIO_37 */ + "CHARGER_INT", /* GPIO_38 */ + "CHARGER_RESET", /* GPIO_39 */ + "NC", /* GPIO_40 */ + "QCA_UART_TXD", /* GPIO_41 */ + "QCA_UART_RXD", /* GPIO_42 */ + "QCA_UART_CTS", /* GPIO_43 */ + "QCA_UART_RTS", /* GPIO_44 */ + "MAWC_UART_TX", /* GPIO_45 */ + "MAWC_UART_RX", /* GPIO_46 */ + "NC", /* GPIO_47 */ + "NC", /* GPIO_48 */ + "NC", /* GPIO_49 */ + "FP_SPI_RST", /* GPIO_50 */ + "TYPEC_I2C_SDA", /* GPIO_51 */ + "TYPEC_I2C_SCL", /* GPIO_52 */ + "CODEC_INT2_N", /* GPIO_53 */ + "CODEC_INT1_N", /* GPIO_54 */ + "APPS_I2C7_SDA", /* GPIO_55 */ + "APPS_I2C7_SCL", /* GPIO_56 */ + "FORCE_USB_BOOT", /* GPIO_57 */ + "NC", /* GPIO_58 */ + "NC", /* GPIO_59 */ + "NC", /* GPIO_60 */ + "NC", /* GPIO_61 */ + "ESE_RSTN", /* GPIO_62 */ + "TYPEC_INT", /* GPIO_63 */ + "CODEC_RESET_N", /* GPIO_64 */ + "PCM_CLK", /* GPIO_65 */ + "PCM_SYNC", /* GPIO_66 */ + "PCM_DIN", /* GPIO_67 */ + "PCM_DOUT", /* GPIO_68 */ + "CDC_44K1_CLK", /* GPIO_69 */ + "SLIMBUS_CLK", /* GPIO_70 */ + "SLIMBUS_DATA0", /* GPIO_71 */ + "SLIMBUS_DATA1", /* GPIO_72 */ + "LDO_5V_IN_EN", /* GPIO_73 */ + "TYPEC_EN_N", /* GPIO_74 */ + "NC", /* GPIO_75 */ + "NC", /* GPIO_76 */ + "NC", /* GPIO_77 */ + "NC", /* GPIO_78 */ + "NC", /* GPIO_79 */ + "SENSOR_RESET_N", /* GPIO_80 */ + "FP_SPI_MOSI", /* GPIO_81 */ + "FP_SPI_MISO", /* GPIO_82 */ + "FP_SPI_CS_N", /* GPIO_83 */ + "FP_SPI_CLK", /* GPIO_84 */ + "NC", /* GPIO_85 */ + "CAM_VDD_1P2_EN", /* GPIO_86 */ + "MSM_TS_I2C_SDA", /* GPIO_87 */ + "MSM_TS_I2C_SCL", /* GPIO_88 */ + "TS_RESOUT_N", /* GPIO_89 */ + "ESE_SPI_CS_N", /* GPIO_90 */ + "NC", /* GPIO_91 */ + "CAM2_AVDD_EN", /* GPIO_92 */ + "CAM2_VCM_EN", /* GPIO_93 */ + "NC", /* GPIO_94 */ + "NC", /* GPIO_95 */ + "NC", /* GPIO_96 */ + "GRFC_0", /* GPIO_97 */ + "GRFC_1", /* GPIO_98 */ + "NC", /* GPIO_99 */ + "GRFC_3", /* GPIO_100 */ + "GRFC_4", /* GPIO_101 */ + "GRFC_5", /* GPIO_102 */ + "NC", /* GPIO_103 */ + "GRFC_7", /* GPIO_104 */ + "UIM2_DATA", /* GPIO_105 */ + "UIM2_CLK", /* GPIO_106 */ + "UIM2_RESET", /* GPIO_107 */ + "UIM2_PRESENT", /* GPIO_108 */ + "UIM1_DATA", /* GPIO_109 */ + "UIM1_CLK", /* GPIO_110 */ + "UIM1_RESET", /* GPIO_111 */ + "UIM1_PRESENT", /* GPIO_112 */ + "UIM_BATT_ALARM", /* GPIO_113 */ + "GRFC_8", /* GPIO_114 */ + "GRFC_9", /* GPIO_115 */ + "TX_GTR_THRES", /* GPIO_116 */ + "ACCEL_INT", /* GPIO_117 */ + "GYRO_INT", /* GPIO_118 */ + "COMPASS_INT", /* GPIO_119 */ + "PROXIMITY_INT_N", /* GPIO_120 */ + "FP_IRQ", /* GPIO_121 */ + "P_SENSE", /* GPIO_122 */ + "HALL_INTR2", /* GPIO_123 */ + "HALL_INTR1", /* GPIO_124 */ + "TS_INT_N", /* GPIO_125 */ + "NC", /* GPIO_126 */ + "GRFC_11", /* GPIO_127 */ + "NC", /* GPIO_128 */ + "EXT_GPS_LNA_EN", /* GPIO_129 */ + "NC", /* GPIO_130 */ + "LCD_ID_DET2", /* GPIO_131 */ + "LCD_TE2", /* GPIO_132 */ + "GRFC_14", /* GPIO_133 */ + "GSM_TX2_PHASE_D", /* GPIO_134 */ + "NC", /* GPIO_135 */ + "GRFC_15", /* GPIO_136 */ + "RFFE3_DATA", /* GPIO_137 */ + "RFFE3_CLK", /* GPIO_138 */ + "NC", /* GPIO_139 */ + "NC", /* GPIO_140 */ + "RFFE5_DATA", /* GPIO_141 */ + "RFFE5_CLK", /* GPIO_142 */ + "NC", /* GPIO_143 */ + "COEX_UART_TX", /* GPIO_144 */ + "COEX_UART_RX", /* GPIO_145 */ + "RFFE2_DATA", /* GPIO_146 */ + "RFFE2_CLK", /* GPIO_147 */ + "RFFE1_DATA", /* GPIO_148 */ + "RFFE1_CLK"; /* GPIO_149 */ + + touchscreen_default: touchscreen-default { + pins = "gpio89", "gpio125"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; + + touchscreen_sleep: touchscreen-sleep { + pins = "gpio89", "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts index 1e2dd6763ad1..30a9e4bed4af 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts @@ -137,7 +137,7 @@ &sound { compatible = "qcom,apq8096-sndcard"; model = "scorpio"; - audio-routing = "RX_BIAS", "MCLK"; + audio-routing = "RX_BIAS", "MCLK"; mm1-dai-link { link-name = "MultiMedia1"; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 9932186f7ceb..742eac4ce9b3 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/qcom,gcc-msm8996.h> #include <dt-bindings/clock/qcom,mmcc-msm8996.h> #include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/interconnect/qcom,msm8996.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,apr.h> #include <dt-bindings/thermal/thermal.h> @@ -357,7 +358,7 @@ firmware { scm { - compatible = "qcom,scm-msm8996"; + compatible = "qcom,scm-msm8996", "qcom,scm"; qcom,dload-mode = <&tcsr 0x13000>; }; }; @@ -463,6 +464,8 @@ rpmcc: qcom,rpmcc { compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; }; rpmpd: power-controller { @@ -585,12 +588,12 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; - pcie_phy: phy@34000 { + pcie_phy: phy-wrapper@34000 { compatible = "qcom,msm8996-qmp-pcie-phy"; reg = <0x00034000 0x488>; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0x0 0x00034000 0x4000>; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, @@ -601,46 +604,55 @@ <&gcc GCC_PCIE_PHY_COM_BCR>, <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; reset-names = "phy", "common", "cfg"; + status = "disabled"; - pciephy_0: phy@35000 { - reg = <0x00035000 0x130>, - <0x00035200 0x200>, - <0x00035400 0x1dc>; - #phy-cells = <0>; + pciephy_0: phy@1000 { + reg = <0x1000 0x130>, + <0x1200 0x200>, + <0x1400 0x1dc>; - #clock-cells = <1>; - clock-output-names = "pcie_0_pipe_clk_src"; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "pipe0"; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "lane0"; - }; - pciephy_1: phy@36000 { - reg = <0x00036000 0x130>, - <0x00036200 0x200>, - <0x00036400 0x1dc>; + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk_src"; + #phy-cells = <0>; + }; + + pciephy_1: phy@2000 { + reg = <0x2000 0x130>, + <0x2200 0x200>, + <0x2400 0x1dc>; - clock-output-names = "pcie_1_pipe_clk_src"; clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; clock-names = "pipe1"; resets = <&gcc GCC_PCIE_1_PHY_BCR>; reset-names = "lane1"; - }; - pciephy_2: phy@37000 { - reg = <0x00037000 0x130>, - <0x00037200 0x200>, - <0x00037400 0x1dc>; + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk_src"; + #phy-cells = <0>; + }; + + pciephy_2: phy@3000 { + reg = <0x3000 0x130>, + <0x3200 0x200>, + <0x3400 0x1dc>; - clock-output-names = "pcie_2_pipe_clk_src"; clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; clock-names = "pipe2"; resets = <&gcc GCC_PCIE_2_PHY_BCR>; reset-names = "lane2"; + + #clock-cells = <0>; + clock-output-names = "pcie_2_pipe_clk_src"; + + #phy-cells = <0>; }; }; @@ -650,7 +662,7 @@ }; qfprom@74000 { - compatible = "qcom,qfprom"; + compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; reg = <0x00074000 0x8ff>; #address-cells = <1>; #size-cells = <1>; @@ -687,8 +699,31 @@ clocks = <&rpmcc RPM_SMD_BB_CLK1>, <&rpmcc RPM_SMD_LN_BB_CLK>, - <&sleep_clk>; - clock-names = "cxo", "cxo2", "sleep_clk"; + <&sleep_clk>, + <&pciephy_0>, + <&pciephy_1>, + <&pciephy_2>, + <&ssusb_phy_0>, + <0>, <0>, <0>; + clock-names = "cxo", + "cxo2", + "sleep_clk", + "pcie_0_pipe_clk_src", + "pcie_1_pipe_clk_src", + "pcie_2_pipe_clk_src", + "usb3_phy_pipe_clk_src", + "ufs_rx_symbol_0_clk_src", + "ufs_rx_symbol_1_clk_src", + "ufs_tx_symbol_0_clk_src"; + }; + + bimc: interconnect@408000 { + compatible = "qcom,msm8996-bimc"; + reg = <0x00408000 0x5a000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; }; tsens0: thermal-sensor@4a9000 { @@ -735,6 +770,74 @@ dma-names = "rx", "tx"; }; + cnoc: interconnect@500000 { + compatible = "qcom,msm8996-cnoc"; + reg = <0x00500000 0x1000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, + <&rpmcc RPM_SMD_CNOC_A_CLK>; + }; + + snoc: interconnect@524000 { + compatible = "qcom,msm8996-snoc"; + reg = <0x00524000 0x1c000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + + a0noc: interconnect@543000 { + compatible = "qcom,msm8996-a0noc"; + reg = <0x00543000 0x6000>; + #interconnect-cells = <1>; + clock-names = "aggre0_snoc_axi", + "aggre0_cnoc_ahb", + "aggre0_noc_mpu_cfg"; + clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, + <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, + <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; + power-domains = <&gcc AGGRE0_NOC_GDSC>; + }; + + a1noc: interconnect@562000 { + compatible = "qcom,msm8996-a1noc"; + reg = <0x00562000 0x5000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, + <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; + }; + + a2noc: interconnect@583000 { + compatible = "qcom,msm8996-a2noc"; + reg = <0x00583000 0x7000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, + <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>; + }; + + mnoc: interconnect@5a4000 { + compatible = "qcom,msm8996-mnoc"; + reg = <0x005a4000 0x1c000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a", "iface"; + clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, + <&rpmcc RPM_SMD_MMAXI_A_CLK>, + <&mmcc AHB_CLK_SRC>; + }; + + pnoc: interconnect@5c0000 { + compatible = "qcom,msm8996-pnoc"; + reg = <0x005c0000 0x3000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_PCNOC_A_CLK>; + }; + tcsr_mutex_regs: syscon@740000 { compatible = "syscon"; reg = <0x00740000 0x40000>; @@ -751,6 +854,22 @@ #reset-cells = <1>; #power-domain-cells = <1>; reg = <0x008c0000 0x40000>; + clocks = <&xo_board>, + <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, + <&gcc GPLL0>, + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <0>, + <0>, + <0>; + clock-names = "xo", + "gcc_mmss_noc_cfg_ahb_clk", + "gpll0", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte", + "hdmipll"; assigned-clocks = <&mmcc MMPLL9_PLL>, <&mmcc MMPLL1_PLL>, <&mmcc MMPLL3_PLL>, @@ -779,8 +898,9 @@ interrupt-controller; #interrupt-cells = <1>; - clocks = <&mmcc MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_MDP_CLK>; + clock-names = "iface", "core"; #address-cells = <1>; #size-cells = <1>; @@ -814,6 +934,11 @@ assigned-clock-rates = <300000000>, <19200000>; + interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, + <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, + <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; + interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -831,6 +956,13 @@ remote-endpoint = <&dsi0_in>; }; }; + + port@2 { + reg = <2>; + mdp5_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; }; }; @@ -856,6 +988,8 @@ "core_mmss", "pixel", "core"; + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; phys = <&dsi0_phy>; phy-names = "dsi"; @@ -900,6 +1034,74 @@ status = "disabled"; }; + dsi1: dsi@996000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x00996000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_BYTE1_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>, + <&mmcc MDSS_PCLK1_CLK>, + <&mmcc MDSS_ESC1_CLK>; + clock-names = "mdp_core", + "byte", + "iface", + "bus", + "core_mmss", + "pixel", + "core"; + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@996400 { + compatible = "qcom,dsi-phy-14nm"; + reg = <0x00996400 0x100>, + <0x00996500 0x300>, + <0x00996800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; + clock-names = "iface", "ref"; + status = "disabled"; + }; + hdmi: hdmi-tx@9a0000 { compatible = "qcom,hdmi-tx-8996"; reg = <0x009a0000 0x50c>, @@ -925,7 +1127,6 @@ "extp"; phys = <&hdmi_phy>; - phy-names = "hdmi_phy"; #sound-dai-cells = <1>; status = "disabled"; @@ -988,6 +1189,9 @@ "mem", "mem_iface"; + interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; + interconnect-names = "gfx-mem"; + power-domains = <&mmcc GPU_GX_GDSC>; iommus = <&adreno_smmu 0>; @@ -1001,7 +1205,7 @@ #cooling-cells = <2>; gpu_opp_table: opp-table { - compatible ="operating-points-v2"; + compatible = "operating-points-v2"; /* * 624Mhz and 560Mhz are only available on speed @@ -1623,7 +1827,7 @@ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_AXI_CLK>; - clock-names = "pipe", + clock-names = "pipe", "aux", "cfg", "bus_master", @@ -1637,7 +1841,7 @@ bus-range = <0x00 0xff>; num-lanes = <1>; - status = "disabled"; + status = "disabled"; reg = <0x00608000 0x2000>, <0x0d000000 0xf1d>, @@ -1677,7 +1881,7 @@ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_AXI_CLK>; - clock-names = "pipe", + clock-names = "pipe", "aux", "cfg", "bus_master", @@ -1727,7 +1931,7 @@ <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, <&gcc GCC_PCIE_2_SLV_AXI_CLK>; - clock-names = "pipe", + clock-names = "pipe", "aux", "cfg", "bus_master", @@ -2013,6 +2217,9 @@ <&mmcc VIDEO_AXI_CLK>, <&mmcc VIDEO_MAXI_CLK>; clock-names = "core", "iface", "bus", "mbus"; + interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; + interconnect-names = "video-mem", "cpu-cfg"; iommus = <&venus_smmu 0x00>, <&venus_smmu 0x01>, <&venus_smmu 0x0a>, @@ -2732,6 +2939,10 @@ <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <120000000>; + interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; + interconnect-names = "usb-ddr", "apps-usb"; + power-domains = <&gcc USB30_GDSC>; status = "disabled"; @@ -2769,7 +2980,7 @@ <0x07410600 0x1a8>; #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clock-output-names = "usb3_phy_pipe_clk_src"; clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; clock-names = "pipe0"; @@ -2804,7 +3015,7 @@ status = "disabled"; }; - sdhc1: sdhci@7464900 { + sdhc1: mmc@7464900 { compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07464900 0x11c>, <0x07464000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -2817,6 +3028,7 @@ clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; + resets = <&gcc GCC_SDCC1_BCR>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_state_on>; @@ -2827,7 +3039,7 @@ status = "disabled"; }; - sdhc2: sdhci@74a4900 { + sdhc2: mmc@74a4900 { compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg = <0x074a4900 0x314>, <0x074a4000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -2840,6 +3052,7 @@ clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; + resets = <&gcc GCC_SDCC2_BCR>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_state_on>; @@ -3084,7 +3297,7 @@ compatible = "qcom,bam-v1.7.0"; qcom,controlled-remotely; reg = <0x09184000 0x32000>; - num-channels = <31>; + num-channels = <31>; interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; qcom,ee = <1>; @@ -3096,7 +3309,7 @@ reg = <0x091c0000 0x2C000>; reg-names = "ctrl"; interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&slimbam 3>, <&slimbam 4>, + dmas = <&slimbam 3>, <&slimbam 4>, <&slimbam 5>, <&slimbam 6>; dma-names = "rx", "tx", "tx2", "rx2"; #address-cells = <1>; @@ -3108,7 +3321,7 @@ tasha_ifd: tas-ifd { compatible = "slim217,1a0"; - reg = <0 0>; + reg = <0 0>; }; wcd9335: codec@1{ @@ -3116,17 +3329,17 @@ pinctrl-names = "default"; compatible = "slim217,1a0"; - reg = <1 0>; + reg = <1 0>; interrupt-parent = <&tlmm>; interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, <53 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "intr1", "intr2"; + interrupt-names = "intr1", "intr2"; interrupt-controller; #interrupt-cells = <1>; reset-gpios = <&tlmm 64 0>; - slim-ifc-dev = <&tasha_ifd>; + slim-ifc-dev = <&tasha_ifd>; #sound-dai-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dts b/arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dts index e204b7050441..102f3e9a79a1 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dts @@ -16,20 +16,22 @@ touchpad@15 { compatible = "hid-over-i2c"; - interrupt-parent = <&tlmm>; - interrupts = <0x7b IRQ_TYPE_LEVEL_LOW>; reg = <0x15>; - hid-descr-addr = <0x0001>; - pinctrl-names = "default"; pinctrl-0 = <&touchpad>; + + interrupt-parent = <&tlmm>; + interrupts = <123 IRQ_TYPE_LEVEL_LOW>; + + hid-descr-addr = <0x0001>; }; keyboard@3a { compatible = "hid-over-i2c"; - interrupt-parent = <&tlmm>; - interrupts = <0x25 IRQ_TYPE_LEVEL_LOW>; reg = <0x3a>; + interrupt-parent = <&tlmm>; + interrupts = <37 IRQ_TYPE_LEVEL_LOW>; + hid-descr-addr = <0x0001>; }; }; @@ -37,12 +39,3 @@ &sdhc2 { cd-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; }; - -&tlmm { - touchpad: touchpad { - config { - pins = "gpio123"; - bias-pull-up; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi b/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi index b3b352530d76..7928b8197474 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi @@ -8,13 +8,10 @@ */ #include "msm8998.dtsi" -#include "pm8998.dtsi" #include "pm8005.dtsi" +#include "pm8998.dtsi" / { - chosen { - }; - vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -37,6 +34,28 @@ }; }; +&blsp1_uart3_on { + rx { + /delete-property/ bias-disable; + /* + * Configure a pull-up on 45 (RX). This is needed to + * avoid garbage data when the TX pin of the Bluetooth + * module is in tri-state (module powered off or not + * driving the signal yet). + */ + bias-pull-up; + }; + + cts { + /delete-property/ bias-disable; + /* + * Configure a pull-down on 47 (CTS) to match the pull + * of the Bluetooth module. + */ + bias-pull-down; + }; +}; + /* * The laptop FW does not appear to support the retention state as it is * not advertised as enabled in ACPI, and enabling it in DT can cause boot @@ -74,6 +93,20 @@ cpu-idle-states = <&BIG_CPU_SLEEP_1>; }; +/* + * If EFIFB is used, enabling MMCC will cause important MMSS clocks to be cleaned + * up, because as far as Linux is concerned - they are unused. Disable it by default + * on clamshell devices, as it will break them, unless either simplefb is configured to + * hold a vote for these clocks, or panels are brought up properly, using drm/msm. + */ +&mmcc { + status = "disabled"; +}; + +&mmss_smmu { + status = "disabled"; +}; + &pcie0 { status = "okay"; }; @@ -82,20 +115,16 @@ status = "okay"; }; -&pm8005_lsid1 { - pm8005-regulators { - compatible = "qcom,pm8005-regulators"; +&pm8005_regulators { + vdd_s1-supply = <&vph_pwr>; - vdd_s1-supply = <&vph_pwr>; + pm8005_s1: s1 { /* VDD_GFX supply */ + regulator-min-microvolt = <524000>; + regulator-max-microvolt = <1100000>; + regulator-enable-ramp-delay = <500>; - pm8005_s1: s1 { /* VDD_GFX supply */ - regulator-min-microvolt = <524000>; - regulator-max-microvolt = <1100000>; - regulator-enable-ramp-delay = <500>; - - /* hack until we rig up the gpu consumer */ - regulator-always-on; - }; + /* hack until we rig up the gpu consumer */ + regulator-always-on; }; }; @@ -143,127 +172,156 @@ regulator-min-microvolt = <1352000>; regulator-max-microvolt = <1352000>; }; + vreg_s4a_1p8: s4 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-allow-set-load; }; + vreg_s5a_2p04: s5 { regulator-min-microvolt = <1904000>; regulator-max-microvolt = <2040000>; }; + vreg_s7a_1p025: s7 { regulator-min-microvolt = <900000>; regulator-max-microvolt = <1028000>; }; + vreg_l1a_0p875: l1 { regulator-min-microvolt = <880000>; regulator-max-microvolt = <880000>; regulator-allow-set-load; }; + vreg_l2a_1p2: l2 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-allow-set-load; }; + vreg_l3a_1p0: l3 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; + vreg_l5a_0p8: l5 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <800000>; }; + vreg_l6a_1p8: l6 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <1808000>; }; + vreg_l7a_1p8: l7 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-allow-set-load; }; + vreg_l8a_1p2: l8 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; + vreg_l9a_1p8: l9 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <2960000>; }; + vreg_l10a_1p8: l10 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <2960000>; }; + vreg_l11a_1p0: l11 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; + vreg_l12a_1p8: l12 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + vreg_l13a_2p95: l13 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <2960000>; }; + vreg_l14a_1p88: l14 { regulator-min-microvolt = <1880000>; regulator-max-microvolt = <1880000>; }; + vreg_l15a_1p8: l15 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + vreg_l16a_2p7: l16 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2704000>; }; + vreg_l17a_1p3: l17 { regulator-min-microvolt = <1304000>; regulator-max-microvolt = <1304000>; regulator-allow-set-load; }; + vreg_l18a_2p7: l18 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2704000>; }; + vreg_l19a_3p0: l19 { regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3008000>; }; + vreg_l20a_2p95: l20 { regulator-min-microvolt = <2960000>; regulator-max-microvolt = <2960000>; regulator-allow-set-load; }; + vreg_l21a_2p95: l21 { regulator-min-microvolt = <2960000>; regulator-max-microvolt = <2960000>; regulator-allow-set-load; regulator-system-load = <800000>; }; + vreg_l22a_2p85: l22 { regulator-min-microvolt = <2864000>; regulator-max-microvolt = <2864000>; }; + vreg_l23a_3p3: l23 { regulator-min-microvolt = <3312000>; regulator-max-microvolt = <3312000>; }; + vreg_l24a_3p075: l24 { regulator-min-microvolt = <3088000>; regulator-max-microvolt = <3088000>; }; + vreg_l25a_3p3: l25 { regulator-min-microvolt = <3104000>; regulator-max-microvolt = <3312000>; regulator-allow-set-load; }; + vreg_l26a_1p2: l26 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; + vreg_l28_3p0: l28 { regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3008000>; @@ -278,7 +336,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - }; }; @@ -286,17 +343,6 @@ status = "okay"; }; -&tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; - - touchpad: touchpad { - config { - pins = "gpio123"; - bias-pull-up; /* pull up */ - }; - }; -}; - &sdhc2 { status = "okay"; @@ -304,8 +350,17 @@ vqmmc-supply = <&vreg_l13a_2p95>; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-0 = <&sdc2_on &sdc2_cd>; + pinctrl-1 = <&sdc2_off &sdc2_cd>; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; + + touchpad: touchpad-pin { + pins = "gpio123"; + bias-pull-up; + }; }; &ufshc { @@ -341,26 +396,3 @@ vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; }; - -/* PINCTRL - board-specific pinctrl */ -&blsp1_uart3_on { - rx { - /delete-property/ bias-disable; - /* - * Configure a pull-up on 45 (RX). This is needed to - * avoid garbage data when the TX pin of the Bluetooth - * module is in tri-state (module powered off or not - * driving the signal yet). - */ - bias-pull-up; - }; - - cts { - /delete-property/ bias-disable; - /* - * Configure a pull-down on 47 (CTS) to match the pull - * of the Bluetooth module. - */ - bias-pull-down; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index dc5b9b274df3..429ba57e20f7 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -6,11 +6,13 @@ /dts-v1/; -#include "msm8998-mtp.dtsi" - #include <dt-bindings/input/input.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include "msm8998.dtsi" +#include "pm8005.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" / { model = "F(x)tec Pro1 (QX1000)"; @@ -18,6 +20,11 @@ chassis-type = "handset"; qcom,board-id = <0x02000b 0x10>; + aliases { + serial0 = &blsp2_uart1; + serial1 = &blsp1_uart3; + }; + /* * Until we hook up type-c detection, we * have to stick with this. But it works. @@ -33,7 +40,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hall_sensor1_default>; - hall-sensor1 { + event-hall-sensor1 { label = "Keyboard Hall Sensor"; gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>; debounce-interval = <15>; @@ -49,7 +56,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_kb_pins_extra>; - home { + key-home { label = "Home"; gpios = <&tlmm 21 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOMEPAGE>; @@ -57,7 +64,7 @@ linux,can-disable; }; - super-l { + key-super-l { label = "Super Left"; gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; linux,code = <KEY_FN>; @@ -65,7 +72,7 @@ linux,can-disable; }; - super-r { + key-super-r { label = "Super Right"; gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; linux,code = <KEY_FN>; @@ -73,7 +80,7 @@ linux,can-disable; }; - shift { + key-shift { label = "Shift"; gpios = <&tlmm 114 GPIO_ACTIVE_LOW>; linux,code = <KEY_RIGHTSHIFT>; @@ -81,7 +88,7 @@ linux,can-disable; }; - ctrl { + key-ctrl { label = "Ctrl"; gpios = <&tlmm 128 GPIO_ACTIVE_LOW>; linux,code = <KEY_LEFTCTRL>; @@ -89,7 +96,7 @@ linux,can-disable; }; - alt { + key-alt { label = "Alt"; gpios = <&tlmm 129 GPIO_ACTIVE_LOW>; linux,code = <KEY_LEFTALT>; @@ -101,12 +108,10 @@ gpio-keys { compatible = "gpio-keys"; label = "Side buttons"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&vol_up_pin_a>, <&cam_focus_pin_a>, <&cam_snapshot_pin_a>; - vol-up { + button-vol-up { label = "Volume Up"; gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; @@ -115,7 +120,7 @@ debounce-interval = <15>; }; - camera-snapshot { + button-camera-snapshot { label = "Camera Snapshot"; gpios = <&pm8998_gpio 7 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; @@ -123,7 +128,7 @@ debounce-interval = <15>; }; - camera-focus { + button-camera-focus { label = "Camera Focus"; gpios = <&pm8998_gpio 8 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; @@ -135,7 +140,7 @@ keyboard-leds { compatible = "gpio-leds"; - backlight { + led-0 { color = <LED_COLOR_ID_WHITE>; default-state = "off"; function = LED_FUNCTION_KBD_BACKLIGHT; @@ -144,7 +149,7 @@ retain-state-suspended; }; - caps-lock { + led-1 { color = <LED_COLOR_ID_YELLOW>; default-state = "off"; function = LED_FUNCTION_CAPSLOCK; @@ -187,10 +192,57 @@ pinctrl-0 = <&ts_vio_default>; regulator-always-on; }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&blsp1_uart3 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + max-speed = <3200000>; + }; +}; + +&blsp1_uart3_on { + rx { + /delete-property/ bias-disable; + /* + * Configure a pull-up on 45 (RX). This is needed to + * avoid garbage data when the TX pin of the Bluetooth + * module is in tri-state (module powered off or not + * driving the signal yet). + */ + bias-pull-up; + }; + + cts { + /delete-property/ bias-disable; + /* + * Configure a pull-down on 47 (CTS) to match the pull + * of the Bluetooth module. + */ + bias-pull-down; + }; +}; + +&blsp2_uart1 { + status = "okay"; }; &blsp2_i2c1 { - status = "ok"; + status = "okay"; touchscreen@14 { compatible = "goodix,gt9286"; @@ -205,16 +257,93 @@ }; }; -&mmcc { - status = "ok"; +&etf { + status = "okay"; +}; + +&etm1 { + status = "okay"; +}; + +&etm2 { + status = "okay"; +}; + +&etm3 { + status = "okay"; +}; + +&etm4 { + status = "okay"; +}; + +&etm5 { + status = "okay"; +}; + +&etm6 { + status = "okay"; +}; + +&etm7 { + status = "okay"; +}; + +&etm8 { + status = "okay"; +}; + +&etr { + status = "okay"; }; -&mmss_smmu { - status = "ok"; +&funnel1 { + status = "okay"; +}; + +&funnel2 { + status = "okay"; +}; + +&funnel3 { + status = "okay"; +}; + +&funnel4 { + // FIXME: Figure out why clock late_initcall crashes the board with + // this enabled. + // status = "okay"; +}; + +&funnel5 { + // FIXME: Figure out why clock late_initcall crashes the board with + // this enabled. + // status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pm8005_regulators { + vdd_s1-supply = <&vph_pwr>; + + pm8005_s1: s1 { /* VDD_GFX supply */ + regulator-min-microvolt = <524000>; + regulator-max-microvolt = <1100000>; + regulator-enable-ramp-delay = <500>; + + /* Hack until we rig up the gpu consumer */ + regulator-always-on; + }; }; &pm8998_gpio { - vol_up_pin_a: vol-up-active { + vol_up_pin_a: vol-up-active-state { pins = "gpio6"; function = "normal"; bias-pull-up; @@ -222,7 +351,7 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; }; - cam_focus_pin_a: cam-focus-btn-active { + cam_focus_pin_a: cam-focus-btn-active-state { pins = "gpio7"; function = "normal"; bias-pull-up; @@ -230,7 +359,7 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; }; - cam_snapshot_pin_a: cam-snapshot-btn-active { + cam_snapshot_pin_a: cam-snapshot-btn-active-state { pins = "gpio8"; function = "normal"; bias-pull-up; @@ -249,6 +378,240 @@ }; }; +&qusb2phy { + status = "okay"; + + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; +}; + +&replicator1 { + status = "okay"; +}; + +&rpm_requests { + pm8998-regulators { + compatible = "qcom,rpm-pm8998-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_s8-supply = <&vph_pwr>; + vdd_s9-supply = <&vph_pwr>; + vdd_s10-supply = <&vph_pwr>; + vdd_s11-supply = <&vph_pwr>; + vdd_s12-supply = <&vph_pwr>; + vdd_s13-supply = <&vph_pwr>; + vdd_l1_l27-supply = <&vreg_s7a_1p025>; + vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>; + vdd_l3_l11-supply = <&vreg_s7a_1p025>; + vdd_l4_l5-supply = <&vreg_s7a_1p025>; + vdd_l6-supply = <&vreg_s5a_2p04>; + vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>; + vdd_l9-supply = <&vreg_bob>; + vdd_l10_l23_l25-supply = <&vreg_bob>; + vdd_l13_l19_l21-supply = <&vreg_bob>; + vdd_l16_l28-supply = <&vreg_bob>; + vdd_l18_l22-supply = <&vreg_bob>; + vdd_l20_l24-supply = <&vreg_bob>; + vdd_l26-supply = <&vreg_s3a_1p35>; + vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; + + vreg_s3a_1p35: s3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s4a_1p8: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + }; + + vreg_s5a_2p04: s5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_1p025: s7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vreg_l1a_0p875: l1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + }; + + vreg_l2a_1p2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l3a_1p0: l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_l5a_0p8: l5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + vreg_l6a_1p8: l6 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <1808000>; + }; + + vreg_l7a_1p8: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l8a_1p2: l8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + }; + + vreg_l10a_1p8: l10 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + }; + + vreg_l11a_1p0: l11 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_l12a_1p8: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l13a_2p95: l13 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + }; + + vreg_l14a_1p88: l14 { + regulator-min-microvolt = <1880000>; + regulator-max-microvolt = <1880000>; + }; + + vreg_l15a_1p8: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l16a_2p7: l16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + }; + + vreg_l17a_1p3: l17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l18a_2p7: l18 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + }; + + vreg_l19a_3p0: l19 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + }; + + vreg_l20a_2p95: l20 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-allow-set-load; + }; + + vreg_l21a_2p95: l21 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-system-load = <800000>; + regulator-allow-set-load; + }; + + vreg_l22a_2p85: l22 { + regulator-min-microvolt = <2864000>; + regulator-max-microvolt = <2864000>; + }; + + vreg_l23a_3p3: l23 { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3312000>; + }; + + vreg_l24a_3p075: l24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + }; + + vreg_l25a_3p3: l25 { + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3312000>; + }; + + vreg_l26a_1p2: l26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-allow-set-load; + }; + + vreg_l28_3p0: l28 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + }; + + vreg_lvs1a_1p8: lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_lvs2a_1p8: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + }; + + pmi8998-regulators { + compatible = "qcom,rpm-pmi8998-regulators"; + + vdd_bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + }; + }; +}; + +&remoteproc_adsp { + status = "okay"; +}; + +&remoteproc_mss { + status = "okay"; +}; + +&remoteproc_slpi { + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <0 4>; @@ -297,12 +660,41 @@ }; }; +&sdhc2 { + status = "okay"; + cd-gpios = <&tlmm 95 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vreg_l13a_2p95>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on &sdc2_cd>; + pinctrl-1 = <&sdc2_off &sdc2_cd>; +}; + +&stm { + status = "okay"; +}; + &ufshc { - status = "ok"; + status = "okay"; + vcc-supply = <&vreg_l20a_2p95>; + vccq-supply = <&vreg_l26a_1p2>; + vccq2-supply = <&vreg_s4a_1p8>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <560000>; + vccq2-max-microamp = <750000>; }; &ufsphy { - status = "ok"; + status = "okay"; + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; + vddp-ref-clk-supply = <&vreg_l26a_1p2>; +}; + +&usb3 { + status = "okay"; }; &usb3_dwc3 { @@ -310,8 +702,24 @@ extcon = <&extcon_usb>; }; +&usb3phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; +}; + /* GT9286 analog supply */ &vreg_l28_3p0 { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dts b/arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dts index 1eb406b43fd7..38389c6a3f68 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dts @@ -16,13 +16,14 @@ keyboard@3a { compatible = "hid-over-i2c"; - interrupt-parent = <&tlmm>; - interrupts = <0x79 IRQ_TYPE_LEVEL_LOW>; reg = <0x3a>; - hid-descr-addr = <0x0001>; - pinctrl-names = "default"; pinctrl-0 = <&touchpad>; + + interrupt-parent = <&tlmm>; + interrupts = <121 IRQ_TYPE_LEVEL_LOW>; + + hid-descr-addr = <0x0001>; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts b/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts index f55f6f3e3e5d..cf81c33a9d7e 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts @@ -16,13 +16,14 @@ keyboard@3a { compatible = "hid-over-i2c"; - interrupt-parent = <&tlmm>; - interrupts = <0x79 IRQ_TYPE_LEVEL_LOW>; reg = <0x3a>; - hid-descr-addr = <0x0001>; - pinctrl-names = "default"; pinctrl-0 = <&touchpad>; + + interrupt-parent = <&tlmm>; + interrupts = <121 IRQ_TYPE_LEVEL_LOW>; + + hid-descr-addr = <0x0001>; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts index 66540d2ca13b..a3ca58100aee 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts @@ -3,11 +3,450 @@ /dts-v1/; -#include "msm8998-mtp.dtsi" +#include "msm8998.dtsi" +#include "pm8005.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" / { model = "Qualcomm Technologies, Inc. MSM8998 v1 MTP"; - compatible = "qcom,msm8998-mtp"; + compatible = "qcom,msm8998-mtp", "qcom,msm8998"; qcom,board-id = <8 0>; + + aliases { + serial0 = &blsp2_uart1; + serial1 = &blsp1_uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&blsp1_uart3 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + max-speed = <3200000>; + }; +}; + +&blsp1_uart3_on { + rx { + /delete-property/ bias-disable; + /* + * Configure a pull-up on 45 (RX). This is needed to + * avoid garbage data when the TX pin of the Bluetooth + * module is in tri-state (module powered off or not + * driving the signal yet). + */ + bias-pull-up; + }; + + cts { + /delete-property/ bias-disable; + /* + * Configure a pull-down on 47 (CTS) to match the pull + * of the Bluetooth module. + */ + bias-pull-down; + }; +}; + +&blsp2_uart1 { + status = "okay"; +}; + +&etf { + status = "okay"; +}; + +&etm1 { + status = "okay"; +}; + +&etm2 { + status = "okay"; +}; + +&etm3 { + status = "okay"; +}; + +&etm4 { + status = "okay"; +}; + +&etm5 { + status = "okay"; +}; + +&etm6 { + status = "okay"; +}; + +&etm7 { + status = "okay"; +}; + +&etm8 { + status = "okay"; +}; + +&etr { + status = "okay"; +}; + +&funnel1 { + status = "okay"; +}; + +&funnel2 { + status = "okay"; +}; + +&funnel3 { + status = "okay"; +}; + +&funnel4 { + // FIXME: Figure out why clock late_initcall crashes the board with + // this enabled. + // status = "okay"; +}; + +&funnel5 { + // FIXME: Figure out why clock late_initcall crashes the board with + // this enabled. + // status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pm8005_regulators { + vdd_s1-supply = <&vph_pwr>; + + pm8005_s1: s1 { /* VDD_GFX supply */ + regulator-min-microvolt = <524000>; + regulator-max-microvolt = <1100000>; + regulator-enable-ramp-delay = <500>; + + /* Hack until we rig up the gpu consumer */ + regulator-always-on; + }; +}; + +&qusb2phy { + status = "okay"; + + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; +}; + +&replicator1 { + status = "okay"; +}; + +&rpm_requests { + pm8998-regulators { + compatible = "qcom,rpm-pm8998-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_s8-supply = <&vph_pwr>; + vdd_s9-supply = <&vph_pwr>; + vdd_s10-supply = <&vph_pwr>; + vdd_s11-supply = <&vph_pwr>; + vdd_s12-supply = <&vph_pwr>; + vdd_s13-supply = <&vph_pwr>; + vdd_l1_l27-supply = <&vreg_s7a_1p025>; + vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>; + vdd_l3_l11-supply = <&vreg_s7a_1p025>; + vdd_l4_l5-supply = <&vreg_s7a_1p025>; + vdd_l6-supply = <&vreg_s5a_2p04>; + vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>; + vdd_l9-supply = <&vreg_bob>; + vdd_l10_l23_l25-supply = <&vreg_bob>; + vdd_l13_l19_l21-supply = <&vreg_bob>; + vdd_l16_l28-supply = <&vreg_bob>; + vdd_l18_l22-supply = <&vreg_bob>; + vdd_l20_l24-supply = <&vreg_bob>; + vdd_l26-supply = <&vreg_s3a_1p35>; + vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; + + vreg_s3a_1p35: s3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s4a_1p8: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + }; + + vreg_s5a_2p04: s5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_1p025: s7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vreg_l1a_0p875: l1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + }; + + vreg_l2a_1p2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l3a_1p0: l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_l5a_0p8: l5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + vreg_l6a_1p8: l6 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <1808000>; + }; + + vreg_l7a_1p8: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l8a_1p2: l8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + }; + + vreg_l10a_1p8: l10 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + }; + + vreg_l11a_1p0: l11 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_l12a_1p8: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l13a_2p95: l13 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + }; + + vreg_l14a_1p88: l14 { + regulator-min-microvolt = <1880000>; + regulator-max-microvolt = <1880000>; + }; + + vreg_l15a_1p8: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l16a_2p7: l16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + }; + + vreg_l17a_1p3: l17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l18a_2p7: l18 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + }; + + vreg_l19a_3p0: l19 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + }; + + vreg_l20a_2p95: l20 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-allow-set-load; + }; + + vreg_l21a_2p95: l21 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-system-load = <800000>; + regulator-allow-set-load; + }; + + vreg_l22a_2p85: l22 { + regulator-min-microvolt = <2864000>; + regulator-max-microvolt = <2864000>; + }; + + vreg_l23a_3p3: l23 { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3312000>; + }; + + vreg_l24a_3p075: l24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + }; + + vreg_l25a_3p3: l25 { + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3312000>; + }; + + vreg_l26a_1p2: l26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-allow-set-load; + }; + + vreg_l28_3p0: l28 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + }; + + vreg_lvs1a_1p8: lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_lvs2a_1p8: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + }; + + pmi8998-regulators { + compatible = "qcom,rpm-pmi8998-regulators"; + + vdd_bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + }; + }; +}; + +&remoteproc_adsp { + status = "okay"; +}; + +&remoteproc_mss { + status = "okay"; +}; + +&remoteproc_slpi { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; +}; + +&sdhc2 { + status = "okay"; + cd-gpios = <&tlmm 95 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vreg_l13a_2p95>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on &sdc2_cd>; + pinctrl-1 = <&sdc2_off &sdc2_cd>; +}; + +&stm { + status = "okay"; +}; + +&ufshc { + status = "okay"; + vcc-supply = <&vreg_l20a_2p95>; + vccq-supply = <&vreg_l26a_1p2>; + vccq2-supply = <&vreg_s4a_1p8>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <560000>; + vccq2-max-microamp = <750000>; +}; + +&ufsphy { + status = "okay"; + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; + vddp-ref-clk-supply = <&vreg_l26a_1p2>; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "host"; /* Force to host until we have Type-C hooked up */ +}; + +&usb3phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; +}; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi deleted file mode 100644 index af67c641df4e..000000000000 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi +++ /dev/null @@ -1,421 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ - -#include "msm8998.dtsi" -#include "pm8998.dtsi" -#include "pmi8998.dtsi" -#include "pm8005.dtsi" - -/ { - aliases { - serial0 = &blsp2_uart1; - serial1 = &blsp1_uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&blsp1_uart3 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn3990-bt"; - - vddio-supply = <&vreg_s4a_1p8>; - vddxo-supply = <&vreg_l7a_1p8>; - vddrf-supply = <&vreg_l17a_1p3>; - vddch0-supply = <&vreg_l25a_3p3>; - max-speed = <3200000>; - }; -}; - -&blsp2_uart1 { - status = "okay"; -}; - -&etf { - status = "okay"; -}; - -&etm1 { - status = "okay"; -}; - -&etm2 { - status = "okay"; -}; - -&etm3 { - status = "okay"; -}; - -&etm4 { - status = "okay"; -}; - -&etm5 { - status = "okay"; -}; - -&etm6 { - status = "okay"; -}; - -&etm7 { - status = "okay"; -}; - -&etm8 { - status = "okay"; -}; - -&etr { - status = "okay"; -}; - -&funnel1 { - status = "okay"; -}; - -&funnel2 { - status = "okay"; -}; - -&funnel3 { - status = "okay"; -}; - -&funnel4 { - // FIXME: Figure out why clock late_initcall crashes the board with - // this enabled. - // status = "okay"; -}; - -&funnel5 { - // FIXME: Figure out why clock late_initcall crashes the board with - // this enabled. - // status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pm8005_lsid1 { - pm8005-regulators { - compatible = "qcom,pm8005-regulators"; - - vdd_s1-supply = <&vph_pwr>; - - pm8005_s1: s1 { /* VDD_GFX supply */ - regulator-min-microvolt = <524000>; - regulator-max-microvolt = <1100000>; - regulator-enable-ramp-delay = <500>; - - /* hack until we rig up the gpu consumer */ - regulator-always-on; - }; - }; -}; - -&qusb2phy { - status = "okay"; - - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; -}; - -&replicator1 { - status = "okay"; -}; - -&rpm_requests { - pm8998-regulators { - compatible = "qcom,rpm-pm8998-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; - vdd_s3-supply = <&vph_pwr>; - vdd_s4-supply = <&vph_pwr>; - vdd_s5-supply = <&vph_pwr>; - vdd_s6-supply = <&vph_pwr>; - vdd_s7-supply = <&vph_pwr>; - vdd_s8-supply = <&vph_pwr>; - vdd_s9-supply = <&vph_pwr>; - vdd_s10-supply = <&vph_pwr>; - vdd_s11-supply = <&vph_pwr>; - vdd_s12-supply = <&vph_pwr>; - vdd_s13-supply = <&vph_pwr>; - vdd_l1_l27-supply = <&vreg_s7a_1p025>; - vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>; - vdd_l3_l11-supply = <&vreg_s7a_1p025>; - vdd_l4_l5-supply = <&vreg_s7a_1p025>; - vdd_l6-supply = <&vreg_s5a_2p04>; - vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>; - vdd_l9-supply = <&vreg_bob>; - vdd_l10_l23_l25-supply = <&vreg_bob>; - vdd_l13_l19_l21-supply = <&vreg_bob>; - vdd_l16_l28-supply = <&vreg_bob>; - vdd_l18_l22-supply = <&vreg_bob>; - vdd_l20_l24-supply = <&vreg_bob>; - vdd_l26-supply = <&vreg_s3a_1p35>; - vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; - - vreg_s3a_1p35: s3 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - vreg_s4a_1p8: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allow-set-load; - }; - vreg_s5a_2p04: s5 { - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2040000>; - }; - vreg_s7a_1p025: s7 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1028000>; - }; - vreg_l1a_0p875: l1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - }; - vreg_l2a_1p2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - vreg_l3a_1p0: l3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l5a_0p8: l5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - }; - vreg_l6a_1p8: l6 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <1808000>; - }; - vreg_l7a_1p8: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l8a_1p2: l8 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - vreg_l9a_1p8: l9 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2960000>; - }; - vreg_l10a_1p8: l10 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2960000>; - }; - vreg_l11a_1p0: l11 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l12a_1p8: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l13a_2p95: l13 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2960000>; - }; - vreg_l14a_1p88: l14 { - regulator-min-microvolt = <1880000>; - regulator-max-microvolt = <1880000>; - }; - vreg_l15a_1p8: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l16a_2p7: l16 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - }; - vreg_l17a_1p3: l17 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - }; - vreg_l18a_2p7: l18 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - }; - vreg_l19a_3p0: l19 { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - }; - vreg_l20a_2p95: l20 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-allow-set-load; - }; - vreg_l21a_2p95: l21 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-allow-set-load; - regulator-system-load = <800000>; - }; - vreg_l22a_2p85: l22 { - regulator-min-microvolt = <2864000>; - regulator-max-microvolt = <2864000>; - }; - vreg_l23a_3p3: l23 { - regulator-min-microvolt = <3312000>; - regulator-max-microvolt = <3312000>; - }; - vreg_l24a_3p075: l24 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - }; - vreg_l25a_3p3: l25 { - regulator-min-microvolt = <3104000>; - regulator-max-microvolt = <3312000>; - }; - vreg_l26a_1p2: l26 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-allow-set-load; - }; - vreg_l28_3p0: l28 { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - }; - - vreg_lvs1a_1p8: lvs1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vreg_lvs2a_1p8: lvs2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - }; - - pmi8998-regulators { - compatible = "qcom,rpm-pmi8998-regulators"; - - vdd_bob-supply = <&vph_pwr>; - - vreg_bob: bob { - regulator-min-microvolt = <3312000>; - regulator-max-microvolt = <3600000>; - }; - }; -}; - -&remoteproc_adsp { - status = "okay"; -}; - -&remoteproc_mss { - status = "okay"; -}; - -&remoteproc_slpi { - status = "okay"; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; -}; - -&sdhc2 { - status = "okay"; - cd-gpios = <&tlmm 95 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vreg_l21a_2p95>; - vqmmc-supply = <&vreg_l13a_2p95>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; -}; - -&stm { - status = "okay"; -}; - -&ufshc { - status = "okay"; - vcc-supply = <&vreg_l20a_2p95>; - vccq-supply = <&vreg_l26a_1p2>; - vccq2-supply = <&vreg_s4a_1p8>; - vcc-max-microamp = <750000>; - vccq-max-microamp = <560000>; - vccq2-max-microamp = <750000>; -}; - -&ufsphy { - status = "okay"; - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l2a_1p2>; - vddp-ref-clk-supply = <&vreg_l26a_1p2>; -}; - -&usb3 { - status = "okay"; -}; - -&usb3_dwc3 { - dr_mode = "host"; /* Force to host until we have Type-C hooked up */ -}; - -&usb3phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l2a_1p2>; -}; - -&wifi { - status = "okay"; - - vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; -}; - -/* PINCTRL - board-specific pinctrl */ -&blsp1_uart3_on { - rx { - /delete-property/ bias-disable; - /* - * Configure a pull-up on 45 (RX). This is needed to - * avoid garbage data when the TX pin of the Bluetooth - * module is in tri-state (module powered off or not - * driving the signal yet). - */ - bias-pull-up; - }; - - cts { - /delete-property/ bias-disable; - /* - * Configure a pull-down on 47 (CTS) to match the pull - * of the Bluetooth module. - */ - bias-pull-down; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts b/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts index 9563eb62db88..ef2a88a64d32 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts @@ -32,7 +32,7 @@ }; &pmi8998_gpio { - button_backlight_default: button-backlight-default { + button_backlight_default: button-backlight-state { pinconf { pins = "gpio5"; function = "normal"; diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi index dbaea360bffc..62bda23791bb 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi @@ -11,9 +11,9 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include "msm8998.dtsi" +#include "pm8005.dtsi" #include "pm8998.dtsi" #include "pmi8998.dtsi" -#include "pm8005.dtsi" / { /* Required for bootloader to select correct board */ @@ -32,6 +32,19 @@ height = <1920>; stride = <(1080 * 4)>; format = "a8r8g8b8"; + /* + * That's a lot of clocks, but it's necessary due + * to unused clk cleanup & no panel driver yet.. + */ + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_VSYNC_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_BYTE0_INTF_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>; + power-domains = <&mmcc MDSS_GDSC>; }; }; @@ -77,7 +90,7 @@ pinctrl-names = "default"; pinctrl-0 = <&vol_keys_default>; - vol-down { + button-vol-down { label = "Volume down"; gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; @@ -85,7 +98,7 @@ wakeup-source; }; - vol-up { + button-vol-up { label = "Volume up"; gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -101,7 +114,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hall_sensor_default>; - hall-sensor { + event-hall-sensor { label = "Hall Effect Sensor"; gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -245,32 +258,24 @@ status = "okay"; }; -&pm8005_lsid1 { - pm8005-regulators { - compatible = "qcom,pm8005-regulators"; - - vdd_s1-supply = <&vph_pwr>; - - pm8005_s1: s1 { /* VDD_GFX supply */ - regulator-min-microvolt = <524000>; - regulator-max-microvolt = <1100000>; - regulator-enable-ramp-delay = <500>; - - /* hack until we rig up the gpu consumer */ - regulator-always-on; - }; +&pm8005_regulators { + /* VDD_GFX supply */ + pm8005_s1: s1 { + regulator-min-microvolt = <524000>; + regulator-max-microvolt = <1100000>; + regulator-enable-ramp-delay = <500>; + /* Hack until we rig up the gpu consumer */ + regulator-always-on; }; }; &pm8998_gpio { - vol_keys_default: vol-keys-default { - pinconf { - pins = "gpio5", "gpio6"; - function = "normal"; - bias-pull-up; - input-enable; - qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; - }; + vol_keys_default: vol-keys-state { + pins = "gpio5", "gpio6"; + function = "normal"; + bias-pull-up; + input-enable; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; }; }; @@ -318,91 +323,113 @@ regulator-min-microvolt = <1352000>; regulator-max-microvolt = <1352000>; }; + vreg_s4a_1p8: s4 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-allow-set-load; }; + vreg_s5a_2p04: s5 { regulator-min-microvolt = <1904000>; regulator-max-microvolt = <2040000>; }; + vreg_s7a_1p025: s7 { regulator-min-microvolt = <900000>; regulator-max-microvolt = <1028000>; }; + vreg_l1a_0p875: l1 { regulator-min-microvolt = <880000>; regulator-max-microvolt = <880000>; }; + vreg_l2a_1p2: l2 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; + vreg_l3a_1p0: l3 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; + vreg_l5a_0p8: l5 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <800000>; }; + vreg_l6a_1p8: l6 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <1808000>; }; + vreg_l7a_1p8: l7 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + vreg_l8a_1p2: l8 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; + vreg_l9a_1p8: l9 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <2960000>; }; + vreg_l10a_1p8: l10 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <2960000>; }; + vreg_l11a_1p0: l11 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; + vreg_l12a_1p8: l12 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + vreg_l13a_2p95: l13 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <2960000>; }; + vreg_l14a_1p88: l14 { regulator-min-microvolt = <1880000>; regulator-max-microvolt = <1880000>; }; + vreg_l15a_1p8: l15 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + vreg_l16a_2p7: l16 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2704000>; }; + vreg_l17a_1p3: l17 { regulator-min-microvolt = <1304000>; regulator-max-microvolt = <1304000>; }; + vreg_l18a_2p7: l18 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2704000>; }; + vreg_l19a_3p0: l19 { regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3008000>; }; + vreg_l20a_2p95: l20 { regulator-min-microvolt = <2960000>; regulator-max-microvolt = <2960000>; @@ -411,34 +438,41 @@ vreg_l21a_2p95: l21 { regulator-min-microvolt = <2960000>; regulator-max-microvolt = <2960000>; - regulator-allow-set-load; regulator-system-load = <800000>; + regulator-allow-set-load; }; + vreg_l22a_2p85: l22 { regulator-min-microvolt = <2864000>; regulator-max-microvolt = <2864000>; }; + vreg_l23a_3p3: l23 { regulator-min-microvolt = <3312000>; regulator-max-microvolt = <3312000>; }; + vreg_l24a_3p075: l24 { regulator-min-microvolt = <3088000>; regulator-max-microvolt = <3088000>; }; + vreg_l25a_3p3: l25 { regulator-min-microvolt = <3104000>; regulator-max-microvolt = <3312000>; }; + vreg_l26a_1p2: l26 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-allow-set-load; }; + vreg_l28_3p0: l28 { regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3008000>; }; + vreg_lvs1a_1p8: lvs1 { }; vreg_lvs2a_1p8: lvs2 { }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts index caacb7c28402..fcaefc1b1e2f 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts @@ -29,3 +29,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; + +&vreg_lvs1a_1p8 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts index 978495a8a6b9..20fe0394a3c1 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts @@ -38,7 +38,7 @@ }; &pmi8998_gpio { - disp_dvdd_en: disp-dvdd-en-active { + disp_dvdd_en: disp-dvdd-en-active-state { pins = "gpio10"; function = "normal"; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 47488a1aecae..d08639082247 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -5,15 +5,13 @@ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> */ +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include "msm8998.dtsi" #include "pm8005.dtsi" #include "pm8998.dtsi" #include "pmi8998.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> -#include <dt-bindings/sound/qcom,q6afe.h> -#include <dt-bindings/sound/qcom,q6asm.h> / { /* required for bootloader to select correct board */ @@ -21,8 +19,6 @@ qcom,board-id = <8 0>; clocks { - compatible = "simple-bus"; - div1_mclk: divclk1 { compatible = "gpio-gate-clock"; pinctrl-0 = <&audio_mclk_pin>; @@ -91,13 +87,21 @@ regulator-boot-on; }; + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 38 GPIO_ACTIVE_HIGH>; + vbus-gpio = <&tlmm 128 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_extcon_active &usb_vbus_active>; + }; + gpio-keys { compatible = "gpio-keys"; label = "Side buttons"; pinctrl-names = "default"; pinctrl-0 = <&vol_down_pin_a>, <&cam_focus_pin_a>, <&cam_snapshot_pin_a>; - vol-down { + button-vol-down { label = "Volume Down"; gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; @@ -106,7 +110,7 @@ debounce-interval = <15>; }; - camera-snapshot { + button-camera-snapshot { label = "Camera Snapshot"; gpios = <&pm8998_gpio 7 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; @@ -114,7 +118,7 @@ debounce-interval = <15>; }; - camera-focus { + button-camera-focus { label = "Camera Focus"; gpios = <&pm8998_gpio 8 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; @@ -129,7 +133,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hall_sensor0_default>; - hall-sensor0 { + event-hall-sensor0 { label = "Cover Hall Sensor"; gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -245,6 +249,24 @@ status = "okay"; }; +&blsp2_i2c2 { + status = "okay"; + + proximity@29 { + compatible = "st,vl53l0x"; + reg = <0x29>; + + interrupt-parent = <&tlmm>; + interrupts = <22 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; + vdd-supply = <&cam_vio_vreg>; + + pinctrl-names = "default"; + pinctrl-0 = <&tof_int &tof_reset>; + }; +}; + &ibb { regulator-min-microamp = <800000>; regulator-max-microamp = <800000>; @@ -270,32 +292,19 @@ regulator-soft-start; }; -&mmcc { - status = "ok"; -}; - -&mmss_smmu { - status = "ok"; -}; - -&pm8005_lsid1 { - pm8005-regulators { - compatible = "qcom,pm8005-regulators"; - - vdd_s1-supply = <&vph_pwr>; - - /* VDD_GFX supply */ - pm8005_s1: s1 { - regulator-min-microvolt = <524000>; - regulator-max-microvolt = <1088000>; - regulator-enable-ramp-delay = <500>; - regulator-always-on; - }; +&pm8005_regulators { + /* VDD_GFX supply */ + pm8005_s1: s1 { + regulator-min-microvolt = <524000>; + regulator-max-microvolt = <1088000>; + regulator-enable-ramp-delay = <500>; + /* Hack until we rig up the gpu consumer */ + regulator-always-on; }; }; &pm8998_gpio { - vol_down_pin_a: vol-down-active { + vol_down_pin_a: vol-down-active-state { pins = "gpio5"; function = PMIC_GPIO_FUNC_NORMAL; bias-pull-up; @@ -303,7 +312,7 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; }; - cam_focus_pin_a: cam-focus-btn-active { + cam_focus_pin_a: cam-focus-btn-active-state { pins = "gpio7"; function = PMIC_GPIO_FUNC_NORMAL; bias-pull-up; @@ -311,7 +320,7 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; }; - cam_snapshot_pin_a: cam-snapshot-btn-active { + cam_snapshot_pin_a: cam-snapshot-btn-active-state { pins = "gpio8"; function = PMIC_GPIO_FUNC_NORMAL; bias-pull-up; @@ -319,7 +328,7 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; }; - audio_mclk_pin: audio-mclk-pin-active { + audio_mclk_pin: audio-mclk-pin-active-state { pins = "gpio13"; function = "func2"; power-source = <0>; @@ -327,7 +336,7 @@ }; &pmi8998_gpio { - cam_vio_default: cam-vio-active { + cam_vio_default: cam-vio-active-state { pins = "gpio1"; function = PMIC_GPIO_FUNC_NORMAL; bias-disable; @@ -337,7 +346,7 @@ power-source = <1>; }; - vib_default: vib-en { + vib_default: vib-en-state { pins = "gpio5"; function = PMIC_GPIO_FUNC_NORMAL; bias-disable; @@ -549,8 +558,8 @@ vqmmc-supply = <&vreg_l13a_2p95>; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-0 = <&sdc2_on &sdc2_cd>; + pinctrl-1 = <&sdc2_off &sdc2_cd>; }; &tlmm { @@ -606,6 +615,14 @@ drive-strength = <2>; }; + tof_int: tof-int { + pins = "gpio22"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + input-enable; + }; + cam1_vdig_default: cam1-vdig-default { pins = "gpio25"; function = "gpio"; @@ -613,6 +630,20 @@ drive-strength = <2>; }; + usb_extcon_active: usb-extcon-active { + pins = "gpio38"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + }; + + tof_reset: tof-reset { + pins = "gpio27"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + hall_sensor0_default: acc-cover-open { pins = "gpio124"; function = "gpio"; @@ -628,6 +659,14 @@ bias-pull-up; }; + usb_vbus_active: usb-vbus-active { + pins = "gpio128"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-low; + }; + ts_vddio_en: ts-vddio-en-default { pins = "gpio133"; function = "gpio"; @@ -658,6 +697,7 @@ &usb3_dwc3 { /* Force to peripheral until we have Type-C hooked up */ dr_mode = "peripheral"; + extcon = <&extcon_usb>; }; &usb3phy { diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 758c45bbbe78..02d21bff2198 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -838,7 +838,7 @@ }; qfprom: qfprom@784000 { - compatible = "qcom,qfprom"; + compatible = "qcom,msm8998-qfprom", "qcom,qfprom"; reg = <0x00784000 0x621c>; #address-cells = <1>; #size-cells = <1>; @@ -929,7 +929,7 @@ interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, + interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>; @@ -1057,85 +1057,58 @@ reg = <0x03400000 0xc00000>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; - #gpio-cells = <0x2>; + #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <0x2>; + #interrupt-cells = <2>; - sdc2_clk_on: sdc2_clk_on { - config { + sdc2_on: sdc2-on { + clk { pins = "sdc2_clk"; - bias-disable; drive-strength = <16>; - }; - }; - - sdc2_clk_off: sdc2_clk_off { - config { - pins = "sdc2_clk"; bias-disable; - drive-strength = <2>; }; - }; - sdc2_cmd_on: sdc2_cmd_on { - config { + cmd { pins = "sdc2_cmd"; - bias-pull-up; drive-strength = <10>; - }; - }; - - sdc2_cmd_off: sdc2_cmd_off { - config { - pins = "sdc2_cmd"; bias-pull-up; - drive-strength = <2>; }; - }; - sdc2_data_on: sdc2_data_on { - config { + data { pins = "sdc2_data"; - bias-pull-up; drive-strength = <10>; + bias-pull-up; }; }; - sdc2_data_off: sdc2_data_off { - config { - pins = "sdc2_data"; - bias-pull-up; + sdc2_off: sdc2-off { + clk { + pins = "sdc2_clk"; drive-strength = <2>; + bias-disable; }; - }; - sdc2_cd_on: sdc2_cd_on { - mux { - pins = "gpio95"; - function = "gpio"; + cmd { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; }; - config { - pins = "gpio95"; - bias-pull-up; + data { + pins = "sdc2_data"; drive-strength = <2>; + bias-pull-up; }; }; - sdc2_cd_off: sdc2_cd_off { - mux { - pins = "gpio95"; - function = "gpio"; - }; - - config { - pins = "gpio95"; - bias-pull-up; - drive-strength = <2>; - }; + sdc2_cd: sdc2-cd { + pins = "gpio95"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; }; - blsp1_uart3_on: blsp1_uart3_on { + blsp1_uart3_on: blsp1-uart3-on { tx { pins = "gpio45"; function = "blsp_uart3_a"; @@ -1416,7 +1389,7 @@ status = "disabled"; gpu_opp_table: opp-table { - compatible = "operating-points-v2"; + compatible = "operating-points-v2"; opp-710000097 { opp-hz = /bits/ 64 <710000097>; opp-level = <RPM_SMD_LEVEL_TURBO>; @@ -2080,7 +2053,7 @@ <0xc010600 0x128>, <0xc010800 0x200>; #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "usb3_phy_pipe_clk_src"; @@ -2102,7 +2075,7 @@ nvmem-cells = <&qusb2_hstx_trim>; }; - sdhc2: sdhci@c0a4900 { + sdhc2: mmc@c0a4900 { compatible = "qcom,sdhci-msm-v4"; reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -2415,7 +2388,6 @@ #reset-cells = <1>; #power-domain-cells = <1>; reg = <0xc8c0000 0x40000>; - status = "disabled"; clock-names = "xo", "gpll0", @@ -2450,7 +2422,6 @@ <&mmcc BIMC_SMMU_AXI_CLK>; clock-names = "iface-mm", "iface-smmu", "bus-mm", "bus-smmu"; - status = "disabled"; #global-interrupts = <0>; interrupts = diff --git a/arch/arm64/boot/dts/qcom/pm6350.dtsi b/arch/arm64/boot/dts/qcom/pm6350.dtsi index c5d85064562b..ecf9b9919182 100644 --- a/arch/arm64/boot/dts/qcom/pm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6350.dtsi @@ -36,9 +36,10 @@ }; pm6350_gpios: gpios@c000 { - compatible = "qcom,pm6350-gpio"; + compatible = "qcom,pm6350-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm6350_gpios 0 0 9>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index c482663aad56..d0eefbb51663 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -171,7 +171,7 @@ }; pm660_gpios: gpios@c000 { - compatible = "qcom,pm660-gpio"; + compatible = "qcom,pm660-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; gpio-ranges = <&pm660_gpios 0 0 13>; diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi index cfef42353611..c7945470ffee 100644 --- a/arch/arm64/boot/dts/qcom/pm660l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi @@ -65,9 +65,15 @@ #address-cells = <1>; #size-cells = <0>; + pm660l_lpg: lpg@b100 { + compatible = "qcom,pm660l-lpg"; + + status = "disabled"; + }; + pm660l_wled: leds@d800 { compatible = "qcom,pm660l-wled"; - reg = <0xd800 0xd900>; + reg = <0xd800>, <0xd900>; interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ovp"; label = "backlight"; diff --git a/arch/arm64/boot/dts/qcom/pm8005.dtsi b/arch/arm64/boot/dts/qcom/pm8005.dtsi index 3f97607d8baa..50fb6c753bf8 100644 --- a/arch/arm64/boot/dts/qcom/pm8005.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8005.dtsi @@ -28,5 +28,9 @@ reg = <0x5 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pm8005_regulators: regulators { + compatible = "qcom,pm8005-regulators"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8009.dtsi b/arch/arm64/boot/dts/qcom/pm8009.dtsi index b126d7e7e4fb..0c2c424be0ea 100644 --- a/arch/arm64/boot/dts/qcom/pm8009.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8009.dtsi @@ -19,9 +19,10 @@ }; pm8009_gpios: gpio@c000 { - compatible = "qcom,pm8005-gpio"; + compatible = "qcom,pm8005-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8009_gpios 0 0 4>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index 0df76f7b1cc1..fd8434215924 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -127,9 +127,10 @@ }; pm8150_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio"; + compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8150_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi index 058cc5107c75..5d1ec3a6cc3c 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -112,9 +112,10 @@ }; pm8150b_gpios: gpio@c000 { - compatible = "qcom,pm8150b-gpio"; + compatible = "qcom,pm8150b-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8150b_gpios 0 0 12>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -126,5 +127,15 @@ reg = <0x3 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pm8150b_lpg: lpg { + compatible = "qcom,pm8150b-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi index 52f094a2b713..c62d023b39a2 100644 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi @@ -100,9 +100,10 @@ }; pm8150l_gpios: gpio@c000 { - compatible = "qcom,pm8150l-gpio"; + compatible = "qcom,pm8150l-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8150l_gpios 0 0 12>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -114,5 +115,16 @@ reg = <0x5 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pm8150l_lpg: lpg { + compatible = "qcom,pm8150l-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8350.dtsi b/arch/arm64/boot/dts/qcom/pm8350.dtsi index b10f33afa5e3..2dfeb99300d7 100644 --- a/arch/arm64/boot/dts/qcom/pm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350.dtsi @@ -45,9 +45,10 @@ }; pm8350_gpios: gpio@8800 { - compatible = "qcom,pm8350-gpio"; + compatible = "qcom,pm8350-gpio", "qcom,spmi-gpio"; reg = <0x8800>; gpio-controller; + gpio-ranges = <&pm8350_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm8350b.dtsi b/arch/arm64/boot/dts/qcom/pm8350b.dtsi index f1d1d4c8edf8..f1c7bd9d079c 100644 --- a/arch/arm64/boot/dts/qcom/pm8350b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350b.dtsi @@ -45,9 +45,10 @@ }; pm8350b_gpios: gpio@8800 { - compatible = "qcom,pm8350b-gpio"; + compatible = "qcom,pm8350b-gpio", "qcom,spmi-gpio"; reg = <0x8800>; gpio-controller; + gpio-ranges = <&pm8350b_gpios 0 0 8>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index d58902432812..606c2a6d1f0f 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -108,14 +108,13 @@ }; pm8916_gpios: gpios@c000 { - compatible = "qcom,pm8916-gpio"; + compatible = "qcom,pm8916-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8916_gpios 0 0 4>; #gpio-cells = <2>; - interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, - <0 0xc1 0 IRQ_TYPE_NONE>, - <0 0xc2 0 IRQ_TYPE_NONE>, - <0 0xc3 0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; }; @@ -125,6 +124,14 @@ #address-cells = <1>; #size-cells = <0>; + pm8916_pwm: pwm { + compatible = "qcom,pm8916-pwm"; + + #pwm-cells = <2>; + + status = "disabled"; + }; + pm8916_vib: vibrator@c000 { compatible = "qcom,pm8916-vib"; reg = <0xc000>; diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index 5ab46117d737..ab342397fcd8 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -135,6 +135,16 @@ #address-cells = <1>; #size-cells = <0>; + pm8994_lpg: lpg { + compatible = "qcom,pm8994-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + pm8994_spmi_regulators: regulators { compatible = "qcom,pm8994-regulators"; }; diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi index 6e7c252568e6..84c44912ec93 100644 --- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi @@ -19,6 +19,16 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pmi8994_mpps: mpps@a000 { + compatible = "qcom,pmi8994-mpp"; + reg = <0xa000>; + gpio-controller; + gpio-ranges = <&pmi8994_mpps 0 0 4>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmic@3 { @@ -27,6 +37,16 @@ #address-cells = <1>; #size-cells = <0>; + pmi8994_lpg: lpg { + compatible = "qcom,pmi8994-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + pmi8994_spmi_regulators: regulators { compatible = "qcom,pmi8994-regulators"; #address-cells = <1>; @@ -35,7 +55,7 @@ pmi8994_wled: wled@d800 { compatible = "qcom,pmi8994-wled"; - reg = <0xd800 0xd900>; + reg = <0xd800>, <0xd900>; interrupts = <3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>; interrupt-names = "short"; qcom,cabc; diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index 0fef5f113f05..6d3d212560c1 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -42,9 +42,19 @@ }; }; + pmi8998_lpg: lpg { + compatible = "qcom,pmi8998-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + pmi8998_wled: leds@d800 { compatible = "qcom,pmi8998-wled"; - reg = <0xd800 0xd900>; + reg = <0xd800>, <0xd900>; interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ovp", "short"; @@ -52,6 +62,5 @@ status = "disabled"; }; - }; }; diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi index 7072e5a2e73f..68e9122363ae 100644 --- a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi +++ b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi @@ -116,7 +116,7 @@ }; pmm8155au_1_gpios: gpio@c000 { - compatible = "qcom,pmm8155au-gpio"; + compatible = "qcom,pmm8155au-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi index 72075964fbb9..c307fc662511 100644 --- a/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi +++ b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi @@ -89,7 +89,7 @@ }; pmm8155au_2_gpios: gpio@c000 { - compatible = "qcom,pmm8155au-gpio"; + compatible = "qcom,pmm8155au-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pmr735b.dtsi b/arch/arm64/boot/dts/qcom/pmr735b.dtsi index 604324188603..ec24c4478005 100644 --- a/arch/arm64/boot/dts/qcom/pmr735b.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735b.dtsi @@ -45,9 +45,10 @@ }; pmr735b_gpios: gpio@8800 { - compatible = "qcom,pmr735b-gpio"; + compatible = "qcom,pmr735b-gpio", "qcom,spmi-gpio"; reg = <0x8800>; gpio-controller; + gpio-ranges = <&pmr735b_gpios 0 0 4>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index 98d173a377d5..634b0681d04c 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -38,22 +38,13 @@ #size-cells = <0>; pms405_gpios: gpio@c000 { - compatible = "qcom,pms405-gpio"; + compatible = "qcom,pms405-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pms405_gpios 0 0 12>; #gpio-cells = <2>; - interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, - <0 0xc1 0 IRQ_TYPE_NONE>, - <0 0xc2 0 IRQ_TYPE_NONE>, - <0 0xc3 0 IRQ_TYPE_NONE>, - <0 0xc4 0 IRQ_TYPE_NONE>, - <0 0xc5 0 IRQ_TYPE_NONE>, - <0 0xc6 0 IRQ_TYPE_NONE>, - <0 0xc7 0 IRQ_TYPE_NONE>, - <0 0xc8 0 IRQ_TYPE_NONE>, - <0 0xc9 0 IRQ_TYPE_NONE>, - <0 0xca 0 IRQ_TYPE_NONE>, - <0 0xcb 0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; pon@800 { diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 2f3104a84417..1721ebe5759b 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -304,7 +304,7 @@ }; &pms405_gpios { - usb_vbus_boost_pin: usb-vbus-boost-pin { + usb_vbus_boost_pin: usb-vbus-boost-state { pinconf { pins = "gpio3"; function = PMIC_GPIO_FUNC_NORMAL; @@ -312,7 +312,7 @@ power-source = <1>; }; }; - usb3_vbus_pin: usb3-vbus-pin { + usb3_vbus_pin: usb3-vbus-state { pinconf { pins = "gpio12"; function = PMIC_GPIO_FUNC_NORMAL; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index d912166b7552..19fd8a2b551e 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -366,7 +366,7 @@ }; qfprom: qfprom@a4000 { - compatible = "qcom,qfprom"; + compatible = "qcom,qcs404-qfprom", "qcom,qfprom"; reg = <0x000a4000 0x1000>; #address-cells = <1>; #size-cells = <1>; @@ -669,8 +669,25 @@ }; blsp1_spi1_default: blsp1-spi1-default { - pins = "gpio22", "gpio23", "gpio24", "gpio25"; - function = "blsp_spi1"; + mosi { + pins = "gpio22"; + function = "blsp_spi_mosi_a1"; + }; + + miso { + pins = "gpio23"; + function = "blsp_spi_miso_a1"; + }; + + cs_n { + pins = "gpio24"; + function = "blsp_spi_cs_n_a1"; + }; + + clk { + pins = "gpio25"; + function = "blsp_spi_clk_a1"; + }; }; blsp1_spi2_default: blsp1-spi2-default { @@ -789,7 +806,7 @@ status = "disabled"; }; - sdcc1: sdcc@7804000 { + sdcc1: mmc@7804000 { compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>, <0x7805000 0x1000>; reg-names = "hc", "cqhci"; @@ -798,10 +815,10 @@ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; status = "disabled"; }; @@ -1102,8 +1119,8 @@ status = "disabled"; }; - imem@8600000 { - compatible = "simple-mfd"; + sram@8600000 { + compatible = "qcom,qcs404-imem", "syscon", "simple-mfd"; reg = <0x08600000 0x1000>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 0e63f707b911..b3740375dd4c 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include <dt-bindings/leds/common.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> @@ -59,6 +60,8 @@ user4 { label = "green:user4"; + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_GREEN>; gpios = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; linux,default-trigger = "panic-indicator"; default-state = "off"; @@ -66,6 +69,8 @@ wlan { label = "yellow:wlan"; + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_YELLOW>; gpios = <&pm8150_gpios 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; default-state = "off"; @@ -73,6 +78,8 @@ bt { label = "blue:bt"; + function = LED_FUNCTION_BLUETOOTH; + color = <LED_COLOR_ID_BLUE>; gpios = <&pm8150_gpios 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; default-state = "off"; @@ -796,7 +803,7 @@ "NC", "PM3003A_MODE"; - lt9611_rst_pin: lt9611-rst-pin { + lt9611_rst_pin: lt9611-rst-state { pins = "gpio5"; function = "normal"; @@ -806,6 +813,35 @@ }; }; +&pm8150l_lpg { + status = "okay"; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <3>; + + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + default-state = "on"; + }; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + }; +}; + &pon_pwrkey { status = "okay"; }; @@ -830,7 +866,7 @@ &q6afedai { qi2s@16 { - reg = <16>; + reg = <PRIMARY_MI2S_RX>; qcom,sd-lines = <0 1 2 3>; }; }; @@ -838,7 +874,7 @@ /* TERT I2S Uses 1 I2S SD Lines for audio on LT9611 HDMI Bridge */ &q6afedai { qi2s@20 { - reg = <20>; + reg = <TERTIARY_MI2S_RX>; qcom,sd-lines = <0>; }; }; @@ -915,7 +951,7 @@ }; codec { - sound-dai = <<9611_codec 0>; + sound-dai = <<9611_codec 0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts new file mode 100644 index 000000000000..9398f0349944 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/spmi/spmi.h> + +#include "sa8540p.dtsi" + +/ { + model = "Qualcomm SA8295P ADP"; + compatible = "qcom,sa8295p-adp", "qcom,sa8540p"; + + aliases { + serial0 = &qup2_uart17; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&apps_rsc { + pmm8540-a-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_l3a: ldo3 { + regulator-name = "vreg_l3a"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1208000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l13a: ldo13 { + regulator-name = "vreg_l13a"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + }; + + pmm8540-c-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l3c: ldo3 { + regulator-name = "vreg_l3c"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1208000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l6c: ldo6 { + regulator-name = "vreg_l6c"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l10c: ldo10 { + regulator-name = "vreg_l10c"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l17c: ldo17 { + regulator-name = "vreg_l17c"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + }; + + pmm8540-g-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "g"; + + vreg_l3g: ldo3 { + regulator-name = "vreg_l3g"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l7g: ldo7 { + regulator-name = "vreg_l7g"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l8g: ldo8 { + regulator-name = "vreg_l8g"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + }; +}; + +&qup2 { + status = "okay"; +}; + +&qup2_uart17 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sa8540p/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_nsp0 { + firmware-name = "qcom/sa8540p/cdsp.mbn"; + status = "okay"; +}; + +&remoteproc_nsp1 { + firmware-name = "qcom/sa8540p/cdsp1.mbn"; + status = "okay"; +}; + +&spmi_bus { + pm8450a: pmic@0 { + compatible = "qcom,pm8150", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8450a_gpios: gpio@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8450c: pmic@4 { + compatible = "qcom,pm8150", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8450c_gpios: gpio@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8450e: pmic@8 { + compatible = "qcom,pm8150", "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8450e_gpios: gpio@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8450g: pmic@c { + compatible = "qcom,pm8150", "qcom,spmi-pmic"; + reg = <0xc SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8450g_gpios: gpio@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17c>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l6c>; + vccq-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l8g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + +&ufs_card_hc { + reset-gpios = <&tlmm 229 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l10c>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l3c>; + vccq-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_card_phy { + vdda-phy-supply = <&vreg_l8g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + +&usb_0 { + status = "okay"; +}; + +&usb_0_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode = "peripheral"; +}; + +&usb_0_hsphy { + vdda-pll-supply = <&vreg_l5a>; + vdda18-supply = <&vreg_l7a>; + vdda33-supply = <&vreg_l13a>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l3a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode = "host"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l1c>; + vdda18-supply = <&vreg_l7c>; + vdda33-supply = <&vreg_l2c>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l4c>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + +&usb_2_hsphy0 { + vdda-pll-supply = <&vreg_l5a>; + vdda18-supply = <&vreg_l7g>; + vdda33-supply = <&vreg_l13a>; + + status = "okay"; +}; + +&usb_2_hsphy1 { + vdda-pll-supply = <&vreg_l5a>; + vdda18-supply = <&vreg_l7g>; + vdda33-supply = <&vreg_l13a>; + + status = "okay"; +}; + +&usb_2_hsphy2 { + vdda-pll-supply = <&vreg_l5a>; + vdda18-supply = <&vreg_l7g>; + vdda33-supply = <&vreg_l13a>; + + status = "okay"; +}; + +&usb_2_hsphy3 { + vdda-pll-supply = <&vreg_l5a>; + vdda18-supply = <&vreg_l7g>; + vdda33-supply = <&vreg_l13a>; + + status = "okay"; +}; + +&usb_2_qmpphy0 { + vdda-phy-supply = <&vreg_l3a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&usb_2_qmpphy1 { + vdda-phy-supply = <&vreg_l3a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; + +/* PINCTRL */ diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi new file mode 100644 index 000000000000..8ea2886fbab2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#include "sc8280xp.dtsi" + +/delete-node/ &cpu0_opp_table; +/delete-node/ &cpu4_opp_table; + +/ { + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + }; + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + }; + opp-595200000 { + opp-hz = /bits/ 64 <595200000>; + }; + opp-710400000 { + opp-hz = /bits/ 64 <710400000>; + }; + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + }; + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + }; + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + }; + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + }; + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + }; + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + }; + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + }; + opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + }; + opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + }; + opp-1881600000 { + opp-hz = /bits/ 64 <1881600000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + }; + opp-2131200000 { + opp-hz = /bits/ 64 <2131200000>; + }; + opp-2246400000 { + opp-hz = /bits/ 64 <2246400000>; + }; + }; + + cpu4_opp_table: cpu4-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + }; + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + }; + opp-1171200000 { + opp-hz = /bits/ 64 <1171200000>; + }; + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + }; + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + }; + opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + }; + opp-1747200000 { + opp-hz = /bits/ 64 <1747200000>; + }; + opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + }; + opp-1977600000 { + opp-hz = /bits/ 64 <1977600000>; + }; + opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + }; + opp-2169600000 { + opp-hz = /bits/ 64 <2169600000>; + }; + opp-2284800000 { + opp-hz = /bits/ 64 <2284800000>; + }; + opp-2380800000 { + opp-hz = /bits/ 64 <2380800000>; + }; + opp-2496000000 { + opp-hz = /bits/ 64 <2496000000>; + }; + opp-2592000000 { + opp-hz = /bits/ 64 <2592000000>; + }; + }; +}; + +&rpmhpd { + compatible = "qcom,sa8540p-rpmhpd"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index acdb36f4479f..9dee131b1e24 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -330,6 +330,7 @@ &dsi_phy { status = "okay"; + vdds-supply = <&vreg_l4a_0p8>; }; &mdp { @@ -389,7 +390,7 @@ pinctrl-names = "default","sleep"; pinctrl-0 = <&sdc2_on>; pinctrl-1 = <&sdc2_off>; - vmmc-supply = <&vreg_l9c_2p9>; + vmmc-supply = <&vreg_l9c_2p9>; vqmmc-supply = <&vreg_l6c_2p9>; cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>; @@ -467,7 +468,7 @@ /* PINCTRL - additions to nodes defined in sc7180.dtsi */ &pm6150l_gpio { - disp_pins: disp-pins { + disp_pins: disp-state { pinconf { pins = "gpio3"; function = PMIC_GPIO_FUNC_FUNC1; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 8ac1f1e61006..7ee407f7b6bb 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -81,6 +81,10 @@ }; &cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb-switches"; + }; + cros_ec_proximity: proximity { compatible = "google,cros-ec-mkbp-proximity"; label = "proximity-wifi"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index 9b3e3d13c165..1bd6c7dcd9e9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -5,7 +5,7 @@ * Copyright 2021 Google LLC. */ -#include "sc7180-trogdor.dtsi" +/* This file must be included after sc7180-trogdor.dtsi */ / { /* BOARD-SPECIFIC TOP LEVEL NODES */ @@ -114,6 +114,12 @@ ap_ts_pen_1v8: &i2c4 { status = "okay"; }; +&cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb-switches"; + }; +}; + &panel { compatible = "samsung,atna33xc20"; enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts new file mode 100644 index 000000000000..1a62e8d435ab --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Kingoftown board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" +#include "sc7180-trogdor-kingoftown.dtsi" + +/ { + model = "Google Kingoftown (rev0)"; + compatible = "google,kingoftown-rev0", "qcom,sc7180"; +}; + +/* + * In rev1+, the enable pin of pp3300_fp_tp will be tied to pp1800_l10a + * power rail instead, since kingoftown does not have FP. + */ +&pp3300_fp_tp { + gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&en_fp_rails>; +}; + +&tlmm { + en_fp_rails: en-fp-rails { + pinmux { + pins = "gpio74"; + function = "gpio"; + }; + + pinconf { + pins = "gpio74"; + drive-strength = <2>; + bias-disable; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts new file mode 100644 index 000000000000..e0752ba7df11 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Kingoftown board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-kingoftown.dtsi" + +/ { + model = "Google Kingoftown (rev1+)"; + compatible = "google,kingoftown", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi new file mode 100644 index 000000000000..74f0e07ea5cf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Kingoftown board device tree source + * + * Copyright 2021 Google LLC. + */ + +/* This file must be included after sc7180-trogdor.dtsi */ +#include <arm/cros-ec-keyboard.dtsi> +#include "sc7180-trogdor-lte-sku.dtsi" + +&alc5682 { + compatible = "realtek,rt5682s"; + realtek,dmic1-clk-pin = <2>; + realtek,dmic-clk-rate-hz = <2048000>; +}; + +&ap_tp_i2c { + status = "okay"; +}; + +ap_ts_pen_1v8: &i2c4 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + vcc33-supply = <&pp3300_ts>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + }; +}; + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; + +&panel { + compatible = "edp-panel"; +}; + +&pp3300_dx_edp { + gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; +}; + +&sound { + compatible = "google,sc7180-trogdor"; + model = "sc7180-rt5682s-max98357a-1mic"; +}; + +&wifi { + qcom,ath10k-calibration-variant = "GO_KINGOFTOWN"; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +&en_pp3300_dx_edp { + pinmux { + pins = "gpio67"; + }; + + pinconf { + pins = "gpio67"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "TP_INT_L", /* 0 */ + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "AP_TP_I2C_SDA", + "AP_TP_I2C_SCL", + "TS_RESET_L", + "TS_INT_L", + "", /* 10 */ + "EDP_BRIJ_IRQ", + "AP_EDP_BKLTEN", + "", + "", + "EDP_BRIJ_I2C_SDA", + "EDP_BRIJ_I2C_SCL", + "HUB_RST_L", + "", + "", + "", /* 20 */ + "", + "", + "AMP_EN", + "", + "", + "", + "", + "HP_IRQ", + "", + "", /* 30 */ + "AP_BRD_ID2", + "BRIJ_SUSPEND", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "BT_UART_CTS", + "BT_UART_RTS", + "BT_UART_TXD", /* 40 */ + "BT_UART_RXD", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", /* 50 */ + "AMP_DIN", + "", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", /* 60 */ + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "EN_PP3300_DX_EDP", + "AP_SPI_CS0_L", + "", + "", /* 70 */ + "", + "", + "", + "EN_FP_RAILS", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RST", + "UIM2_PRESENT_L", + "UIM1_DATA", + "UIM1_CLK", /* 80 */ + "UIM1_RST", + "", + "CODEC_PWR_EN", + "HUB_EN", + "", + "", + "", + "", + "", + "AP_SKU_ID1", /* 90 */ + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "", + "", + "", + "", + "", + "", /* 100 */ + "", + "", + "", + "EDP_BRIJ_EN", + "", + "", + "", + "", + "", + "", /* 110 */ + "", + "", + "", + "", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index fe2369c29aad..2cf7d5212c61 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -5,7 +5,8 @@ * Copyright 2020 Google LLC. */ -#include "sc7180-trogdor.dtsi" +/* This file must be included after sc7180-trogdor.dtsi */ +#include <arm/cros-ec-keyboard.dtsi> &ap_sar_sensor { semtech,cs0-ground; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts new file mode 100644 index 000000000000..2767817fb053 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x0 => 0 + * - bits 7..4: Panel ID: 0x0 (AUO) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland-rev0.dtsi" + +/ { + model = "Google Mrbland rev0 AUO panel board"; + compatible = "google,mrbland-rev0-sku0", "qcom,sc7180"; +}; + +&panel { + compatible = "auo,b101uan08.3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts new file mode 100644 index 000000000000..711485574a03 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x10 => 16 + * - bits 7..4: Panel ID: 0x1 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland-rev0.dtsi" + +/ { + model = "Google Mrbland rev0 BOE panel board"; + compatible = "google,mrbland-rev0-sku16", "qcom,sc7180"; +}; + +&panel { + compatible = "boe,tv101wum-n53"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi new file mode 100644 index 000000000000..7bc8402c018e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland.dtsi" + +&avdd_lcd { + gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; +}; + +&panel { + enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>; +}; + +&v1p8_mipi { + gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor-mrbland.dtsi */ +&avdd_lcd_en { + pinmux { + pins = "gpio80"; + }; + + pinconf { + pins = "gpio80"; + }; +}; + +&mipi_1800_en { + pinmux { + pins = "gpio81"; + }; + + pinconf { + pins = "gpio81"; + }; +}; +&vdd_reset_1800 { + pinmux { + pins = "gpio76"; + }; + + pinconf { + pins = "gpio76"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts new file mode 100644 index 000000000000..275313ef7554 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x600 => 1536 + * - bits 11..8: Panel ID: 0x6 (AUO) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland.dtsi" + +/ { + model = "Google Mrbland rev1+ AUO panel board"; + compatible = "google,mrbland-sku1536", "qcom,sc7180"; +}; + +&panel { + compatible = "auo,b101uan08.3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts new file mode 100644 index 000000000000..87c6b6c30b5e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x300 => 768 + * - bits 11..8: Panel ID: 0x3 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland.dtsi" + +/ { + model = "Google Mrbland (rev1 - 2) BOE panel board"; + /* Uses ID 768 on rev1 and 1024 on rev2+ */ + compatible = "google,mrbland-sku1024", "google,mrbland-sku768", + "qcom,sc7180"; +}; + +&panel { + compatible = "boe,tv101wum-n53"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi new file mode 100644 index 000000000000..97cba7f8064f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" + +/* This board only has 1 USB Type-C port. */ +/delete-node/ &usb_c1; + +/ { + avdd_lcd: avdd-lcd { + compatible = "regulator-fixed"; + regulator-name = "avdd_lcd"; + + gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&avdd_lcd_en>; + + vin-supply = <&pp5000_a>; + }; + + avee_lcd: avee-lcd { + compatible = "regulator-fixed"; + regulator-name = "avee_lcd"; + + gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&avee_lcd_en>; + + vin-supply = <&pp5000_a>; + }; + + v1p8_mipi: v1p8-mipi { + compatible = "regulator-fixed"; + regulator-name = "v1p8_mipi"; + + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&mipi_1800_en>; + + vin-supply = <&pp3300_a>; + }; +}; + +&backlight { + pwms = <&cros_ec_pwm 0>; +}; + +&camcc { + status = "okay"; +}; + +&cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb-switches"; + }; +}; + +&dsi0 { + + panel: panel@0 { + /* Compatible will be filled in per-board */ + reg = <0>; + enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_reset_1800>; + avdd-supply = <&avdd_lcd>; + avee-supply = <&avee_lcd>; + pp1800-supply = <&v1p8_mipi>; + pp3300-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + rotation = <270>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; + + ports { + port@1 { + endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&gpio_keys { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@5d { + compatible = "goodix,gt7375p"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + + vdd-supply = <&pp3300_ts>; + }; +}; + +&pp1800_uf_cam { + status = "okay"; +}; + +&pp1800_wf_cam { + status = "okay"; +}; + +&pp2800_uf_cam { + status = "okay"; +}; + +&pp2800_wf_cam { + status = "okay"; +}; + +&wifi { + qcom,ath10k-calibration-variant = "GO_MRBLAND"; +}; + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ +pp3300_disp_on: &pp3300_dx_edp { + gpio = <&tlmm 85 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ + +tp_en: &en_pp3300_dx_edp { + pinmux { + pins = "gpio85"; + }; + + pinconf { + pins = "gpio85"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "HUB_RST_L", + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "UF_CAM_EN", + "WF_CAM_EN", + "TS_RESET_L", + "TS_INT_L", + "", + "", + "AP_EDP_BKLTEN", + "UF_CAM_MCLK", + "WF_CAM_CLK", + "", + "", + "UF_CAM_SDA", + "UF_CAM_SCL", + "WF_CAM_SDA", + "WF_CAM_SCL", + "AVEE_LCD_EN", + "", + "AMP_EN", + "", + "", + "", + "", + "HP_IRQ", + "WF_CAM_RST_L", + "UF_CAM_RST_L", + "AP_BRD_ID2", + "", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "BT_UART_CTS", + "BT_UART_RTS", + "BT_UART_TXD", + "BT_UART_RXD", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", + "AMP_DIN", + "PEN_DET_ODL", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "", + "AP_SPI_CS0_L", + "", + "", + "", + "", + "WLAN_SW_CTRL", + "", + "REPORT_E", + "", + "ID0", + "", + "ID1", + "", + "", + "", + "CODEC_PWR_EN", + "HUB_EN", + "TP_EN", + "MIPI_1.8V_EN", + "VDD_RESET_1.8V", + "AVDD_LCD_EN", + "", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "SDM_GRFC_3", + "", + "", + "BOOT_CONFIG_4", + "BOOT_CONFIG_2", + "", + "", + "", + "", + "", + "", + "", + "BOOT_CONFIG_3", + "WCI2_LTE_COEX_TXD", + "WCI2_LTE_COEX_RXD", + "", + "", + "", + "", + "FORCED_USB_BOOT_POL", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; + + avdd_lcd_en: avdd-lcd-en { + pinmux { + pins = "gpio88"; + function = "gpio"; + }; + + pinconf { + pins = "gpio88"; + drive-strength = <2>; + bias-disable; + }; + }; + + avee_lcd_en: avee-lcd-en { + pinmux { + pins = "gpio21"; + function = "gpio"; + }; + + pinconf { + pins = "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + + mipi_1800_en: mipi-1800-en { + pinmux { + pins = "gpio86"; + function = "gpio"; + }; + + pinconf { + pins = "gpio86"; + drive-strength = <2>; + bias-disable; + }; + }; + + vdd_reset_1800: vdd-reset-1800 { + pinmux { + pins = "gpio87"; + function = "gpio"; + }; + + pinconf { + pins = "gpio87"; + drive-strength = <2>; + bias-disable; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-parade.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-parade.dts new file mode 100644 index 000000000000..764c451c1a85 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-parade.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-pazquel.dtsi" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Pazquel (Parade,LTE)"; + compatible = "google,pazquel-sku4", "qcom,sc7180"; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-ti.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-ti.dts new file mode 100644 index 000000000000..9145b74e9009 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-ti.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" +#include "sc7180-trogdor-pazquel.dtsi" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Pazquel (TI,LTE)"; + compatible = "google,pazquel-sku0", "google,pazquel-sku2", "qcom,sc7180"; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-parade.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-parade.dts new file mode 100644 index 000000000000..9a0e6632a786 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-parade.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-pazquel.dtsi" + +/ { + model = "Google Pazquel (Parade)"; + compatible = "google,pazquel-sku5", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-ti.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-ti.dts new file mode 100644 index 000000000000..47c5970d8c22 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-ti.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" +#include "sc7180-trogdor-pazquel.dtsi" + +/ { + model = "Google Pazquel (TI)"; + compatible = "google,pazquel-sku1", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi new file mode 100644 index 000000000000..56d787785fd5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2021 Google LLC. + */ + +/* This file must be included after sc7180-trogdor.dtsi */ +#include <arm/cros-ec-keyboard.dtsi> + +&ap_sar_sensor { + compatible = "semtech,sx9324"; + semtech,ph0-pin = <1 3 3>; + semtech,ph1-pin = <3 1 3>; + semtech,ph2-pin = <1 3 3>; + semtech,ph3-pin = <0 0 0>; + semtech,ph01-resolution = <1024>; + semtech,ph23-resolution = <1024>; + semtech,startup-sensor = <1>; + semtech,ph01-proxraw-strength = <3>; + semtech,ph23-proxraw-strength = <1>; + semtech,avg-pos-strength = <128>; + semtech,input-analog-gain = <0>; + semtech,cs-idle-sleep = "gnd"; + + /delete-property/ svdd-supply; + vdd-supply = <&pp1800_prox>; +}; + +/delete-node/&trackpad; +&ap_tp_i2c { + status = "okay"; + trackpad: trackpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + + vcc-supply = <&pp3300_fp_tp>; + post-power-on-delay-ms = <100>; + hid-descr-addr = <0x0001>; + + wakeup-source; + }; +}; + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + CROS_STD_MAIN_KEYMAP + >; +}; + +&panel { + compatible = "edp-panel"; +}; + +&pp3300_dx_edp { + gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; +}; + +&en_pp3300_dx_edp { + pinmux { + pins = "gpio67"; + }; + + pinconf { + pins = "gpio67"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "TP_INT_ODL", + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "AP_TP_I2C_SDA", + "AP_TP_I2C_SCL", + "TS_RESET_L", + "TS_INT_L", + "", + "EDP_BRIJ_IRQ", + "AP_EDP_BKLTEN", + "", + "", + "EDP_BRIJ_I2C_SDA", + "EDP_BRIJ_I2C_SCL", + "HUB_RST_L", + "", + "", + "", + "", + "", + "AMP_EN", + "P_SENSOR_INT_L", + "AP_SAR_SENSOR_SDA", + "AP_SAR_SENSOR_SCL", + "", + "HP_IRQ", + "", + "", + "AP_BRD_ID2", + "BRIJ_SUSPEND", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "", + "", + "", + "", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", + "AMP_DIN", + "", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "EN_PP3300_DX_EDP", + "AP_SPI_CS0_L", + "", + "", + "", + "", + "", + "", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RST", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RST", + "", + "CODEC_PWR_EN", + "HUB_EN", + "", + "", + "", + "", + "", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "EDP_BRIJ_EN", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index 3df4920295ad..a7582fb547ee 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -6,6 +6,8 @@ */ #include "sc7180-trogdor.dtsi" +/* Must come after sc7180-trogdor.dtsi to modify cros_ec */ +#include <arm/cros-ec-keyboard.dtsi> #include "sc7180-trogdor-ti-sn65dsi86.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0-lte.dts new file mode 100644 index 000000000000..35e8945fc56d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0-lte.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Quackingstick board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x600 => 1536 + * - bits 11..8: Panel ID: 0x6 (AUO) + */ + +#include "sc7180-trogdor-quackingstick-r0.dts" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Quackingstick (rev0+) with LTE"; + compatible = "google,quackingstick-sku1536", "qcom,sc7180"; +}; + +&ap_sar_sensor { + compatible = "semtech,sx9324"; + semtech,ph0-pin = <3 1 3>; + semtech,ph1-pin = <2 1 2>; + semtech,ph2-pin = <3 3 1>; + semtech,ph3-pin = <1 3 3>; + semtech,ph01-resolution = <1024>; + semtech,ph23-resolution = <1024>; + semtech,startup-sensor = <1>; + semtech,ph01-proxraw-strength = <3>; + semtech,ph23-proxraw-strength = <3>; + semtech,avg-pos-strength = <256>; + + /delete-property/ svdd-supply; + vdd-supply = <&pp1800_prox>; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts new file mode 100644 index 000000000000..5c81e44ed4a5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Quackingstick board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x601 => 1537 + * - bits 11..8: Panel ID: 0x6 (AUO) + */ + +#include "sc7180-trogdor-quackingstick.dtsi" + +/ { + model = "Google Quackingstick (rev0+)"; + compatible = "google,quackingstick-sku1537", "qcom,sc7180"; +}; + +&dsi_phy { + qcom,phy-rescode-offset-top = /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>; + qcom,phy-rescode-offset-bot = /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>; + qcom,phy-drive-ldo-level = <375>; +}; + +&panel { + compatible = "auo,b101uan08.3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi new file mode 100644 index 000000000000..695b04fe7221 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Quackingstick board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" + +/* This board only has 1 USB Type-C port. */ +/delete-node/ &usb_c1; + +/ { + ppvar_lcd: ppvar-lcd { + compatible = "regulator-fixed"; + regulator-name = "ppvar_lcd"; + + gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&ppvar_lcd_en>; + + vin-supply = <&pp5000_a>; + }; + + v1p8_disp: v1p8-disp { + compatible = "regulator-fixed"; + regulator-name = "v1p8_disp"; + + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pp1800_disp_on>; + + vin-supply = <&pp3300_a>; + }; +}; + +&backlight { + pwms = <&cros_ec_pwm 0>; +}; + +&camcc { + status = "okay"; +}; + +&cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb-switches"; + }; +}; + +&dsi0 { + panel: panel@0 { + /* Compatible will be filled in per-board */ + reg = <0>; + enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst>; + avdd-supply = <&ppvar_lcd>; + pp1800-supply = <&v1p8_disp>; + pp3300-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + rotation = <270>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; + + ports { + port@1 { + endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&gpio_keys { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <20>; + hid-descr-addr = <0x0001>; + + vdd-supply = <&pp3300_ts>; + }; +}; + +&sdhc_2 { + status = "okay"; +}; + +&pp1800_uf_cam { + status = "okay"; +}; + +&pp1800_wf_cam { + status = "okay"; +}; + +&pp2800_uf_cam { + status = "okay"; +}; + +&pp2800_wf_cam { + status = "okay"; +}; + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ +pp3300_disp_on: &pp3300_dx_edp { + gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ + +tp_en: &en_pp3300_dx_edp { + pinmux { + pins = "gpio67"; + }; + + pinconf { + pins = "gpio67"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "HUB_RST_L", + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "UF_CAM_EN", + "WF_CAM_EN", + "TS_RESET_L", + "TS_INT_L", + "", + "", + "AP_EDP_BKLTEN", + "UF_CAM_MCLK", + "WF_CAM_CLK", + "EDP_BRIJ_I2C_SDA", + "EDP_BRIJ_I2C_SCL", + "UF_CAM_SDA", + "UF_CAM_SCL", + "WF_CAM_SDA", + "WF_CAM_SCL", + "", + "", + "AMP_EN", + "P_SENSOR_INT_L", + "AP_SAR_SENSOR_SDA", + "AP_SAR_SENSOR_SCL", + "", + "HP_IRQ", + "WF_CAM_RST_L", + "UF_CAM_RST_L", + "AP_BRD_ID2", + "", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "", + "", + "", + "", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "", + "", + "AMP_DIN", + "PEN_DET_ODL", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "EN_PP3300_DX_EDP", + "AP_SPI_CS0_L", + "SD_CD_ODL", + "", + "", + "", + "", + "", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RST", + "UIM2_PRESENT_L", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RST", + "", + "CODEC_PWR_EN", + "HUB_EN", + "", + "PP1800_DISP_ON", + "LCD_RST", + "PPVAR_LCD_EN", + "", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AP_TS_I2C_SDA", + "AP_TS_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; + + lcd_rst: lcd-rst { + pinmux { + pins = "gpio87"; + function = "gpio"; + }; + + pinconf { + pins = "gpio87"; + drive-strength = <2>; + bias-disable; + }; + }; + + ppvar_lcd_en: ppvar-lcd-en { + pinmux { + pins = "gpio88"; + function = "gpio"; + }; + + pinconf { + pins = "gpio88"; + drive-strength = <2>; + bias-disable; + }; + }; + + pp1800_disp_on: pp1800-disp-on { + pinmux { + pins = "gpio86"; + function = "gpio"; + }; + + pinconf { + pins = "gpio86"; + drive-strength = <2>; + bias-disable; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts index 352827e5740a..59a23d0e9651 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts @@ -8,6 +8,8 @@ /dts-v1/; #include "sc7180-trogdor.dtsi" +/* Must come after sc7180-trogdor.dtsi to modify cros_ec */ +#include <arm/cros-ec-keyboard.dtsi> #include "sc7180-trogdor-ti-sn65dsi86.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts new file mode 100644 index 000000000000..d6ed7d0afe4a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x10 => 16 + * - bits 7..4: Panel ID: 0x1 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler-rev0.dtsi" + +/ { + model = "Google Wormdingler rev0 BOE panel board"; + compatible = "google,wormdingler-rev0-sku16", "qcom,sc7180"; +}; + +&panel { + compatible = "boe,tv110c9m-ll3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts new file mode 100644 index 000000000000..c03525ea64ca --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x0 => 0 + * - bits 7..4: Panel ID: 0x0 (INX) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler-rev0.dtsi" + +/ { + model = "Google Wormdingler rev0 INX panel board"; + compatible = "google,wormdingler-rev0-sku0", "qcom,sc7180"; +}; + +&panel { + compatible = "innolux,hj110iz-01a"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi new file mode 100644 index 000000000000..db29e0cba29d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler.dtsi" + +&avdd_lcd { + gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; +}; + +&panel { + enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>; +}; + +&v1p8_mipi { + gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor-wormdingler.dtsi */ +&avdd_lcd_en { + pinmux { + pins = "gpio80"; + }; + + pinconf { + pins = "gpio80"; + }; +}; + +&mipi_1800_en { + pinmux { + pins = "gpio81"; + }; + + pinconf { + pins = "gpio81"; + }; +}; +&vdd_reset_1800 { + pinmux { + pins = "gpio76"; + }; + + pinconf { + pins = "gpio76"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dts new file mode 100644 index 000000000000..aa605885c371 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x401 => 1025 + * - bits 11..8: Panel ID: 0x4 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler-rev1-boe.dts" + +/ { + model = "Google Wormdingler rev1+ (BOE, rt5682s)"; + compatible = "google,wormdingler-sku1025", "qcom,sc7180"; +}; + +&alc5682 { + compatible = "realtek,rt5682s"; + realtek,dmic1-clk-pin = <2>; + realtek,dmic-clk-rate-hz = <2048000>; +}; + +&sound { + compatible = "google,sc7180-trogdor"; + model = "sc7180-rt5682s-max98357a-1mic"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts new file mode 100644 index 000000000000..c5b0658bd632 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x400 => 1024 + * - bits 11..8: Panel ID: 0x4 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler.dtsi" + +/ { + model = "Google Wormdingler rev1+ BOE panel board"; + compatible = "google,wormdingler-sku1024", "qcom,sc7180"; +}; + +&dsi_phy { + qcom,phy-rescode-offset-top = /bits/ 8 <31 31 31 31 (-32)>; + qcom,phy-rescode-offset-bot = /bits/ 8 <31 31 31 31 (-32)>; + qcom,phy-drive-ldo-level = <450>; +}; + +&panel { + compatible = "boe,tv110c9m-ll3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dts new file mode 100644 index 000000000000..7116c44c8d85 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x0001 => 1 + * - bits 11..8: Panel ID: 0x0 (INX) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler-rev1-inx.dts" + +/ { + model = "Google Wormdingler rev1+ (INX, rt5682s)"; + compatible = "google,wormdingler-sku1", "qcom,sc7180"; +}; + +&alc5682 { + compatible = "realtek,rt5682s"; + realtek,dmic1-clk-pin = <2>; + realtek,dmic-clk-rate-hz = <2048000>; +}; + +&sound { + compatible = "google,sc7180-trogdor"; + model = "sc7180-rt5682s-max98357a-1mic"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx.dts new file mode 100644 index 000000000000..dd34a2297ea0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x0000 => 0 + * - bits 11..8: Panel ID: 0x0 (INX) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler.dtsi" + +/ { + model = "Google Wormdingler rev1+ INX panel board"; + compatible = "google,wormdingler-sku0", "qcom,sc7180"; +}; + +&panel { + compatible = "innolux,hj110iz-01a"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi new file mode 100644 index 000000000000..6312108e8b3e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -0,0 +1,412 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" + +/ { + avdd_lcd: avdd-lcd { + compatible = "regulator-fixed"; + regulator-name = "avdd_lcd"; + + gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&avdd_lcd_en>; + + vin-supply = <&pp5000_a>; + }; + + avee_lcd: avee-lcd { + compatible = "regulator-fixed"; + regulator-name = "avee_lcd"; + + gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&avee_lcd_en>; + + vin-supply = <&pp5000_a>; + }; + + pp1800_ts: + v1p8_mipi: v1p8-mipi { + compatible = "regulator-fixed"; + regulator-name = "v1p8_mipi"; + + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&mipi_1800_en>; + + vin-supply = <&pp3300_a>; + }; + + thermal-zones { + skin_temp_thermal: skin-temp-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&pm6150_adc_tm 1>; + sustainable-power = <574>; + + trips { + skin_temp_alert0: trip-point0 { + temperature = <58000>; + hysteresis = <1000>; + type = "passive"; + }; + + skin_temp_alert1: trip-point1 { + temperature = <62500>; + hysteresis = <1000>; + type = "passive"; + }; + + skin-temp-crit { + temperature = <68000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&skin_temp_alert0>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&skin_temp_alert1>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; + +&backlight { + pwms = <&cros_ec_pwm 0>; +}; + +&camcc { + status = "okay"; +}; + +&cros_ec { + base_detection: cbas { + compatible = "google,cros-cbas"; + }; + + keyboard-controller { + compatible = "google,cros-ec-keyb-switches"; + }; +}; + +&dsi0 { + + panel: panel@0 { + reg = <0>; + enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_reset_1800>; + avdd-supply = <&avdd_lcd>; + avee-supply = <&avee_lcd>; + pp1800-supply = <&v1p8_mipi>; + pp3300-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + rotation = <270>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; + + ports { + port@1 { + endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@1 { + compatible = "hid-over-i2c"; + reg = <0x01>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + + post-power-on-delay-ms = <70>; + hid-descr-addr = <0x0001>; + + vdd-supply = <&pp3300_ts>; + vddl-supply = <&pp1800_ts>; + }; +}; + +&pm6150_adc { + skin-temp-thermistor@4d { + reg = <ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm6150_adc_tm { + status = "okay"; + + skin-temp-thermistor@1 { + reg = <1>; + io-channels = <&pm6150_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pp1800_uf_cam { + status = "okay"; +}; + +&pp1800_wf_cam { + status = "okay"; +}; + +&pp2800_uf_cam { + status = "okay"; +}; + +&pp2800_wf_cam { + status = "okay"; +}; + +&wifi { + qcom,ath10k-calibration-variant = "GO_WORMDINGLER"; +}; + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ +pp3300_disp_on: &pp3300_dx_edp { + gpio = <&tlmm 85 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ + +tp_en: &en_pp3300_dx_edp { + pinmux { + pins = "gpio85"; + }; + + pinconf { + pins = "gpio85"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "HUB_RST_L", + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "UF_CAM_EN", + "WF_CAM_EN", + "TS_RESET_L", + "TS_INT_L", + "", + "", + "AP_EDP_BKLTEN", + "UF_CAM_MCLK", + "WF_CAM_CLK", + "", + "", + "UF_CAM_SDA", + "UF_CAM_SCL", + "WF_CAM_SDA", + "WF_CAM_SCL", + "AVEE_LCD_EN", + "", + "AMP_EN", + "", + "", + "", + "", + "HP_IRQ", + "WF_CAM_RST_L", + "UF_CAM_RST_L", + "AP_BRD_ID2", + "", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "BT_UART_CTS", + "BT_UART_RTS", + "BT_UART_TXD", + "BT_UART_RXD", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", + "AMP_DIN", + "", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "", + "AP_SPI_CS0_L", + "", + "", + "", + "", + "WLAN_SW_CTRL", + "", + "REPORT_E", + "", + "ID0", + "", + "ID1", + "", + "", + "", + "CODEC_PWR_EN", + "HUB_EN", + "TP_EN", + "MIPI_1.8V_EN", + "VDD_RESET_1.8V", + "AVDD_LCD_EN", + "", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "SDM_GRFC_3", + "", + "", + "BOOT_CONFIG_4", + "BOOT_CONFIG_2", + "", + "", + "", + "", + "", + "", + "", + "BOOT_CONFIG_3", + "WCI2_LTE_COEX_TXD", + "WCI2_LTE_COEX_RXD", + "", + "", + "", + "", + "FORCED_USB_BOOT_POL", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; + + avdd_lcd_en: avdd-lcd-en { + pinmux { + pins = "gpio88"; + function = "gpio"; + }; + + pinconf { + pins = "gpio88"; + drive-strength = <2>; + bias-disable; + }; + }; + + avee_lcd_en: avee-lcd-en { + pinmux { + pins = "gpio21"; + function = "gpio"; + }; + + pinconf { + pins = "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + + mipi_1800_en: mipi-1800-en { + pinmux { + pins = "gpio86"; + function = "gpio"; + }; + + pinconf { + pins = "gpio86"; + drive-strength = <2>; + bias-disable; + }; + }; + + vdd_reset_1800: vdd-reset-1800 { + pinmux { + pins = "gpio87"; + function = "gpio"; + }; + + pinconf { + pins = "gpio87"; + drive-strength = <2>; + bias-disable; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index e55dbaa6dc12..b5f534db135a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/gpio-keys.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <dt-bindings/sound/sc7180-lpass.h> @@ -43,6 +44,7 @@ */ /delete-node/ &hyp_mem; +/delete-node/ &ipa_fw_mem; /delete-node/ &xbl_mem; /delete-node/ &aop_mem; /delete-node/ &sec_apps_mem; @@ -330,7 +332,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pen_pdct_l>; - pen_insert: pen-insert { + pen_insert: switch-pen-insert { label = "Pen Insert"; /* Insert = low, eject = high */ @@ -355,6 +357,7 @@ keyboard_backlight: keyboard-backlight { status = "disabled"; label = "cros_ec::kbd_backlight"; + function = LED_FUNCTION_KBD_BACKLIGHT; pwms = <&cros_ec_pwm 0>; max-brightness = <1023>; }; @@ -812,8 +815,6 @@ hp_i2c: &i2c9 { pinctrl-names = "default"; pinctrl-0 = <&dp_hot_plug_det>; data-lanes = <0 1>; - vdda-1p2-supply = <&vdda_usb_ss_dp_1p2>; - vdda-0p9-supply = <&vdda_usb_ss_dp_core>; }; &pm6150_adc { @@ -903,7 +904,6 @@ ap_spi_fp: &spi10 { }; }; -#include <arm/cros-ec-keyboard.dtsi> #include <arm/cros-ec-sbs.dtsi> &uart3 { diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 5dcaac23a138..881e30953c0f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -398,7 +398,7 @@ }; }; - cpu0_opp_table: cpu0_opp_table { + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; @@ -453,7 +453,7 @@ }; }; - cpu6_opp_table: cpu6_opp_table { + cpu6_opp_table: opp-table-cpu6 { compatible = "operating-points-v2"; opp-shared; @@ -693,7 +693,7 @@ }; }; - sdhc_1: sdhci@7c4000 { + sdhc_1: mmc@7c4000 { compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x7c4000 0 0x1000>, <0 0x07c5000 0 0x1000>; @@ -704,10 +704,10 @@ <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; @@ -725,7 +725,7 @@ status = "disabled"; - sdhc1_opp_table: sdhc1-opp-table { + sdhc1_opp_table: opp-table { compatible = "operating-points-v2"; opp-100000000 { @@ -744,7 +744,7 @@ }; }; - qup_opp_table: qup-opp-table { + qup_opp_table: opp-table-qup { compatible = "operating-points-v2"; opp-75000000 { @@ -2048,7 +2048,7 @@ }; gmu: gmu@506a000 { - compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; + compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, <0 0x0b490000 0 0x10000>; reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; @@ -2578,7 +2578,7 @@ }; }; - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -2587,10 +2587,10 @@ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; @@ -2602,7 +2602,7 @@ status = "disabled"; - sdhc2_opp_table: sdhc2-opp-table { + sdhc2_opp_table: opp-table { compatible = "operating-points-v2"; opp-100000000 { @@ -2621,7 +2621,7 @@ }; }; - qspi_opp_table: qspi-opp-table { + qspi_opp_table: opp-table-qspi { compatible = "operating-points-v2"; opp-75000000 { @@ -2825,7 +2825,7 @@ compatible = "venus-encoder"; }; - venus_opp_table: venus-opp-table { + venus_opp_table: opp-table { compatible = "operating-points-v2"; opp-150000000 { @@ -2896,9 +2896,6 @@ <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "ahb", "core"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; @@ -2928,12 +2925,10 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "bus", "iface", "rot", "lut", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_ROT_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>; - assigned-clock-rates = <300000000>, - <19200000>, + assigned-clock-rates = <19200000>, <19200000>, <19200000>; operating-points-v2 = <&mdp_opp_table>; @@ -2963,7 +2958,7 @@ }; }; - mdp_opp_table: mdp-opp-table { + mdp_opp_table: opp-table { compatible = "operating-points-v2"; opp-200000000 { @@ -3042,7 +3037,7 @@ }; }; - dsi_opp_table: dsi-opp-table { + dsi_opp_table: opp-table { compatible = "operating-points-v2"; opp-187500000 { @@ -3215,7 +3210,7 @@ }; aoss_qmp: power-controller@c300000 { - compatible = "qcom,sc7180-aoss-qmp"; + compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; mboxes = <&apss_shared 0>; @@ -3247,8 +3242,8 @@ cell-index = <0>; }; - imem@146aa000 { - compatible = "simple-mfd"; + sram@146aa000 { + compatible = "qcom,sc7180-imem", "syscon", "simple-mfd"; reg = <0 0x146aa000 0 0x2000>; #address-cells = <1>; @@ -3384,9 +3379,9 @@ }; timer@17c20000{ - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; compatible = "arm,armv7-timer-mem"; reg = <0 0x17c20000 0 0x1000>; @@ -3394,49 +3389,49 @@ frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c21000 0 0x1000>, - <0 0x17c22000 0 0x1000>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; }; frame@17c23000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c23000 0 0x1000>; + reg = <0x17c23000 0x1000>; status = "disabled"; }; frame@17c25000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c25000 0 0x1000>; + reg = <0x17c25000 0x1000>; status = "disabled"; }; frame@17c27000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c27000 0 0x1000>; + reg = <0x17c27000 0x1000>; status = "disabled"; }; frame@17c29000 { frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c29000 0 0x1000>; + reg = <0x17c29000 0x1000>; status = "disabled"; }; frame@17c2b000 { frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c2b000 0 0x1000>; + reg = <0x17c2b000 0x1000>; status = "disabled"; }; frame@17c2d000 { frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c2d000 0 0x1000>; + reg = <0x17c2d000 0x1000>; status = "disabled"; }; }; @@ -3584,7 +3579,7 @@ compatible = "qcom,sc7180-lpass-cpu"; reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; - reg-names = "lpass-hdmiif", "lpass-lpaif"; + reg-names = "lpass-hdmiif", "lpass-lpaif"; iommus = <&apps_smmu 0x1020 0>, <&apps_smmu 0x1021 0>, diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi index 9f4a9c263c35..cfe2741456a1 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi @@ -88,10 +88,26 @@ status = "okay"; compatible = "qcom,sc7280-mss-pil"; iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; + interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; memory-region = <&mba_mem>, <&mpss_mem>; + firmware-name = "qcom/sc7280-herobrine/modem/mba.mbn", + "qcom/sc7280-herobrine/modem/qdsp6sw.mbn"; +}; + +&remoteproc_wpss { + status = "okay"; + firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt"; }; /* Increase the size from 2.5MB to 8MB */ &rmtfs_mem { reg = <0x0 0x9c900000 0x0 0x800000>; }; + +&wifi { + status = "okay"; + + wifi-firmware { + iommus = <&apps_smmu 0x1c02 0x1>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi new file mode 100644 index 000000000000..32a1e78982b2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * sc7280 device tree source for boards using Max98360 and wcd9385 codec + * + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +&mi2s1_data0 { + drive-strength = <6>; + bias-disable; +}; + +&mi2s1_sclk { + drive-strength = <6>; + bias-disable; +}; + +&mi2s1_ws { + drive-strength = <6>; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts index a4ac33c4fd59..e9ca6c5d24a1 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "sc7280-herobrine.dtsi" +#include "sc7280-herobrine-audio-wcd9385.dtsi" / { model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)"; @@ -134,6 +135,17 @@ ap_ts_pen_1v8: &i2c13 { status = "okay"; }; +/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ + +/* + * This pin goes to the display panel but then doesn't actually do anything + * on the panel itself (it doesn't connect to the touchscreen controller). + * We'll set a pullup here just to park the line. + */ +&ts_rst_conn { + bias-pull-up; +}; + /* PINCTRL - BOARD-SPECIFIC */ /* @@ -143,6 +155,67 @@ ap_ts_pen_1v8: &i2c13 { * - If a pin is totally internal to Qcard then it gets Qcard name. * - If a pin is not hooked up on Qcard, it gets no name. */ +&lpass_dmic01_clk { + drive-strength = <8>; + bias-disable; +}; + +&lpass_dmic01_clk_sleep { + drive-strength = <2>; +}; + +&lpass_dmic01_data { + bias-pull-down; +}; + +&lpass_dmic23_clk { + drive-strength = <8>; + bias-disable; +}; + +&lpass_dmic23_clk_sleep { + drive-strength = <2>; +}; + +&lpass_dmic23_data { + bias-pull-down; +}; + +&lpass_rx_swr_clk { + drive-strength = <2>; + slew-rate = <1>; + bias-disable; +}; + +&lpass_rx_swr_clk_sleep { + bias-pull-down; +}; + +&lpass_rx_swr_data { + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; +}; + +&lpass_rx_swr_data_sleep { + bias-pull-down; +}; + +&lpass_tx_swr_clk { + drive-strength = <2>; + slew-rate = <1>; + bias-disable; +}; + +&lpass_tx_swr_clk_sleep { + bias-pull-down; +}; + +&lpass_tx_swr_data { + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; +}; &pm8350c_gpios { gpio-line-names = "FLASH_STROBE_1", /* 1 */ diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts index b69ca09d9bfb..c1647a85a371 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts @@ -128,6 +128,17 @@ ts_i2c: &i2c13 { status = "okay"; }; +/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ + +/* + * This pin goes to the display panel but then doesn't actually do anything + * on the panel itself (it doesn't connect to the touchscreen controller). + * We'll set a pullup here just to park the line. + */ +&ts_rst_conn { + bias-pull-up; +}; + /* PINCTRL - BOARD-SPECIFIC */ /* diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts index d3d6ffad4eff..2cacafd8faa8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts @@ -46,6 +46,25 @@ ap_tp_i2c: &i2c0 { }; }; +ts_i2c: &i2c13 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@10 { + compatible = "elan,ekth6915"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>; + + interrupt-parent = <&tlmm>; + interrupts = <55 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; + + vcc33-supply = <&ts_avdd>; + }; +}; + &ap_sar_sensor_i2c { status = "okay"; }; @@ -76,11 +95,21 @@ ap_tp_i2c: &i2c0 { status = "okay"; }; +&pwmleds { + status = "okay"; +}; + /* For eMMC */ &sdhc_1 { status = "okay"; }; +/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ + +&ts_rst_conn { + bias-disable; +}; + /* PINCTRL - BOARD-SPECIFIC */ /* diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 9cb1bc8ed6b5..ed8008174a33 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -15,6 +15,7 @@ #include <dt-bindings/input/gpio-keys.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include "sc7280-qcard.dtsi" #include "sc7280-chrome-common.dtsi" @@ -295,12 +296,12 @@ /* BOARD-SPECIFIC TOP LEVEL NODES */ - pwmleds { + pwmleds: pwmleds { compatible = "pwm-leds"; status = "disabled"; keyboard_backlight: keyboard-backlight { - status = "disabled"; label = "cros_ec::kbd_backlight"; + function = LED_FUNCTION_KBD_BACKLIGHT; pwms = <&cros_ec_pwm 0>; max-brightness = <1023>; }; @@ -388,7 +389,7 @@ ap_sar_sensor_i2c: &i2c1 { vdd-supply = <&pp1800_prox>; - label = "proximity-wifi-lte0"; + label = "proximity-wifi_cellular-0"; status = "disabled"; }; @@ -404,7 +405,7 @@ ap_sar_sensor_i2c: &i2c1 { vdd-supply = <&pp1800_prox>; - label = "proximity-wifi-lte1"; + label = "proximity-wifi_cellular-1"; status = "disabled"; }; }; @@ -429,6 +430,15 @@ ap_i2c_tpm: &i2c14 { status = "okay"; }; +&mdss_dp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp_hot_plug_det>; + data-lanes = <0 1>; + vdda-1p2-supply = <&vdd_a_usbssdp_0_1p2>; + vdda-0p9-supply = <&vdd_a_usbssdp_0_core>; +}; + &mdss_mdp { status = "okay"; }; @@ -476,6 +486,10 @@ ap_i2c_tpm: &i2c14 { cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; }; +&spi_flash { + spi-max-frequency = <50000000>; +}; + /* Fingerprint, enabled on a per-board basis */ ap_spi_fp: &spi9 { pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs_gpio_init_high>, <&qup_spi9_cs_gpio>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 5eb668991e24..a74e0b730db6 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -27,7 +27,7 @@ pinctrl-names = "default"; pinctrl-0 = <&key_vol_up_default>; - volume-up { + key-volume-up { label = "volume_up"; gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -367,8 +367,84 @@ bias-disable; }; +&lpass_dmic01_clk { + drive-strength = <8>; + bias-disable; +}; + +&lpass_dmic01_clk_sleep { + drive-strength = <2>; +}; + +&lpass_dmic01_data { + bias-pull-down; +}; + +&lpass_dmic23_clk { + drive-strength = <8>; + bias-disable; +}; + +&lpass_dmic23_clk_sleep { + drive-strength = <2>; +}; + +&lpass_dmic23_data { + bias-pull-down; +}; + +&lpass_rx_swr_clk { + drive-strength = <2>; + slew-rate = <1>; + bias-disable; +}; + +&lpass_rx_swr_clk_sleep { + bias-pull-down; +}; + +&lpass_rx_swr_data { + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; +}; + +&lpass_rx_swr_data_sleep { + bias-pull-down; +}; + +&lpass_tx_swr_clk { + drive-strength = <2>; + slew-rate = <1>; + bias-disable; +}; + +&lpass_tx_swr_clk_sleep { + bias-pull-down; +}; + +&lpass_tx_swr_data { + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; +}; + +&mi2s1_data0 { + drive-strength = <6>; + bias-disable; +}; + +&mi2s1_sclk { + drive-strength = <6>; + bias-disable; +}; + +&mi2s1_ws { + drive-strength = <6>; +}; + &pm7325_gpios { - key_vol_up_default: key-vol-up-default { + key_vol_up_default: key-vol-up-state { pins = "gpio6"; function = "normal"; input-enable; @@ -560,14 +636,3 @@ bias-pull-down; }; }; - -&remoteproc_wpss { - status = "okay"; -}; - -&wifi { - status = "okay"; - wifi-firmware { - iommus = <&apps_smmu 0x1c02 0x1>; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index d59002d4492e..4c25ffc39535 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -123,6 +123,12 @@ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; + vreg_l17b_1p8: ldo17 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + vdd_px_wcd9385: vdd_txrx: vddpx_0: @@ -517,7 +523,7 @@ mos_bt_uart: &uart7 { */ &pm8350c_gpios { - pmic_edp_bl_en: pmic-edp-bl-en { + pmic_edp_bl_en: pmic-edp-bl-en-state { pins = "gpio7"; function = "normal"; bias-disable; @@ -527,7 +533,7 @@ mos_bt_uart: &uart7 { output-low; }; - pmic_edp_bl_pwm: pmic-edp-bl-pwm { + pmic_edp_bl_pwm: pmic-edp-bl-pwm-state { pins = "gpio8"; function = "func1"; bias-disable; @@ -604,7 +610,6 @@ mos_bt_uart: &uart7 { ts_rst_conn: ts-rst-conn { pins = "gpio54"; function = "gpio"; - bias-pull-up; drive-strength = <2>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e66fc67de206..ef431c954ab5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -417,7 +417,7 @@ }; }; - cpu0_opp_table: cpu0-opp-table { + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; @@ -477,7 +477,7 @@ }; }; - cpu4_opp_table: cpu4-opp-table { + cpu4_opp_table: opp-table-cpu4 { compatible = "operating-points-v2"; opp-shared; @@ -547,7 +547,7 @@ }; }; - cpu7_opp_table: cpu7-opp-table { + cpu7_opp_table: opp-table-cpu7 { compatible = "operating-points-v2"; opp-shared; @@ -763,7 +763,7 @@ method = "smc"; }; - qspi_opp_table: qspi-opp-table { + qspi_opp_table: opp-table-qspi { compatible = "operating-points-v2"; opp-75000000 { @@ -787,7 +787,7 @@ }; }; - qup_opp_table: qup-opp-table { + qup_opp_table: opp-table-qup { compatible = "operating-points-v2"; opp-75000000 { @@ -818,7 +818,7 @@ reg = <0 0x00100000 0 0x1f0000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <0>, <&pcie1_lane 0>, + <0>, <&pcie1_lane>, <0>, <0>, <0>, <0>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk", @@ -857,7 +857,7 @@ }; }; - sdhc_1: sdhci@7c4000 { + sdhc_1: mmc@7c4000 { compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; @@ -873,10 +873,10 @@ <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; @@ -2035,7 +2035,7 @@ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, - <&pcie1_lane 0>, + <&pcie1_lane>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, @@ -2110,7 +2110,7 @@ clock-names = "pipe0"; #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clock-output-names = "pcie_1_pipe_clk"; }; }; @@ -2201,7 +2201,7 @@ lpasscore: clock-controller@3900000 { compatible = "qcom,sc7280-lpasscorecc"; reg = <0 0x03900000 0 0x50000>; - clocks = <&rpmhcc RPMH_CXO_CLK>; + clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "bi_tcxo"; power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; #clock-cells = <1>; @@ -2224,6 +2224,98 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sc7280-lpass-lpi-pinctrl"; + reg = <0 0x033c0000 0x0 0x20000>, + <0 0x03550000 0x0 0x10000>; + qcom,adsp-bypass-mode; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 15>; + + #clock-cells = <1>; + + lpass_dmic01_clk: dmic01-clk { + pins = "gpio6"; + function = "dmic1_clk"; + }; + + lpass_dmic01_clk_sleep: dmic01-clk-sleep { + pins = "gpio6"; + function = "dmic1_clk"; + }; + + lpass_dmic01_data: dmic01-data { + pins = "gpio7"; + function = "dmic1_data"; + }; + + lpass_dmic01_data_sleep: dmic01-data-sleep { + pins = "gpio7"; + function = "dmic1_data"; + }; + + lpass_dmic23_clk: dmic23-clk { + pins = "gpio8"; + function = "dmic2_clk"; + }; + + lpass_dmic23_clk_sleep: dmic23-clk-sleep { + pins = "gpio8"; + function = "dmic2_clk"; + }; + + lpass_dmic23_data: dmic23-data { + pins = "gpio9"; + function = "dmic2_data"; + }; + + lpass_dmic23_data_sleep: dmic23-data-sleep { + pins = "gpio9"; + function = "dmic2_data"; + }; + + lpass_rx_swr_clk: rx-swr-clk { + pins = "gpio3"; + function = "swr_rx_clk"; + }; + + lpass_rx_swr_clk_sleep: rx-swr-clk-sleep { + pins = "gpio3"; + function = "swr_rx_clk"; + }; + + lpass_rx_swr_data: rx-swr-data { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + }; + + lpass_rx_swr_data_sleep: rx-swr-data-sleep { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + }; + + lpass_tx_swr_clk: tx-swr-clk { + pins = "gpio0"; + function = "swr_tx_clk"; + }; + + lpass_tx_swr_clk_sleep: tx-swr-clk-sleep { + pins = "gpio0"; + function = "swr_tx_clk"; + }; + + lpass_tx_swr_data: tx-swr-data { + pins = "gpio1", "gpio2", "gpio14"; + function = "swr_tx_data"; + }; + + lpass_tx_swr_data_sleep: tx-swr-data-sleep { + pins = "gpio1", "gpio2", "gpio14"; + function = "swr_tx_data"; + }; + }; + gpu: gpu@3d00000 { compatible = "qcom,adreno-635.0", "qcom,adreno"; reg = <0 0x03d00000 0 0x40000>, @@ -2305,7 +2397,7 @@ }; gmu: gmu@3d6a000 { - compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; + compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; reg = <0 0x03d6a000 0 0x34000>, <0 0x3de0000 0 0x10000>, <0 0x0b290000 0 0x10000>; @@ -2313,13 +2405,13 @@ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hfi", "gmu"; - clocks = <&gpucc 5>, - <&gpucc 8>, - <&gcc GCC_DDRSS_GPU_AXI_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gpucc 2>, - <&gpucc 15>, - <&gpucc 11>; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; clock-names = "gmu", "cxo", "axi", @@ -2327,8 +2419,8 @@ "ahb", "hub", "smmu_vote"; - power-domains = <&gpucc 0>, - <&gpucc 1>; + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; power-domain-names = "cx", "gx"; iommus = <&adreno_smmu 5 0x400>; @@ -2377,12 +2469,12 @@ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, - <&gpucc 2>, - <&gpucc 11>, - <&gpucc 5>, - <&gpucc 15>, - <&gpucc 13>; + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; clock-names = "gcc_gpu_memnoc_gfx_clk", "gcc_gpu_snoc_dvm_gfx_clk", "gpu_cc_ahb_clk", @@ -2391,7 +2483,7 @@ "gpu_cc_hub_cx_int_clk", "gpu_cc_hub_aon_clk"; - power-domains = <&gpucc 0>; + power-domains = <&gpucc GPU_CC_CX_GDSC>; }; remoteproc_mpss: remoteproc@4080000 { @@ -2936,7 +3028,7 @@ }; }; - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; @@ -2950,10 +3042,10 @@ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; @@ -3334,7 +3426,7 @@ iommus = <&apps_smmu 0x21a2 0x0>; }; - venus_opp_table: venus-opp-table { + venus_opp_table: opp-table { compatible = "operating-points-v2"; opp-133330000 { @@ -3426,9 +3518,6 @@ "ahb", "core"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; @@ -3462,11 +3551,9 @@ "lut", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>; - assigned-clock-rates = <300000000>, - <19200000>, + assigned-clock-rates = <19200000>, <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SC7280_CX>; @@ -3733,7 +3820,7 @@ <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; - clock-names = "core_iface", + clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", @@ -3843,7 +3930,7 @@ }; aoss_qmp: power-controller@c300000 { - compatible = "qcom,sc7280-aoss-qmp"; + compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP @@ -3898,6 +3985,46 @@ function = "edp_hot"; }; + mi2s0_data0: mi2s0-data0 { + pins = "gpio98"; + function = "mi2s0_data0"; + }; + + mi2s0_data1: mi2s0-data1 { + pins = "gpio99"; + function = "mi2s0_data1"; + }; + + mi2s0_mclk: mi2s0-mclk { + pins = "gpio96"; + function = "pri_mi2s"; + }; + + mi2s0_sclk: mi2s0-sclk { + pins = "gpio97"; + function = "mi2s0_sck"; + }; + + mi2s0_ws: mi2s0-ws { + pins = "gpio100"; + function = "mi2s0_ws"; + }; + + mi2s1_data0: mi2s1-data0 { + pins = "gpio107"; + function = "mi2s1_data0"; + }; + + mi2s1_sclk: mi2s1-sclk { + pins = "gpio106"; + function = "mi2s1_sck"; + }; + + mi2s1_ws: mi2s1-ws { + pins = "gpio108"; + function = "mi2s1_ws"; + }; + pcie1_clkreq_n: pcie1-clkreq-n { pins = "gpio79"; function = "pcie1_clkreqn"; @@ -4639,8 +4766,8 @@ }; }; - imem@146a5000 { - compatible = "qcom,sc7280-imem", "syscon"; + sram@146a5000 { + compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; reg = <0 0x146a5000 0 0x6000>; #address-cells = <1>; @@ -4771,9 +4898,9 @@ }; timer@17c20000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; compatible = "arm,armv7-timer-mem"; reg = <0 0x17c20000 0 0x1000>; @@ -4781,49 +4908,49 @@ frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c21000 0 0x1000>, - <0 0x17c22000 0 0x1000>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; }; frame@17c23000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c23000 0 0x1000>; + reg = <0x17c23000 0x1000>; status = "disabled"; }; frame@17c25000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c25000 0 0x1000>; + reg = <0x17c25000 0x1000>; status = "disabled"; }; frame@17c27000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c27000 0 0x1000>; + reg = <0x17c27000 0x1000>; status = "disabled"; }; frame@17c29000 { frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c29000 0 0x1000>; + reg = <0x17c29000 0x1000>; status = "disabled"; }; frame@17c2b000 { frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c2b000 0 0x1000>; + reg = <0x17c2b000 0x1000>; status = "disabled"; }; frame@17c2d000 { frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c2d000 0 0x1000>; + reg = <0x17c2d000 0x1000>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts new file mode 100644 index 000000000000..45058ad0a1c8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -0,0 +1,427 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +#include "sc8280xp.dtsi" +#include "sc8280xp-pmics.dtsi" + +/ { + model = "Qualcomm SC8280XP CRD"; + compatible = "qcom,sc8280xp-crd", "qcom,sc8280xp"; + + aliases { + serial0 = &qup2_uart17; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pmc8280c_lpg 3 1000000>; + enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_bl>; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vreg_edp_bl: regulator-edp-bl { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_BL"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + gpio = <&pmc8280_1_gpios 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_bl_reg_en>; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8280_1_gpios 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&misc_3p3_reg_en>; + + regulator-boot-on; + regulator-always-on; + }; +}; + +&apps_rsc { + pmc8280-1-rpmh-regulators { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-l3-l5-supply = <&vreg_s11b>; + + vreg_s11b: smps11 { + regulator-name = "vreg_s11b"; + regulator-min-microvolt = <1272000>; + regulator-max-microvolt = <1272000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3b: ldo3 { + regulator-name = "vreg_l3b"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-boot-on; + regulator-always-on; + }; + + vreg_l4b: ldo4 { + regulator-name = "vreg_l4b"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l6b: ldo6 { + regulator-name = "vreg_l6b"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-boot-on; + }; + }; + + pmc8280c-rpmh-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l13c: ldo13 { + regulator-name = "vreg_l13c"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + }; + + pmc8280-2-rpmh-regulators { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-l4-supply = <&vreg_s11b>; + + vreg_l3d: ldo3 { + regulator-name = "vreg_l3d"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l4d: ldo4 { + regulator-name = "vreg_l4d"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l6d: ldo6 { + regulator-name = "vreg_l6d"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l7d: ldo7 { + regulator-name = "vreg_l7d"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l9d: ldo9 { + regulator-name = "vreg_l9d"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + }; +}; + +&pmc8280c_lpg { + status = "okay"; +}; + +&pmk8280_pon_pwrkey { + status = "okay"; +}; + +&qup0 { + status = "okay"; +}; + +&qup0_i2c4 { + clock-frequency = <400000>; + + pinctrl-names = "default"; + pinctrl-0 = <&qup0_i2c4_default>, <&ts0_default>; + + status = "okay"; + + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + }; +}; + +&qup1 { + status = "okay"; +}; + +&qup2 { + status = "okay"; +}; + +&qup2_i2c5 { + clock-frequency = <400000>; + + pinctrl-names = "default"; + pinctrl-0 = <&qup2_i2c5_default>, <&kybd_default>, <&tpad_default>; + + status = "okay"; + + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + }; + + keyboard@68 { + compatible = "hid-over-i2c"; + reg = <0x68>; + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + }; +}; + +&qup2_uart17 { + compatible = "qcom,geni-debug-uart"; + + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sc8280xp/qcadsp8280.mbn"; + + status = "okay"; +}; + +&remoteproc_nsp0 { + firmware-name = "qcom/sc8280xp/qccdsp8280.mbn"; + + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7c>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l3d>; + vccq-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l6b>; + vdda-pll-supply = <&vreg_l3b>; + + status = "okay"; +}; + +&usb_0 { + status = "okay"; +}; + +&usb_0_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode = "host"; +}; + +&usb_0_hsphy { + vdda-pll-supply = <&vreg_l9d>; + vdda18-supply = <&vreg_l1c>; + vdda33-supply = <&vreg_l7d>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l9d>; + vdda-pll-supply = <&vreg_l4d>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode = "host"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l4b>; + vdda18-supply = <&vreg_l1c>; + vdda33-supply = <&vreg_l13c>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l4b>; + vdda-pll-supply = <&vreg_l3b>; + + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; + +/* PINCTRL - additions to nodes defined in sc8280xp.dtsi */ + +&pmc8280_1_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio8"; + function = "normal"; + }; + + edp_bl_reg_en: edp-bl-reg-en-state { + pins = "gpio9"; + function = "normal"; + }; + + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio1"; + function = "normal"; + }; +}; + +&pmc8280c_gpios { + edp_bl_pwm: edp-bl-pwm-state { + pins = "gpio8"; + function = "func1"; + }; +}; + +&tlmm { + gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; + + kybd_default: kybd-default-state { + disable { + pins = "gpio102"; + function = "gpio"; + output-low; + }; + + int-n { + pins = "gpio104"; + function = "gpio"; + bias-disable; + }; + + reset { + pins = "gpio105"; + function = "gpio"; + bias-disable; + }; + }; + + qup0_i2c4_default: qup0-i2c4-default-state { + pins = "gpio171", "gpio172"; + function = "qup4"; + + bias-disable; + drive-strength = <16>; + }; + + qup2_i2c5_default: qup2-i2c5-default-state { + pins = "gpio81", "gpio82"; + function = "qup21"; + + bias-disable; + drive-strength = <16>; + }; + + tpad_default: tpad-default-state { + int-n { + pins = "gpio182"; + function = "gpio"; + bias-disable; + }; + }; + + ts0_default: ts0-default-state { + int-n { + pins = "gpio175"; + function = "gpio"; + bias-pull-up; + }; + + reset-n { + pins = "gpio99"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts new file mode 100644 index 000000000000..84dc92dda0b8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -0,0 +1,386 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +#include "sc8280xp.dtsi" +#include "sc8280xp-pmics.dtsi" + +/ { + model = "Lenovo ThinkPad X13s"; + compatible = "lenovo,thinkpad-x13s", "qcom,sc8280xp"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pmc8280c_lpg 3 1000000>; + enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_bl>; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; + }; + + vreg_edp_bl: regulator-edp-bl { + compatible = "regulator-fixed"; + + regulator-name = "VBL9"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + gpio = <&pmc8280_1_gpios 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_bl_reg_en>; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VCC3B"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8280_1_gpios 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&misc_3p3_reg_en>; + + regulator-boot-on; + regulator-always-on; + }; +}; + +&apps_rsc { + pmc8280-1-rpmh-regulators { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-l3-l5-supply = <&vreg_s11b>; + + vreg_s11b: smps11 { + regulator-name = "vreg_s11b"; + regulator-min-microvolt = <1272000>; + regulator-max-microvolt = <1272000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3b: ldo3 { + regulator-name = "vreg_l3b"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-boot-on; + }; + + vreg_l4b: ldo4 { + regulator-name = "vreg_l4b"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l6b: ldo6 { + regulator-name = "vreg_l6b"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-boot-on; + regulator-always-on; // FIXME: VDD_A_EDP_0_0P9 + }; + }; + + pmc8280c-rpmh-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l12c: ldo12 { + regulator-name = "vreg_l12c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l13c: ldo13 { + regulator-name = "vreg_l13c"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + }; + + pmc8280-2-rpmh-regulators { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-l4-supply = <&vreg_s11b>; + + vreg_l3d: ldo3 { + regulator-name = "vreg_l3d"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l4d: ldo4 { + regulator-name = "vreg_l4d"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l7d: ldo7 { + regulator-name = "vreg_l7d"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l9d: ldo9 { + regulator-name = "vreg_l9d"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + }; +}; + +&pmc8280c_lpg { + status = "okay"; +}; + +&pmk8280_pon_pwrkey { + status = "okay"; +}; + +&qup0 { + status = "okay"; +}; + +&qup0_i2c4 { + clock-frequency = <400000>; + + pinctrl-names = "default"; + pinctrl-0 = <&qup0_i2c4_default>, <&ts0_default>; + + status = "okay"; + + /* FIXME: verify */ + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + }; +}; + +&qup1 { + status = "okay"; +}; + +&qup2 { + status = "okay"; +}; + +&qup2_i2c5 { + clock-frequency = <400000>; + + pinctrl-names = "default"; + pinctrl-0 = <&qup2_i2c5_default>, <&kybd_default>, <&tpad_default>; + + status = "okay"; + + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + }; + + keyboard@68 { + compatible = "hid-over-i2c"; + reg = <0x68>; + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + }; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sc8280xp/qcadsp8280.mbn"; + + status = "okay"; +}; + +&remoteproc_nsp0 { + firmware-name = "qcom/sc8280xp/qccdsp8280.mbn"; + + status = "okay"; +}; + +&usb_0 { + status = "okay"; +}; + +&usb_0_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode = "host"; +}; + +&usb_0_hsphy { + vdda-pll-supply = <&vreg_l9d>; + vdda18-supply = <&vreg_l1c>; + vdda33-supply = <&vreg_l7d>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l9d>; + vdda-pll-supply = <&vreg_l4d>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode = "host"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l4b>; + vdda18-supply = <&vreg_l1c>; + vdda33-supply = <&vreg_l13c>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l4b>; + vdda-pll-supply = <&vreg_l3b>; + + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; + +/* PINCTRL */ + +&pmc8280_1_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio8"; + function = "normal"; + }; + + edp_bl_reg_en: edp-bl-reg-en-state { + pins = "gpio9"; + function = "normal"; + }; + + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio1"; + function = "normal"; + }; +}; + +&pmc8280c_gpios { + edp_bl_pwm: edp-bl-pwm-state { + pins = "gpio8"; + function = "func1"; + }; +}; + +&tlmm { + gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; + + kybd_default: kybd-default-state { + disable { + pins = "gpio102"; + function = "gpio"; + output-low; + }; + + int-n { + pins = "gpio104"; + function = "gpio"; + bias-disable; + }; + + reset { + pins = "gpio105"; + function = "gpio"; + bias-disable; + }; + }; + + qup0_i2c4_default: qup0-i2c4-default-state { + pins = "gpio171", "gpio172"; + function = "qup4"; + bias-disable; + drive-strength = <16>; + }; + + qup2_i2c5_default: qup2-i2c5-default-state { + pins = "gpio81", "gpio82"; + function = "qup21"; + bias-disable; + drive-strength = <16>; + }; + + tpad_default: tpad-default-state { + int-n { + pins = "gpio182"; + function = "gpio"; + bias-disable; + }; + }; + + ts0_default: ts0-default-state { + int-n { + pins = "gpio175"; + function = "gpio"; + bias-pull-up; + }; + + reset-n { + pins = "gpio99"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi new file mode 100644 index 000000000000..ae90b97aecb8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +&spmi_bus { + pmk8280: pmic@0 { + compatible = "qcom,pmk8350", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmk8280_pon: pon@1300 { + compatible = "qcom,pm8998-pon"; + reg = <0x1300>; + + pmk8280_pon_pwrkey: pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = <KEY_POWER>; + status = "disabled"; + }; + }; + }; + + pmc8280_1: pmic@1 { + compatible = "qcom,pm8350", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmc8280_1_gpios: gpio@8800 { + compatible = "qcom,pm8350-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmc8280_1_gpios 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmc8280c: pmic@2 { + compatible = "qcom,pm8350c", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmc8280c_gpios: gpio@8800 { + compatible = "qcom,pm8350c-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmc8280c_gpios 0 0 9>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmc8280c_lpg: lpg@e800 { + compatible = "qcom,pm8350c-pwm"; + reg = <0xe800>; + + #address-cells = <1>; + #size-cells = <0>; + + #pwm-cells = <2>; + + status = "disabled"; + }; + }; + + pmc8280_2: pmic@3 { + compatible = "qcom,pm8350", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmc8280_2_gpios: gpio@8800 { + compatible = "qcom,pm8350-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmc8280_2_gpios 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmr735a: pmic@4 { + compatible = "qcom,pmr735a", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmr735a_gpios: gpio@8800 { + compatible = "qcom,pmr735a-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmr735a_gpios 0 0 4>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi new file mode 100644 index 000000000000..7945cbb57bb4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -0,0 +1,2139 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> +#include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/interconnect/qcom,sc8280xp.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + clocks { + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + }; + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + }; + opp-595200000 { + opp-hz = /bits/ 64 <595200000>; + }; + opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + }; + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + }; + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + }; + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + }; + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + }; + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + }; + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + }; + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + }; + opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + }; + opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + }; + opp-1881600000 { + opp-hz = /bits/ 64 <1881600000>; + }; + opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + }; + opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + }; + opp-2227200000 { + opp-hz = /bits/ 64 <2227200000>; + }; + opp-2342400000 { + opp-hz = /bits/ 64 <2342400000>; + }; + opp-2438400000 { + opp-hz = /bits/ 64 <2438400000>; + }; + }; + + cpu4_opp_table: cpu4-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + }; + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + }; + opp-1171200000 { + opp-hz = /bits/ 64 <1171200000>; + }; + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + }; + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + }; + opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + }; + opp-1747200000 { + opp-hz = /bits/ 64 <1747200000>; + }; + opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + }; + opp-1977600000 { + opp-hz = /bits/ 64 <1977600000>; + }; + opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + }; + opp-2169600000 { + opp-hz = /bits/ 64 <2169600000>; + }; + opp-2284800000 { + opp-hz = /bits/ 64 <2284800000>; + }; + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + }; + opp-2496000000 { + opp-hz = /bits/ 64 <2496000000>; + }; + opp-2592000000 { + opp-hz = /bits/ 64 <2592000000>; + }; + opp-2688000000 { + opp-hz = /bits/ 64 <2688000000>; + }; + opp-2803200000 { + opp-hz = /bits/ 64 <2803200000>; + }; + opp-2899200000 { + opp-hz = /bits/ 64 <2899200000>; + }; + opp-2995200000 { + opp-hz = /bits/ 64 <2995200000>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <602>; + next-level-cache = <&L2_0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <602>; + next-level-cache = <&L2_100>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <602>; + next-level-cache = <&L2_200>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <602>; + next-level-cache = <&L2_300>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_400>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + #cooling-cells = <2>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_500>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + #cooling-cells = <2>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_600>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + #cooling-cells = <2>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_700>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + #cooling-cells = <2>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <355>; + exit-latency-us = <909>; + min-residency-us = <3934>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <241>; + exit-latency-us = <1461>; + min-residency-us = <4488>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-power-collapse"; + arm,psci-suspend-param = <0x4100c344>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9987>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sc8280xp", "qcom,scm"; + }; + }; + + aggre1_noc: interconnect-aggre1-noc { + compatible = "qcom,sc8280xp-aggre1-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect-aggre2-noc { + compatible = "qcom,sc8280xp-aggre2-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + clk_virt: interconnect-clk-virt { + compatible = "qcom,sc8280xp-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect-config-noc { + compatible = "qcom,sc8280xp-config-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + dc_noc: interconnect-dc-noc { + compatible = "qcom,sc8280xp-dc-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect-gem-noc { + compatible = "qcom,sc8280xp-gem-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_noc: interconnect-lpass-ag-noc { + compatible = "qcom,sc8280xp-lpass-ag-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-mc-virt { + compatible = "qcom,sc8280xp-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect-mmss-noc { + compatible = "qcom,sc8280xp-mmss-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nspa_noc: interconnect-nspa-noc { + compatible = "qcom,sc8280xp-nspa-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nspb_noc: interconnect-nspb-noc { + compatible = "qcom,sc8280xp-nspb-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect-system-noc { + compatible = "qcom,sc8280xp-system-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; + }; + + qup_opp_table_100mhz: qup-100mhz-opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + reserved-region@80000000 { + reg = <0 0x80000000 0 0x860000>; + no-map; + }; + + cmd_db: cmd-db-region@80860000 { + compatible = "qcom,cmd-db"; + reg = <0 0x80860000 0 0x20000>; + no-map; + }; + + reserved-region@80880000 { + reg = <0 0x80880000 0 0x80000>; + no-map; + }; + + smem_mem: smem-region@80900000 { + compatible = "qcom,smem"; + reg = <0 0x80900000 0 0x200000>; + no-map; + hwlocks = <&tcsr_mutex 3>; + }; + + reserved-region@80b00000 { + reg = <0 0x80b00000 0 0x100000>; + no-map; + }; + + reserved-region@83b00000 { + reg = <0 0x83b00000 0 0x1700000>; + no-map; + }; + + reserved-region@85b00000 { + reg = <0 0x85b00000 0 0xc00000>; + no-map; + }; + + pil_adsp_mem: adsp-region@86c00000 { + reg = <0 0x86c00000 0 0x2000000>; + no-map; + }; + + pil_nsp0_mem: cdsp0-region@8a100000 { + reg = <0 0x8a100000 0 0x1e00000>; + no-map; + }; + + pil_nsp1_mem: cdsp1-region@8c600000 { + reg = <0 0x8c600000 0 0x1e00000>; + no-map; + }; + + reserved-region@aeb00000 { + reg = <0 0xaeb00000 0 0x16600000>; + no-map; + }; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-nsp0 { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_nsp0_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_nsp0_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-nsp1 { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_NSP1 + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <12>; + + smp2p_nsp1_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_nsp1_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sc8280xp"; + reg = <0x0 0x00100000 0x0 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&usb_0_ssphy>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&usb_1_ssphy>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + }; + + ipcc: mailbox@408000 { + compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; + reg = <0 0x00408000 0 0x1000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + qup2: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x008c0000 0 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0xa3 0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + qup2_uart17: serial@884000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00884000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + operating-points-v2 = <&qup_opp_table_100mhz>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + qup2_i2c5: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + }; + + qup0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x009c0000 0 0x6000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0x563 0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + qup0_i2c4: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00990000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + }; + + qup1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x00ac0000 0 0x6000>; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0x83 0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + }; + + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0xe0 0x0>; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz = <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sc8280xp-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0xe10>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "ref", + "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: phy@1d87400 { + reg = <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, + <0 0x01d87800 0 0x108>, + <0 0x01d87a00 0 0x1e0>; + #phy-cells = <0>; + }; + }; + + ufs_card_hc: ufs@1da4000 { + compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01da4000 0 0x3000>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufs_card_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_CARD_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_CARD_GDSC>; + + iommus = <&apps_smmu 0x4a0 0x0>; + + clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, + <&gcc GCC_UFS_CARD_AHB_CLK>, + <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz = <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; + }; + + ufs_card_phy: phy@1da7000 { + compatible = "qcom,sc8280xp-qmp-ufs-phy"; + reg = <0 0x01da7000 0 0xe10>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "ref", + "ref_aux"; + clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, + <&gcc GCC_UFS_CARD_PHY_AUX_CLK>; + + resets = <&ufs_card_hc 0>; + reset-names = "ufsphy"; + + status = "disabled"; + + ufs_card_phy_lanes: phy@1da7400 { + reg = <0 0x01da7400 0 0x108>, + <0 0x01da7600 0 0x1e0>, + <0 0x01da7c00 0 0x1dc>, + <0 0x01da7800 0 0x108>, + <0 0x01da7a00 0 0x1e0>; + #phy-cells = <0>; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + usb_0_hsphy: phy@88e5000 { + compatible = "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088e5000 0 0x400>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_2_hsphy0: phy@88e7000 { + compatible = "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088e7000 0 0x400>; + clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_2_hsphy1: phy@88e8000 { + compatible = "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088e8000 0 0x400>; + clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_2_hsphy2: phy@88e9000 { + compatible = "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088e9000 0 0x400>; + clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_2_hsphy3: phy@88ea000 { + compatible = "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088ea000 0 0x400>; + clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_2_qmpphy0: phy-wrapper@88ef000 { + compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; + reg = <0 0x088ef000 0 0x1c8>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP0_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + + resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; + reset-names = "phy", "common"; + + power-domains = <&gcc USB30_MP_GDSC>; + + status = "disabled"; + + usb_2_ssphy0: phy@88efe00 { + reg = <0 0x088efe00 0 0x160>, + <0 0x088f0000 0 0x1ec>, + <0 0x088ef200 0 0x1f0>; + #phy-cells = <0>; + #clock-cells = <0>; + clocks = <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb2_phy0_pipe_clk"; + }; + }; + + usb_2_qmpphy1: phy-wrapper@88f1000 { + compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; + reg = <0 0x088f1000 0 0x1c8>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP1_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + + resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; + reset-names = "phy", "common"; + + power-domains = <&gcc USB30_MP_GDSC>; + + status = "disabled"; + + usb_2_ssphy1: phy@88f1e00 { + reg = <0 0x088f1e00 0 0x160>, + <0 0x088f2000 0 0x1ec>, + <0 0x088f1200 0 0x1f0>; + #phy-cells = <0>; + #clock-cells = <0>; + clocks = <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb2_phy1_pipe_clk"; + }; + }; + + remoteproc_adsp: remoteproc@3000000 { + compatible = "qcom,sc8280xp-adsp-pas"; + reg = <0 0x03000000 0 0x100>; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SC8280XP_LCX>, + <&rpmhpd SC8280XP_LMX>; + power-domain-names = "lcx", "lmx"; + + memory-region = <&pil_adsp_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + }; + }; + + usb_0_qmpphy: phy-wrapper@88ec000 { + compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; + reg = <0 0x088ec000 0 0x1e4>, + <0 0x088eb000 0 0x40>, + <0 0x088ed000 0 0x1c8>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB4_EUD_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + status = "disabled"; + + usb_0_ssphy: usb3-phy@88eb400 { + reg = <0 0x088eb400 0 0x100>, + <0 0x088eb600 0 0x3ec>, + <0 0x088ec400 0 0x1f0>, + <0 0x088eba00 0 0x100>, + <0 0x088ebc00 0 0x3ec>, + <0 0x088ec700 0 0x64>; + #phy-cells = <0>; + #clock-cells = <0>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb0_phy_pipe_clk_src"; + }; + + usb_0_dpphy: dp-phy@88ed200 { + reg = <0 0x088ed200 0 0x200>, + <0 0x088ed400 0 0x200>, + <0 0x088eda00 0 0x200>, + <0 0x088ea600 0 0x200>, + <0 0x088ea800 0 0x200>; + #clock-cells = <1>; + #phy-cells = <0>; + }; + }; + + usb_1_hsphy: phy@8902000 { + compatible = "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x08902000 0 0x400>; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + + status = "disabled"; + }; + + usb_1_qmpphy: phy-wrapper@8904000 { + compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; + reg = <0 0x08904000 0 0x1e4>, + <0 0x08903000 0 0x40>, + <0 0x08905000 0 0x1c8>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB4_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + + resets = <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + power-domains = <&gcc USB30_SEC_GDSC>; + + status = "disabled"; + + usb_1_ssphy: usb3-phy@8903400 { + reg = <0 0x08903400 0 0x100>, + <0 0x08903c00 0 0x3ec>, + <0 0x08904400 0 0x1f0>, + <0 0x08903a00 0 0x100>, + <0 0x08903c00 0 0x3ec>, + <0 0x08904200 0 0x18>; + #phy-cells = <0>; + #clock-cells = <0>; + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb1_phy_pipe_clk_src"; + }; + + usb_1_dpphy: dp-phy@8904200 { + reg = <0 0x08904200 0 0x200>, + <0 0x08904400 0 0x200>, + <0 0x08904a00 0 0x200>, + <0 0x08904600 0 0x200>, + <0 0x08904800 0 0x200>; + #clock-cells = <1>; + #phy-cells = <0>; + }; + }; + + system-cache-controller@9200000 { + compatible = "qcom,sc8280xp-llcc"; + reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; + }; + + usb_0: usb@a6f8800 { + compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "core", "iface", "bus_aggr", "utmi", "sleep", + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + status = "disabled"; + + usb_0_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x820 0x0>; + phys = <&usb_0_hsphy>, <&usb_0_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usb_1: usb@a8f8800 { + compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; + reg = <0 0x0a8f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "core", "iface", "bus_aggr", "utmi", "sleep", + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 12 IRQ_TYPE_EDGE_BOTH>, + <&pdc 13 IRQ_TYPE_EDGE_BOTH>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains = <&gcc USB30_SEC_GDSC>; + + resets = <&gcc GCC_USB30_SEC_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + status = "disabled"; + + usb_1_dwc3: usb@a800000 { + compatible = "snps,dwc3"; + reg = <0 0x0a800000 0 0xcd00>; + interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x860 0x0>; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; + qcom,pdc-ranges = <0 480 40>, + <40 140 14>, + <54 263 1>, + <55 306 4>, + <59 312 3>, + <62 374 2>, + <64 434 2>, + <66 438 3>, + <69 86 1>, + <70 520 54>, + <124 609 28>, + <159 638 1>, + <160 720 8>, + <168 801 1>, + <169 728 30>, + <199 416 2>, + <201 449 1>, + <202 89 1>, + <203 451 1>, + <204 462 1>, + <205 264 1>, + <206 579 1>, + <207 653 1>, + <208 656 1>, + <209 659 1>, + <210 122 1>, + <211 699 1>, + <212 705 1>, + <213 450 1>, + <214 643 1>, + <216 646 5>, + <221 390 5>, + <226 700 3>, + <229 240 3>, + <232 269 1>, + <233 377 1>, + <234 372 1>, + <235 138 1>, + <236 857 1>, + <237 860 1>, + <238 137 1>, + <239 668 1>, + <240 366 1>, + <241 949 1>, + <242 815 5>, + <247 769 1>, + <248 768 1>, + <249 663 1>, + <250 799 2>, + <252 798 1>, + <253 765 1>, + <254 763 1>, + <255 454 1>, + <258 139 1>, + <259 786 2>, + <261 370 2>, + <263 158 2>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; + reg = <0 0x0c263000 0 0x1ff>, /* TM */ + <0 0x0c222000 0 0x8>; /* SROT */ + #qcom,sensors = <14>; + interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; + reg = <0 0x0c265000 0 0x1ff>, /* TM */ + <0 0x0c223000 0 0x8>; /* SROT */ + #qcom,sensors = <16>; + interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + aoss_qmp: power-controller@c300000 { + compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c300000 0 0x400>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0x0c440000 0 0x1100>, + <0 0x0c600000 0 0x2000000>, + <0 0x0e600000 0 0x100000>, + <0 0x0e700000 0 0xa0000>, + <0 0x0c40a000 0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,sc8280xp-tlmm"; + reg = <0 0x0f100000 0 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 230>; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + #redistributor-regions = <1>; + redistributor-stride = <0 0x20000>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic-its@17a40000 { + compatible = "arm,gic-v3-its"; + reg = <0 0x17a40000 0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + watchdog@17c10000 { + compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; + reg = <0 0x17c10000 0 0x1000>; + clocks = <&sleep_clk>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer@17c20000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17c20000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@17c21000 { + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c26000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, + <WAKE_TCS 3>, <CONTROL_TCS 1>; + label = "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sc8280xp-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board_clk>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sc8280xp-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@18591000 { + compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x18591000 0 0x1000>, + <0 0x18592000 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; + + remoteproc_nsp0: remoteproc@1b300000 { + compatible = "qcom,sc8280xp-nsp0-pas"; + reg = <0 0x1b300000 0 0x100>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SC8280XP_NSP>; + power-domain-names = "nsp"; + + memory-region = <&pil_nsp0_mem>; + + qcom,smem-states = <&smp2p_nsp0_out 0>; + qcom,smem-state-names = "stop"; + + interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "nsp0"; + qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x3181 0x0420>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x3182 0x0420>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x3183 0x0420>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x3184 0x0420>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x3185 0x0420>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x3186 0x0420>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x3187 0x0420>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x3188 0x0420>; + }; + + compute-cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + iommus = <&apps_smmu 0x318b 0x0420>; + }; + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <10>; + iommus = <&apps_smmu 0x318b 0x0420>; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + iommus = <&apps_smmu 0x318c 0x0420>; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&apps_smmu 0x318d 0x0420>; + }; + + compute-cb@13 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + iommus = <&apps_smmu 0x318e 0x0420>; + }; + + compute-cb@14 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <14>; + iommus = <&apps_smmu 0x318f 0x0420>; + }; + }; + }; + }; + + remoteproc_nsp1: remoteproc@21300000 { + compatible = "qcom,sc8280xp-nsp1-pas"; + reg = <0 0x21300000 0 0x100>; + + interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SC8280XP_NSP>; + power-domain-names = "nsp"; + + memory-region = <&pil_nsp1_mem>; + + qcom,smem-states = <&smp2p_nsp1_out 0>; + qcom,smem-state-names = "stop"; + + interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_NSP1 + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "nsp1"; + qcom,remote-pid = <12>; + }; + }; + }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 1>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 2>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 4>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 5>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 6>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 7>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 8>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cluster0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 9>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 15>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts new file mode 100644 index 000000000000..28050bc5f081 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -0,0 +1,461 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Ltd. + * Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org> + * Copyright (c) 2020, AngeloGioacchino Del Regno + * <angelogioacchino.delregno@somainline.org> + */ + +/dts-v1/; + +#include "sdm660.dtsi" +#include "pm660.dtsi" +#include "pm660l.dtsi" + +/ { + model = "Inforce 6560 Single Board Computer"; + compatible = "inforce,ifc6560", "qcom,sda660"; + chassis-type = "embedded"; /* SBC */ + + aliases { + serial0 = &blsp1_uart2; + serial1 = &blsp2_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + volup { + label = "Volume Up"; + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <15>; + }; + }; + + /* + * Until we hook up type-c detection, we + * have to stick with this. But it works. + */ + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7533_out>; + }; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + + regulator-always-on; + regulator-boot-on; + }; + + v3p3_bck_bst: v3p3-bck-bst-regulator { + compatible = "regulator-fixed"; + regulator-name = "v3p3_bck_bst"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vph_pwr>; + }; + + v1p2_ldo: v1p2-ldo-regulator { + compatible = "regulator-fixed"; + regulator-name = "v1p2_ldo"; + + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + vin-supply = <&vph_pwr>; + }; + + v5p0_boost: v5p0-boost-regulator { + compatible = "regulator-fixed"; + regulator-name = "v5p0_boost"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&vph_pwr>; + }; +}; + +&adsp_pil { + firmware-name = "qcom/ifc6560/adsp.mbn"; +}; + +&blsp_i2c6 { + status = "okay"; + + adv7533: hdmi@39 { + compatible = "adi,adv7535"; + reg = <0x39>, <0x66>; + reg-names = "main", "edid"; + + interrupt-parent = <&pm660l_gpios>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + clocks = <&rpmcc RPM_SMD_BB_CLK2>; + clock-names = "cec"; + /* + * Limit to 3 lanes to prevent the bridge from changing amount + * of lanes in the fly. MSM DSI host doesn't like that. + */ + adi,dsi-lanes = <3>; + avdd-supply = <&vreg_l13a_1p8>; + dvdd-supply = <&vreg_l13a_1p8>; + pvdd-supply = <&vreg_l13a_1p8>; + a2vdd-supply = <&vreg_l13a_1p8>; + v3p3-supply = <&v3p3_bck_bst>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7533_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + adv7533_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&blsp1_dma { + /* + * The board will lock up if we toggle the BLSP clock, unless the + * BAM DMA interconnects support is in place. + */ + /delete-property/ clocks; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&blsp2_dma { + /* + * The board will lock up if we toggle the BLSP clock, unless the + * BAM DMA interconnects support is in place. + */ + /delete-property/ clocks; +}; + +&blsp2_uart1 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_l13a_1p8>; + vddxo-supply = <&vreg_l9a_1p8>; + vddrf-supply = <&vreg_l6a_1p3>; + vddch0-supply = <&vreg_l19a_3p3>; + max-speed = <3200000>; + }; +}; + +&dsi0 { + status = "okay"; + vdda-supply = <&vreg_l1a_1p225>; +}; + +&dsi0_out { + remote-endpoint = <&adv7533_in>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + status = "okay"; + vcca-supply = <&vreg_l1b_0p925>; +}; + +&mdss { + status = "okay"; +}; + +&mmss_smmu { + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + + linux,code = <KEY_VOLUMEUP>; +}; + +&qusb2phy0 { + status = "okay"; + + vdd-supply = <&vreg_l1b_0p925>; + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; +}; + +&qusb2phy1 { + status = "okay"; + + vdd-supply = <&vreg_l1b_0p925>; + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; +}; + +&rpm_requests { + pm660-regulators { + compatible = "qcom,rpm-pm660-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>; + vdd_l2_l3-supply = <&vreg_s2b_1p05>; + vdd_l5-supply = <&vreg_s2b_1p05>; + vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>; + vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>; + + vreg_s4a_2p04: s4 { + regulator-min-microvolt = <1805000>; + regulator-max-microvolt = <2040000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + vreg_s5a_1p35: s5 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1350000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_l1a_1p225: l1 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l6a_1p3: l6 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1368000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l8a_1p8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-system-load = <325000>; + regulator-allow-set-load; + }; + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1804000>; + regulator-max-microvolt = <1896000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l13a_1p8: l13 { + /* This gives power to the LPDDR4: never turn it off! */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1944000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_l19a_3p3: l19 { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + }; + + pm660l-regulators { + compatible = "qcom,rpm-pm660l-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>; + vdd_l2-supply = <&vreg_bob>; + vdd_l3_l5_l7_l8-supply = <&vreg_bob>; + vdd_l4_l6-supply = <&vreg_bob>; + vdd_bob-supply = <&vph_pwr>; + + vreg_s2b_1p05: s2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_l1b_0p925: l1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <925000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l2b_2p95: l2 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l4b_2p95: l4 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + + regulator-min-microamp = <200>; + regulator-max-microamp = <600000>; + regulator-system-load = <570000>; + regulator-allow-set-load; + }; + + /* + * Downstream specifies a range of 1721-3600mV, + * but the only assigned consumers are SDHCI2 VMMC + * and Coresight QPDI that both request pinned 2.95V. + * Tighten the range to 1.8-3.328 (closest to 3.3) to + * make the mmc driver happy. + */ + vreg_l5b_2p95: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3328000>; + regulator-enable-ramp-delay = <250>; + regulator-system-load = <800000>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l7b_3p125: l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3125000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8b_3p3: l8 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3624000>; + regulator-enable-ramp-delay = <500>; + regulator-ramp-delay = <0>; + }; + }; +}; + +&sdc2_state_on { + sd-cd { + pins = "gpio54"; + bias-pull-up; + drive-strength = <2>; + }; +}; + +&sdc2_state_off { + sd-cd { + pins = "gpio54"; + bias-disable; + drive-strength = <2>; + }; +}; + +&sdhc_1 { + status = "okay"; + supports-cqe; + + vmmc-supply = <&vreg_l4b_2p95>; + vqmmc-supply = <&vreg_l8a_1p8>; + + mmc-ddr-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&vreg_l5b_2p95>; + vqmmc-supply = <&vreg_l2b_2p95>; + + cd-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; + no-sdio; + no-emmc; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <8 4>; +}; + +&usb2 { + status = "okay"; +}; + +&usb2_dwc3 { + dr_mode = "host"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; + extcon = <&extcon_usb>; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 42af1fade461..09c07800793a 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/leds/common.h> / { /* required for bootloader to select correct board */ @@ -34,7 +35,7 @@ height = <1920>; stride = <(1080 * 4)>; format = "a8r8g8b8"; - status= "okay"; + status = "okay"; }; }; @@ -87,13 +88,10 @@ pinctrl-0 = <&imx300_vana_default>; }; - gpio_keys { - status = "okay"; + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - camera_focus { + key-camera-focus { label = "Camera Focus"; gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -101,7 +99,7 @@ debounce-interval = <15>; }; - camera_snapshot { + key-camera-snapshot { label = "Camera Snapshot"; gpios = <&tlmm 113 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -109,7 +107,7 @@ debounce-interval = <15>; }; - vol_down { + key-vol-down { label = "Volume Down"; gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -214,6 +212,35 @@ /* HCI Bluetooth */ }; +&pm660l_lpg { + qcom,power-source = <1>; + + status = "okay"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_BLUE>; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_RED>; + }; + }; +}; + &pon_pwrkey { status = "okay"; }; @@ -224,7 +251,7 @@ linux,code = <KEY_VOLUMEUP>; }; -&qusb2phy { +&qusb2phy0 { status = "okay"; vdd-supply = <&vreg_l1b_0p925>; @@ -549,6 +576,22 @@ }; }; +&sdc2_state_on { + sd-cd { + pins = "gpio54"; + bias-pull-up; + drive-strength = <2>; + }; +}; + +&sdc2_state_off { + sd-cd { + pins = "gpio54"; + bias-disable; + drive-strength = <2>; + }; +}; + &sdhc_1 { status = "okay"; supports-cqe; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index b72e8e6c52f3..1bc9091cad2a 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/qcom,gpucc-sdm660.h> #include <dt-bindings/clock/qcom,mmcc-sdm660.h> #include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/interconnect/qcom,sdm660.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -552,19 +553,19 @@ }; qfprom: qfprom@780000 { - compatible = "qcom,qfprom"; + compatible = "qcom,sdm630-qfprom", "qcom,qfprom"; reg = <0x00780000 0x621c>; #address-cells = <1>; #size-cells = <1>; qusb2_hstx_trim: hstx-trim@240 { - reg = <0x240 0x1>; - bits = <25 3>; + reg = <0x243 0x1>; + bits = <1 3>; }; gpu_speed_bin: gpu-speed-bin@41a0 { - reg = <0x41a0 0x1>; - bits = <21 7>; + reg = <0x41a2 0x1>; + bits = <5 7>; }; }; @@ -982,12 +983,6 @@ bias-pull-up; drive-strength = <10>; }; - - sd-cd { - pins = "gpio54"; - bias-pull-up; - drive-strength = <2>; - }; }; sdc2_state_off: sdc2-off { @@ -1008,12 +1003,6 @@ bias-pull-up; drive-strength = <2>; }; - - sd-cd { - pins = "gpio54"; - bias-disable; - drive-strength = <2>; - }; }; }; @@ -1045,13 +1034,15 @@ nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; - interconnects = <&gnoc 1 &bimc 5>; + interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>; interconnect-names = "gfx-mem"; operating-points-v2 = <&gpu_sdm630_opp_table>; + status = "disabled"; + gpu_sdm630_opp_table: opp-table { - compatible = "operating-points-v2"; + compatible = "operating-points-v2"; opp-775000000 { opp-hz = /bits/ 64 <775000000>; opp-level = <RPM_SMD_LEVEL_TURBO>; @@ -1252,19 +1243,19 @@ * haven't seen any devices making use of it. */ maximum-speed = "high-speed"; - phys = <&qusb2phy>; + phys = <&qusb2phy0>; phy-names = "usb2-phy"; snps,hird-threshold = /bits/ 8 <0>; }; }; - qusb2phy: phy@c012000 { + qusb2phy0: phy@c012000 { compatible = "qcom,sdm660-qusb2-phy"; reg = <0x0c012000 0x180>; #phy-cells = <0>; clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_RX1_USB2_CLKREF_CLK>; + <&gcc GCC_RX0_USB2_CLKREF_CLK>; clock-names = "cfg_ahb", "ref"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; @@ -1272,7 +1263,21 @@ status = "disabled"; }; - sdhc_2: sdhci@c084000 { + qusb2phy1: phy@c014000 { + compatible = "qcom,sdm660-qusb2-phy"; + reg = <0x0c014000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_RX1_USB2_CLKREF_CLK>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + nvmem-cells = <&qusb2_hstx_trim>; + status = "disabled"; + }; + + sdhc_2: mmc@c084000 { compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0c084000 0x1000>; reg-names = "hc"; @@ -1282,13 +1287,16 @@ interrupt-names = "hc_irq", "pwr_irq"; bus-width = <4>; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; + interconnects = <&a2noc 3 &a2noc 10>, <&gnoc 0 &cnoc 28>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; operating-points-v2 = <&sdhc2_opp_table>; pinctrl-names = "default", "sleep"; @@ -1322,7 +1330,7 @@ }; }; - sdhc_1: sdhci@c0c4000 { + sdhc_1: mmc@c0c4000 { compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0c0c4000 0x1000>, <0x0c0c5000 0x1000>, @@ -1333,15 +1341,15 @@ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>, <&gcc GCC_SDCC1_ICE_CORE_CLK>; - clock-names = "core", "iface", "xo", "ice"; + clock-names = "iface", "core", "xo", "ice"; interconnects = <&a2noc 2 &a2noc 10>, <&gnoc 0 &cnoc 27>; - interconnect-names = "sdhc1-ddr", "cpu-sdhc1"; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; operating-points-v2 = <&sdhc1_opp_table>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_state_on>; @@ -1377,6 +1385,47 @@ }; }; + usb2: usb@c2f8800 { + compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; + reg = <0x0c2f8800 0x400>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>; + clock-names = "cfg_noc", "core", + "mock_utmi", "sleep"; + + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates = <19200000>, <60000000>; + + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq"; + + qcom,select-utmi-as-pipe-clk; + + resets = <&gcc GCC_USB_20_BCR>; + + usb2_dwc3: usb@c200000 { + compatible = "snps,dwc3"; + reg = <0x0c200000 0xc8d0>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + /* This is the HS-only host */ + maximum-speed = "high-speed"; + phys = <&qusb2phy1>; + phy-names = "usb2-phy"; + snps,hird-threshold = /bits/ 8 <0>; + }; + }; + mmcc: clock-controller@c8c0000 { compatible = "qcom,mmcc-sdm630"; reg = <0x0c8c0000 0x40000>; @@ -1405,7 +1454,7 @@ <0>; }; - dsi_opp_table: dsi-opp-table { + dsi_opp_table: opp-table-dsi { compatible = "operating-points-v2"; opp-131250000 { @@ -1494,7 +1543,7 @@ }; }; - mdp_opp_table: mdp-opp { + mdp_opp_table: opp-table { compatible = "operating-points-v2"; opp-150000000 { @@ -1563,6 +1612,8 @@ phys = <&dsi0_phy>; phy-names = "dsi"; + status = "disabled"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1596,6 +1647,7 @@ clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; clock-names = "iface", "ref"; + status = "disabled"; }; }; @@ -1829,8 +1881,8 @@ status = "disabled"; }; - imem@146bf000 { - compatible = "simple-mfd"; + sram@146bf000 { + compatible = "qcom,sdm630-imem", "syscon", "simple-mfd"; reg = <0x146bf000 0x1000>; #address-cells = <1>; @@ -1846,138 +1898,138 @@ camss: camss@ca00000 { compatible = "qcom,sdm660-camss"; - reg = <0x0c824000 0x1000>, + reg = <0x0ca00020 0x10>, + <0x0ca30000 0x100>, + <0x0ca30400 0x100>, + <0x0ca30800 0x100>, + <0x0ca30c00 0x100>, + <0x0c824000 0x1000>, <0x0ca00120 0x4>, <0x0c825000 0x1000>, <0x0ca00124 0x4>, <0x0c826000 0x1000>, <0x0ca00128 0x4>, - <0x0ca30000 0x100>, - <0x0ca30400 0x100>, - <0x0ca30800 0x100>, - <0x0ca30c00 0x100>, <0x0ca31000 0x500>, - <0x0ca00020 0x10>, <0x0ca10000 0x1000>, <0x0ca14000 0x1000>; - reg-names = "csiphy0", + reg-names = "csi_clk_mux", + "csid0", + "csid1", + "csid2", + "csid3", + "csiphy0", "csiphy0_clk_mux", "csiphy1", "csiphy1_clk_mux", "csiphy2", "csiphy2_clk_mux", - "csid0", - "csid1", - "csid2", - "csid3", "ispif", - "csi_clk_mux", "vfe0", "vfe1"; - interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, + interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "csiphy0", - "csiphy1", - "csiphy2", - "csid0", + interrupt-names = "csid0", "csid1", "csid2", "csid3", + "csiphy0", + "csiphy1", + "csiphy2", "ispif", "vfe0", "vfe1"; - clocks = <&mmcc CAMSS_TOP_AHB_CLK>, - <&mmcc THROTTLE_CAMSS_AXI_CLK>, - <&mmcc CAMSS_ISPIF_AHB_CLK>, - <&mmcc CAMSS_CSI0PHYTIMER_CLK>, - <&mmcc CAMSS_CSI1PHYTIMER_CLK>, - <&mmcc CAMSS_CSI2PHYTIMER_CLK>, - <&mmcc CAMSS_CSI0_AHB_CLK>, - <&mmcc CAMSS_CSI0_CLK>, - <&mmcc CAMSS_CPHY_CSID0_CLK>, - <&mmcc CAMSS_CSI0PIX_CLK>, - <&mmcc CAMSS_CSI0RDI_CLK>, - <&mmcc CAMSS_CSI1_AHB_CLK>, - <&mmcc CAMSS_CSI1_CLK>, - <&mmcc CAMSS_CPHY_CSID1_CLK>, - <&mmcc CAMSS_CSI1PIX_CLK>, - <&mmcc CAMSS_CSI1RDI_CLK>, - <&mmcc CAMSS_CSI2_AHB_CLK>, - <&mmcc CAMSS_CSI2_CLK>, - <&mmcc CAMSS_CPHY_CSID2_CLK>, - <&mmcc CAMSS_CSI2PIX_CLK>, - <&mmcc CAMSS_CSI2RDI_CLK>, - <&mmcc CAMSS_CSI3_AHB_CLK>, - <&mmcc CAMSS_CSI3_CLK>, - <&mmcc CAMSS_CPHY_CSID3_CLK>, - <&mmcc CAMSS_CSI3PIX_CLK>, - <&mmcc CAMSS_CSI3RDI_CLK>, - <&mmcc CAMSS_AHB_CLK>, - <&mmcc CAMSS_VFE0_CLK>, - <&mmcc CAMSS_CSI_VFE0_CLK>, - <&mmcc CAMSS_VFE0_AHB_CLK>, - <&mmcc CAMSS_VFE0_STREAM_CLK>, - <&mmcc CAMSS_VFE1_CLK>, - <&mmcc CAMSS_CSI_VFE1_CLK>, - <&mmcc CAMSS_VFE1_AHB_CLK>, - <&mmcc CAMSS_VFE1_STREAM_CLK>, - <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, - <&mmcc CAMSS_VFE_VBIF_AXI_CLK>, - <&mmcc CSIPHY_AHB2CRIF_CLK>, - <&mmcc CAMSS_CPHY_CSID0_CLK>, - <&mmcc CAMSS_CPHY_CSID1_CLK>, - <&mmcc CAMSS_CPHY_CSID2_CLK>, - <&mmcc CAMSS_CPHY_CSID3_CLK>; - clock-names = "top_ahb", - "throttle_axi", - "ispif_ahb", - "csiphy0_timer", - "csiphy1_timer", - "csiphy2_timer", - "csi0_ahb", - "csi0", - "csi0_phy", - "csi0_pix", - "csi0_rdi", - "csi1_ahb", - "csi1", - "csi1_phy", - "csi1_pix", - "csi1_rdi", - "csi2_ahb", - "csi2", - "csi2_phy", - "csi2_pix", - "csi2_rdi", - "csi3_ahb", - "csi3", - "csi3_phy", - "csi3_pix", - "csi3_rdi", - "ahb", - "vfe0", - "csi_vfe0", - "vfe0_ahb", - "vfe0_stream", - "vfe1", - "csi_vfe1", - "vfe1_ahb", - "vfe1_stream", - "vfe_ahb", - "vfe_axi", - "csiphy_ahb2crif", - "cphy_csid0", - "cphy_csid1", - "cphy_csid2", - "cphy_csid3"; + clocks = <&mmcc CAMSS_AHB_CLK>, + <&mmcc CAMSS_CPHY_CSID0_CLK>, + <&mmcc CAMSS_CPHY_CSID1_CLK>, + <&mmcc CAMSS_CPHY_CSID2_CLK>, + <&mmcc CAMSS_CPHY_CSID3_CLK>, + <&mmcc CAMSS_CSI0_AHB_CLK>, + <&mmcc CAMSS_CSI0_CLK>, + <&mmcc CAMSS_CPHY_CSID0_CLK>, + <&mmcc CAMSS_CSI0PIX_CLK>, + <&mmcc CAMSS_CSI0RDI_CLK>, + <&mmcc CAMSS_CSI1_AHB_CLK>, + <&mmcc CAMSS_CSI1_CLK>, + <&mmcc CAMSS_CPHY_CSID1_CLK>, + <&mmcc CAMSS_CSI1PIX_CLK>, + <&mmcc CAMSS_CSI1RDI_CLK>, + <&mmcc CAMSS_CSI2_AHB_CLK>, + <&mmcc CAMSS_CSI2_CLK>, + <&mmcc CAMSS_CPHY_CSID2_CLK>, + <&mmcc CAMSS_CSI2PIX_CLK>, + <&mmcc CAMSS_CSI2RDI_CLK>, + <&mmcc CAMSS_CSI3_AHB_CLK>, + <&mmcc CAMSS_CSI3_CLK>, + <&mmcc CAMSS_CPHY_CSID3_CLK>, + <&mmcc CAMSS_CSI3PIX_CLK>, + <&mmcc CAMSS_CSI3RDI_CLK>, + <&mmcc CAMSS_CSI0PHYTIMER_CLK>, + <&mmcc CAMSS_CSI1PHYTIMER_CLK>, + <&mmcc CAMSS_CSI2PHYTIMER_CLK>, + <&mmcc CSIPHY_AHB2CRIF_CLK>, + <&mmcc CAMSS_CSI_VFE0_CLK>, + <&mmcc CAMSS_CSI_VFE1_CLK>, + <&mmcc CAMSS_ISPIF_AHB_CLK>, + <&mmcc THROTTLE_CAMSS_AXI_CLK>, + <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc CAMSS_VFE0_AHB_CLK>, + <&mmcc CAMSS_VFE0_CLK>, + <&mmcc CAMSS_VFE0_STREAM_CLK>, + <&mmcc CAMSS_VFE1_AHB_CLK>, + <&mmcc CAMSS_VFE1_CLK>, + <&mmcc CAMSS_VFE1_STREAM_CLK>, + <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, + <&mmcc CAMSS_VFE_VBIF_AXI_CLK>; + clock-names = "ahb", + "cphy_csid0", + "cphy_csid1", + "cphy_csid2", + "cphy_csid3", + "csi0_ahb", + "csi0", + "csi0_phy", + "csi0_pix", + "csi0_rdi", + "csi1_ahb", + "csi1", + "csi1_phy", + "csi1_pix", + "csi1_rdi", + "csi2_ahb", + "csi2", + "csi2_phy", + "csi2_pix", + "csi2_rdi", + "csi3_ahb", + "csi3", + "csi3_phy", + "csi3_pix", + "csi3_rdi", + "csiphy0_timer", + "csiphy1_timer", + "csiphy2_timer", + "csiphy_ahb2crif", + "csi_vfe0", + "csi_vfe1", + "ispif_ahb", + "throttle_axi", + "top_ahb", + "vfe0_ahb", + "vfe0", + "vfe0_stream", + "vfe1_ahb", + "vfe1", + "vfe1_stream", + "vfe_ahb", + "vfe_axi"; interconnects = <&mnoc 5 &bimc 5>; interconnect-names = "vfe-mem"; iommus = <&mmss_smmu 0xc00>, @@ -2158,8 +2210,6 @@ label = "lpass"; mboxes = <&apcs_glb 9>; qcom,remote-pid = <2>; - #address-cells = <1>; - #size-cells = <0>; apr { compatible = "qcom,apr-v2"; diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 8b815b2a60a7..891e314bc782 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -27,7 +27,7 @@ gpio-keys { compatible = "gpio-keys"; - volume-up { + key-volume-up { label = "volume_up"; linux,code = <KEY_VOLUMEUP>; gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts index b96da53f2f1e..58f687fc49e0 100644 --- a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts +++ b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts @@ -19,7 +19,7 @@ }; &sdc2_state_on { - pinconf-clk { + clk { drive-strength = <14>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index dcbaacf18f66..a3559f6e34a5 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -51,7 +51,7 @@ gpio-keys { compatible = "gpio-keys"; - volup { + key-volup { label = "Volume Up"; gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -103,7 +103,7 @@ linux,code = <KEY_VOLUMEDOWN>; }; -&qusb2phy { +&qusb2phy0 { status = "okay"; vdd-supply = <&vreg_l1b_0p925>; @@ -363,6 +363,30 @@ }; }; +&pm660l_wled { + status = "okay"; + + qcom,switching-freq = <800>; + qcom,current-limit-microamp = <20000>; + qcom,num-strings = <2>; +}; + +&sdc2_state_on { + sd-cd { + pins = "gpio54"; + bias-pull-up; + drive-strength = <2>; + }; +}; + +&sdc2_state_off { + sd-cd { + pins = "gpio54"; + bias-disable; + drive-strength = <2>; + }; +}; + &sdhc_1 { status = "okay"; supports-cqe; diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index 1d748c5305f4..43220af1b685 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -14,7 +14,7 @@ operating-points-v2 = <&gpu_sdm660_opp_table>; gpu_sdm660_opp_table: opp-table { - compatible = "operating-points-v2"; + compatible = "operating-points-v2"; /* * 775MHz is only available on the highest speed bin @@ -192,6 +192,8 @@ phys = <&dsi1_phy>; phy-names = "dsi"; + status = "disabled"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -225,6 +227,7 @@ clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "ref"; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index e7e4cc5936aa..b5eb8f7eca1d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -119,7 +119,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pen_eject_odl>; - pen-insert { + switch-pen-insert { label = "Pen Insert"; /* Insert = low, eject = high */ gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; @@ -130,7 +130,7 @@ }; panel: panel { - compatible ="innolux,p120zdg-bf1"; + compatible = "innolux,p120zdg-bf1"; power-supply = <&pp3300_dx_edp>; backlight = <&backlight>; no-hpd; @@ -145,6 +145,138 @@ }; }; +&psci { + /delete-node/ cpu0; + /delete-node/ cpu1; + /delete-node/ cpu2; + /delete-node/ cpu3; + /delete-node/ cpu4; + /delete-node/ cpu5; + /delete-node/ cpu6; + /delete-node/ cpu7; + /delete-node/ cpu-cluster0; +}; + +&cpus { + /delete-node/ domain-idle-states; +}; + +&cpu_idle_states { + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-power-down"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <350>; + exit-latency-us = <461>; + min-residency-us = <1890>; + local-timer-stop; + }; + + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + compatible = "arm,idle-state"; + idle-state-name = "little-rail-power-down"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <360>; + exit-latency-us = <531>; + min-residency-us = <3934>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-power-down"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <264>; + exit-latency-us = <621>; + min-residency-us = <952>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "big-rail-power-down"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <1061>; + min-residency-us = <4488>; + local-timer-stop; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "cluster-power-down"; + arm,psci-suspend-param = <0x400000F4>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9987>; + local-timer-stop; + }; +}; + +&CPU0 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU1 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU2 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU3 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU4 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU5 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU6 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU7 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + /* * Reserved memory changes * diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 194ebeb3259c..4afdb72cc556 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <dt-bindings/sound/qcom,q6afe.h> @@ -43,14 +44,14 @@ regulator-always-on; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; autorepeat; pinctrl-names = "default"; pinctrl-0 = <&vol_up_pin_a>; - vol-up { + key-vol-up { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; @@ -60,22 +61,28 @@ leds { compatible = "gpio-leds"; - user4 { + led-0 { label = "green:user4"; + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_GREEN>; gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>; linux,default-trigger = "panic-indicator"; default-state = "off"; }; - wlan { + led-1 { label = "yellow:wlan"; + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_YELLOW>; gpios = <&pm8998_gpio 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; default-state = "off"; }; - bt { + led-2 { label = "blue:bt"; + function = LED_FUNCTION_BLUETOOTH; + color = <LED_COLOR_ID_BLUE>; gpios = <&pm8998_gpio 5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; default-state = "off"; @@ -569,7 +576,7 @@ "OPTION2", "PM845_SLB"; - cam0_dvdd_1v2_en_default: cam0-dvdd-1v2-en { + cam0_dvdd_1v2_en_default: cam0-dvdd-1v2-en-state { pins = "gpio12"; function = "normal"; @@ -578,7 +585,7 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; }; - cam0_avdd_2v8_en_default: cam0-avdd-2v8-en { + cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state { pins = "gpio10"; function = "normal"; @@ -587,7 +594,7 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; }; - vol_up_pin_a: vol-up-active { + vol_up_pin_a: vol-up-active-state { pins = "gpio6"; function = "normal"; input-enable; @@ -606,10 +613,40 @@ }; }; +&pmi8998_lpg { + status = "okay"; + + qcom,power-source = <1>; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <3>; + + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + led@4 { + reg = <4>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + }; + + led@5 { + reg = <5>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + }; +}; + /* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */ &q6afedai { qi2s@22 { - reg = <22>; + reg = <QUATERNARY_MI2S_RX>; qcom,sd-lines = <0 1 2 3>; }; }; @@ -718,7 +755,7 @@ }; codec { - sound-dai = <<9611_codec 0>; + sound-dai = <<9611_codec 0>; }; }; @@ -733,7 +770,7 @@ }; codec { - sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; + sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; }; }; @@ -1144,7 +1181,8 @@ }; &camss { - vdda-supply = <&vreg_l1a_0p875>; + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; status = "ok"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi new file mode 100644 index 000000000000..20f275f8694d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -0,0 +1,614 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM845 LG G7 / V35 (judyln / judyp) common device tree + * + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +#include "sdm845.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" + +/delete-node/ &adsp_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &gpu_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &mba_region; +/delete-node/ &mpss_region; +/delete-node/ &qseecom_mem; +/delete-node/ &rmtfs_mem; +/delete-node/ &slpi_mem; +/delete-node/ &spss_mem; +/delete-node/ &venus_mem; +/delete-node/ &wlan_msa_mem; + +/ { + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + qseecom_mem: memory@b2000000 { + reg = <0 0xb2000000 0 0x1800000>; + no-map; + }; + + gpu_mem: memory@8c415000 { + reg = <0 0x8c415000 0 0x2000>; + no-map; + }; + + ipa_fw_mem: memory@8c400000 { + reg = <0 0x8c400000 0 0x10000>; + no-map; + }; + + adsp_mem: memory@8c500000 { + reg = <0 0x8c500000 0 0x1e00000>; + no-map; + }; + + wlan_msa_mem: memory@8e300000 { + reg = <0 0x8e300000 0 0x100000>; + no-map; + }; + + mpss_region: memory@8e400000 { + reg = <0 0x8e400000 0 0x8900000>; + no-map; + }; + + venus_mem: memory@96d00000 { + reg = <0 0x96d00000 0 0x500000>; + no-map; + }; + + cdsp_mem: memory@97200000 { + reg = <0 0x97200000 0 0x800000>; + no-map; + }; + + mba_region: memory@97a00000 { + reg = <0 0x97a00000 0 0x200000>; + no-map; + }; + + slpi_mem: memory@97c00000 { + reg = <0 0x97c00000 0 0x1400000>; + no-map; + }; + + spss_mem: memory@99000000 { + reg = <0 0x99000000 0 0x100000>; + no-map; + }; + + /* Framebuffer region */ + memory@9d400000 { + reg = <0x0 0x9d400000 0x0 0x2400000>; + no-map; + }; + + /* rmtfs lower guard */ + memory@f0800000 { + reg = <0 0xf0800000 0 0x1000>; + no-map; + }; + + rmtfs_mem: memory@f0801000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xf0801000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + + /* rmtfs upper guard */ + memory@f0a01000 { + reg = <0 0xf0a01000 0 0x1000>; + no-map; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_pin_a>; + + label = "GPIO Buttons"; + + key-vol-up { + label = "Volume up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + /* + * Apparently RPMh does not provide support for PM8998 S4 because it + * is always-on; model it as a fixed regulator. + */ + vreg_s4a_1p8: pm8998-smps4-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; +}; + +&adsp_pas { + status = "okay"; +}; + +&apps_rsc { + pm8998-rpmh-regulators { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + vdd-s13-supply = <&vph_pwr>; + vdd-l1-l27-supply = <&vreg_s7a_1p025>; + vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; + vdd-l3-l11-supply = <&vreg_s7a_1p025>; + vdd-l4-l5-supply = <&vreg_s7a_1p025>; + vdd-l6-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; + vdd-l9-supply = <&vreg_bob>; + vdd-l10-l23-l25-supply = <&vreg_bob>; + vdd-l13-l19-l21-supply = <&vreg_bob>; + vdd-l16-l28-supply = <&vreg_bob>; + vdd-l18-l22-supply = <&vreg_bob>; + vdd-l20-l24-supply = <&vreg_bob>; + vdd-l26-supply = <&vreg_s3a_1p35>; + vin-lvs-1-2-supply = <&vreg_s4a_1p8>; + + vreg_s2a_1p125: smps2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vdd_qusb_hs0: + vdda_hp_pcie_core: + vdda_mipi_csi0_0p9: + vdda_mipi_csi1_0p9: + vdda_mipi_csi2_0p9: + vdda_mipi_dsi0_pll: + vdda_mipi_dsi1_pll: + vdda_qlink_lv: + vdda_qlink_lv_ck: + vdda_qrefs_0p875: + vdda_pcie_core: + vdda_pll_cc_ebi01: + vdda_pll_cc_ebi23: + vdda_sp_sensor: + vdda_ufs1_core: + vdda_ufs2_core: + vdda_usb1_ss_core: + vdda_usb2_ss_core: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vddpx_10: + vreg_l2a_1p2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + }; + + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdd_wcss_cx: + vdd_wcss_mx: + vdda_wcss_pll: + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vddpx_13: + vreg_l6a_1p8: ldo6 { + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <1856000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8a_1p2: ldo8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1248000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9a_1p8: ldo9 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11a_1p0: ldo11 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1048000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdd_qfprom: + vdd_qfprom_sp: + vdda_apc1_cs_1p8: + vdda_gfx_cs_1p8: + vdda_qrefs_1p8: + vdda_qusb_hs0_1p8: + vddpx_11: + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vddpx_2: + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14a_1p88: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l18a_2p7: ldo18 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l22a_2p85: ldo22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l23a_3p3: ldo23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdda_qusb_hs0_3p1: + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdda_hp_pcie_1p2: + vdda_hv_ebi0: + vdda_hv_ebi1: + vdda_hv_ebi2: + vdda_hv_ebi3: + vdda_mipi_csi_1p25: + vdda_mipi_dsi0_1p2: + vdda_mipi_dsi1_1p2: + vdda_pcie_1p2: + vdda_ufs1_1p2: + vdda_ufs2_1p2: + vdda_usb1_ss_1p2: + vdda_usb2_ss_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l28a_3p0: ldo28 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_lvs1a_1p8: lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_lvs2a_1p8: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + pmi8998-rpmh-regulators { + compatible = "qcom,pmi8998-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-bypass; + }; + }; + + pm8005-rpmh-regulators { + compatible = "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s3c_0p6: smps3 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + }; + }; +}; + +&cdsp_pas { + status = "okay"; +}; + +&dispcc { + status = "disabled"; +}; + +&gcc { + protected-clocks = <GCC_QSPI_CORE_CLK>, + <GCC_QSPI_CORE_CLK_SRC>, + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <GCC_LPASS_Q6_AXI_CLK>, + <GCC_LPASS_SWAY_CLK>; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + }; +}; + +&ipa { + status = "okay"; + modem-init; +}; + +&mss_pil { + status = "okay"; +}; + +&pm8998_pon { + resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = <KEY_VOLUMEDOWN>; + }; +}; + +&sdhc_2 { + status = "okay"; + + cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_card_det_n>; + + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vddpx_2>; +}; + +/* + * UFS works partially and only with clk_ignore_unused. + * Sometimes it crashes with I/O errors. + */ +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <600000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vdda_ufs1_core>; + vdda-pll-supply = <&vdda_ufs1_1p2>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + /* TODO: these devices have usb id pin */ + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdd-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_qusb_hs0_1p8>; + vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; + qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; + qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vdda_usb1_ss_1p2>; + vdda-pll-supply = <&vdda_usb1_ss_core>; +}; + +/* PINCTRL - additions to nodes defined in sdm845.dtsi */ + +&tlmm { + gpio-reserved-ranges = <28 4>, <81 4>; + + sdc2_clk: sdc2-clk { + pinconf { + pins = "sdc2_clk"; + bias-disable; + + /* + * It seems that mmc_test reports errors if drive + * strength is not 16 on clk, cmd, and data pins. + * + * TODO: copy-pasted from mtp, try other values + * on these devices. + */ + drive-strength = <16>; + }; + }; + + sdc2_cmd: sdc2-cmd { + pinconf { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + sdc2_data: sdc2-data { + pinconf { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + sd_card_det_n: sd-card-det-n { + pinmux { + pins = "gpio126"; + function = "gpio"; + }; + + pinconf { + pins = "gpio126"; + bias-pull-up; + }; + }; +}; + +&pm8998_gpio { + vol_up_pin_a: vol-up-active-pins { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts new file mode 100644 index 000000000000..7d967a104b3e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM845 LG G7 (judyln) device tree. + * + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include "sdm845-lg-common.dtsi" + +/ { + model = "LG G7 ThinQ"; + compatible = "lg,judyln", "qcom,sdm845"; + + chosen { + framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9d400000 0x0 (1440 * 3120 * 4)>; + width = <1440>; + height = <3120>; + stride = <(1440 * 4)>; + format = "a8r8g8b8"; + lab-supply = <&lab>; + ibb-supply = <&ibb>; + }; + }; + + /* Additional ThinQ key */ + gpio-keys { + pinctrl-0 = <&vol_up_pin_a &thinq_key_default>; + + key-thinq { + label = "ThinQ"; + linux,code = <KEY_ASSISTANT>; + interrupt-parent = <&tlmm>; + interrupts = <89 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&adsp_pas { + firmware-name = "qcom/sdm845/judyln/adsp.mbn"; +}; + +&cdsp_pas { + firmware-name = "qcom/sdm845/judyln/cdsp.mbn"; +}; + +&gpu { + zap-shader { + firmware-name = "qcom/sdm845/judyln/a630_zap.mbn"; + }; +}; + +&mss_pil { + firmware-name = "qcom/sdm845/judyln/mba.mbn", "qcom/sdm845/judyln/modem.mbn"; +}; + +&tlmm { + thinq_key_default: thinq-key-default { + pins = "gpio89"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts b/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts new file mode 100644 index 000000000000..d17d4d4d5609 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM845 LG V35 (judyp) device tree. + * + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include "sdm845-lg-common.dtsi" + +/ { + model = "LG V35 ThinQ"; + compatible = "lg,judyp", "qcom,sdm845"; + + chosen { + framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9d400000 0x0 (1440 * 2880 * 4)>; + width = <1440>; + height = <2880>; + stride = <(1440 * 4)>; + format = "a8r8g8b8"; + }; + }; +}; + +&adsp_pas { + firmware-name = "qcom/sdm845/judyp/adsp.mbn"; +}; + +&cdsp_pas { + firmware-name = "qcom/sdm845/judyp/cdsp.mbn"; +}; + +&gpu { + zap-shader { + firmware-name = "qcom/sdm845/judyp/a630_zap.mbn"; + }; +}; + +&mss_pil { + firmware-name = "qcom/sdm845/judyp/mba.mbn", "qcom/sdm845/judyp/modem.mbn"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 07b729f9fec5..392461c29e76 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -34,14 +34,14 @@ pinctrl-names = "default"; pinctrl-0 = <&volume_down_gpio &volume_up_gpio>; - vol-down { + key-vol-down { label = "Volume down"; linux,code = <KEY_VOLUMEDOWN>; gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; debounce-interval = <15>; }; - vol-up { + key-vol-up { label = "Volume up"; linux,code = <KEY_VOLUMEUP>; gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; @@ -440,7 +440,7 @@ }; &pm8998_gpio { - volume_down_gpio: pm8998_gpio5 { + volume_down_gpio: pm8998-gpio5-state { pinconf { pins = "gpio5"; function = "normal"; @@ -450,7 +450,7 @@ }; }; - volume_up_gpio: pm8998_gpio6 { + volume_up_gpio: pm8998-gpio6-state { pinconf { pins = "gpio6"; function = "normal"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 103cc40816fd..83261c9bb4f2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -2,11 +2,13 @@ /* * Copyright (c) 2022, Alexander Martinz <amartinz@shiftphones.com> * Copyright (c) 2022, Caleb Connolly <caleb@connolly.tech> + * Copyright (c) 2022, Dylan Van Assche <me@dylanvanassche.be> */ /dts-v1/; #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sdm845.dtsi" #include "pm8998.dtsi" @@ -48,7 +50,7 @@ pinctrl-names = "default"; pinctrl-0 = <&volume_up_gpio>; - vol-up { + key-vol-up { label = "volume_up"; linux,code = <KEY_VOLUMEUP>; gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; @@ -468,7 +470,7 @@ }; &i2c5 { - status="okay"; + status = "okay"; touchscreen@38 { compatible = "focaltech,fts8719"; @@ -508,7 +510,7 @@ }; &pm8998_gpio { - volume_up_gpio: pm8998_gpio6 { + volume_up_gpio: pm8998-gpio6-state { pinconf { pins = "gpio6"; function = "normal"; @@ -529,6 +531,33 @@ }; }; +&pmi8998_lpg { + status = "okay"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_BLUE>; + }; + + led@4 { + reg = <4>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@5 { + reg = <5>; + color = <LED_COLOR_ID_RED>; + }; + }; +}; + &qup_uart9_default { pinconf-rx { pins = "gpio5"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts index 8a0d94e7f598..2f5e12deaada 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts @@ -19,8 +19,9 @@ }; &vreg_l22a_2p8 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; + /* Note: Round-down from 2700000 to be a multiple of PLDO step-size 8000 */ + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <2696000>; }; &vreg_l28a_2p8 { diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 281fe6dea62a..51ee42e3c995 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -19,7 +19,7 @@ /* Neither Camera Focus, nor Camera Shutter seem to work... */ - vol-down { + key-vol-down { label = "volume_down"; gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index d88dc07205f7..82c27f90d300 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -45,7 +45,7 @@ pinctrl-names = "default"; pinctrl-0 = <&vol_up_pin_a>; - vol-up { + key-vol-up { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; @@ -306,7 +306,7 @@ }; &pm8998_gpio { - vol_up_pin_a: vol-up-active { + vol_up_pin_a: vol-up-active-state { pins = "gpio6"; function = "normal"; input-enable; @@ -339,7 +339,7 @@ /* QUAT I2S Uses 1 I2S SD Line for audio on TAS2559/60 amplifiers */ &q6afedai { qi2s@22 { - reg = <22>; + reg = <QUATERNARY_MI2S_RX>; qcom,sd-lines = <0>; }; }; @@ -419,7 +419,7 @@ }; codec { - sound-dai = <&wcd9340 0>; + sound-dai = <&wcd9340 0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0692ae0e60a4..7fb10c2ef2fb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -188,7 +188,7 @@ }; }; - cpus { + cpus: cpus { #address-cells = <2>; #size-cells = <0>; @@ -197,15 +197,14 @@ compatible = "qcom,kryo385"; reg = <0x0 0x0>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <290>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&L2_0>; L2_0: l2-cache { @@ -222,15 +221,14 @@ compatible = "qcom,kryo385"; reg = <0x0 0x100>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <290>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&L2_100>; L2_100: l2-cache { @@ -244,15 +242,14 @@ compatible = "qcom,kryo385"; reg = <0x0 0x200>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <290>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&L2_200>; L2_200: l2-cache { @@ -266,9 +263,6 @@ compatible = "qcom,kryo385"; reg = <0x0 0x300>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <290>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -276,6 +270,8 @@ interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; next-level-cache = <&L2_300>; L2_300: l2-cache { compatible = "cache"; @@ -289,14 +285,13 @@ reg = <0x0 0x400>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&L2_400>; L2_400: l2-cache { @@ -311,14 +306,13 @@ reg = <0x0 0x500>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&L2_500>; L2_500: l2-cache { @@ -333,14 +327,13 @@ reg = <0x0 0x600>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&L2_600>; L2_600: l2-cache { @@ -355,14 +348,13 @@ reg = <0x0 0x700>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&L2_700>; L2_700: l2-cache { @@ -407,53 +399,35 @@ }; }; - idle-states { + cpu_idle_states: idle-states { entry-method = "psci"; LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { compatible = "arm,idle-state"; - idle-state-name = "little-power-down"; - arm,psci-suspend-param = <0x40000003>; + idle-state-name = "little-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; entry-latency-us = <350>; exit-latency-us = <461>; min-residency-us = <1890>; local-timer-stop; }; - LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { - compatible = "arm,idle-state"; - idle-state-name = "little-rail-power-down"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <360>; - exit-latency-us = <531>; - min-residency-us = <3934>; - local-timer-stop; - }; - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { compatible = "arm,idle-state"; - idle-state-name = "big-power-down"; - arm,psci-suspend-param = <0x40000003>; + idle-state-name = "big-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; entry-latency-us = <264>; exit-latency-us = <621>; min-residency-us = <952>; local-timer-stop; }; + }; - BIG_CPU_SLEEP_1: cpu-sleep-1-1 { - compatible = "arm,idle-state"; - idle-state-name = "big-rail-power-down"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <702>; - exit-latency-us = <1061>; - min-residency-us = <4488>; - local-timer-stop; - }; - + domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "cluster-power-down"; - arm,psci-suspend-param = <0x400000F4>; + compatible = "domain-idle-state"; + idle-state-name = "cluster-power-collapse"; + arm,psci-suspend-param = <0x4100c244>; entry-latency-us = <3263>; exit-latency-us = <6562>; min-residency-us = <9987>; @@ -462,7 +436,7 @@ }; }; - cpu0_opp_table: cpu0_opp_table { + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; @@ -557,7 +531,7 @@ }; }; - cpu4_opp_table: cpu4_opp_table { + cpu4_opp_table: opp-table-cpu4 { compatible = "operating-points-v2"; opp-shared; @@ -1050,9 +1024,62 @@ }; }; - psci { + psci: psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; }; soc: soc@0 { @@ -1104,7 +1131,7 @@ clock-names = "core"; }; - qup_opp_table: qup-opp-table { + qup_opp_table: opp-table-qup { compatible = "operating-points-v2"; opp-50000000 { @@ -2026,6 +2053,43 @@ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; + pmu@1436400 { + compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon"; + reg = <0 0x01436400 0 0x600>; + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* + * The interconnect path bandwidth taken from + * cpu4_opp_table bandwidth for OSM L3 + * interconnect. This also matches the OSM L3 + * from bandwidth table of qcom,cpu4-l3lat-mon + * (qcom,core-dev-table, bus width: 16 bytes) + * from msm-4.9 downstream kernel. + */ + opp-0 { + opp-peak-kBps = <4800000>; + }; + opp-1 { + opp-peak-kBps = <9216000>; + }; + opp-2 { + opp-peak-kBps = <15052800>; + }; + opp-3 { + opp-peak-kBps = <20889600>; + }; + opp-4 { + opp-peak-kBps = <25497600>; + }; + }; + }; + pcie0: pci@1c00000 { compatible = "qcom,pcie-sdm845"; reg = <0 0x01c00000 0 0x2000>, @@ -3551,7 +3615,7 @@ }; }; - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -3569,7 +3633,7 @@ status = "disabled"; - sdhc2_opp_table: sdhc2-opp-table { + sdhc2_opp_table: opp-table { compatible = "operating-points-v2"; opp-9600000 { @@ -3594,7 +3658,7 @@ }; }; - qspi_opp_table: qspi-opp-table { + qspi_opp_table: opp-table-qspi { compatible = "operating-points-v2"; opp-19200000 { @@ -3640,7 +3704,7 @@ qcom,apps-ch-pipes = <0x780000>; qcom,ea-pc = <0x270>; status = "okay"; - dmas = <&slimbam 3>, <&slimbam 4>, + dmas = <&slimbam 3>, <&slimbam 4>, <&slimbam 5>, <&slimbam 6>; dma-names = "rx", "tx", "tx2", "rx2"; @@ -3655,13 +3719,13 @@ wcd9340_ifd: ifd@0{ compatible = "slim217,250"; - reg = <0 0>; + reg = <0 0>; }; wcd9340: codec@1{ compatible = "slim217,250"; - reg = <1 0>; - slim-ifc-dev = <&wcd9340_ifd>; + reg = <1 0>; + slim-ifc-dev = <&wcd9340_ifd>; #sound-dai-cells = <1>; @@ -3692,8 +3756,8 @@ reg = <0xc85 0x40>; interrupts-extended = <&wcd9340 20>; - qcom,dout-ports = <6>; - qcom,din-ports = <2>; + qcom,dout-ports = <6>; + qcom,din-ports = <2>; qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; @@ -3971,7 +4035,7 @@ compatible = "venus-encoder"; }; - venus_opp_table: venus-opp-table { + venus_opp_table: opp-table { compatible = "operating-points-v2"; opp-100000000 { @@ -4208,7 +4272,7 @@ clock-names = "bi_tcxo"; }; - dsi_opp_table: dsi-opp-table { + dsi_opp_table: opp-table-dsi { compatible = "operating-points-v2"; opp-19200000 { @@ -4244,13 +4308,10 @@ power-domains = <&dispcc MDSS_GDSC>; - clocks = <&gcc GCC_DISP_AHB_CLK>, + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "core"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; @@ -4281,10 +4342,8 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <300000000>, - <19200000>; + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SDM845_CX>; @@ -4310,7 +4369,7 @@ }; }; - mdp_opp_table: mdp-opp-table { + mdp_opp_table: opp-table { compatible = "operating-points-v2"; opp-19200000 { @@ -4574,7 +4633,7 @@ }; gmu: gmu@506a000 { - compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; + compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; reg = <0 0x506a000 0 0x30000>, <0 0xb280000 0 0x10000>, @@ -4721,8 +4780,8 @@ cell-index = <0>; }; - imem@146bf000 { - compatible = "simple-mfd"; + sram@146bf000 { + compatible = "qcom,sdm845-imem", "syscon", "simple-mfd"; reg = <0 0x146bf000 0 0x1000>; #address-cells = <1>; @@ -4939,7 +4998,7 @@ compatible = "qcom,bam-v1.7.0"; qcom,controlled-remotely; reg = <0 0x17184000 0 0x2a000>; - num-channels = <31>; + num-channels = <31>; interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; qcom,ee = <1>; @@ -4948,9 +5007,9 @@ }; timer@17c90000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; compatible = "arm,armv7-timer-mem"; reg = <0 0x17c90000 0 0x1000>; @@ -4958,49 +5017,49 @@ frame-number = <0>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17ca0000 0 0x1000>, - <0 0x17cb0000 0 0x1000>; + reg = <0x17ca0000 0x1000>, + <0x17cb0000 0x1000>; }; frame@17cc0000 { frame-number = <1>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17cc0000 0 0x1000>; + reg = <0x17cc0000 0x1000>; status = "disabled"; }; frame@17cd0000 { frame-number = <2>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17cd0000 0 0x1000>; + reg = <0x17cd0000 0x1000>; status = "disabled"; }; frame@17ce0000 { frame-number = <3>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17ce0000 0 0x1000>; + reg = <0x17ce0000 0x1000>; status = "disabled"; }; frame@17cf0000 { frame-number = <4>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17cf0000 0 0x1000>; + reg = <0x17cf0000 0x1000>; status = "disabled"; }; frame@17d00000 { frame-number = <5>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17d00000 0 0x1000>; + reg = <0x17d00000 0x1000>; status = "disabled"; }; frame@17d10000 { frame-number = <6>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17d10000 0 0x1000>; + reg = <0x17d10000 0x1000>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index f1619b3f97ef..a7af1bed4312 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -41,7 +41,7 @@ pinctrl-names = "default"; pinctrl-0 = <&lid_pin_active>, <&mode_pin_active>; - lid { + switch-lid { gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>; linux,input-type = <EV_SW>; linux,code = <SW_LID>; @@ -49,7 +49,7 @@ wakeup-event-action = <EV_ACT_DEASSERTED>; }; - mode { + switch-mode { gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; linux,input-type = <EV_SW>; linux,code = <SW_TABLET_MODE>; @@ -581,7 +581,7 @@ }; codec { - sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; + sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; }; }; @@ -611,7 +611,7 @@ }; codec { - sound-dai = <&wcd9340 2>; + sound-dai = <&wcd9340 2>; }; }; }; @@ -817,5 +817,5 @@ &crypto { /* FIXME: qce_start triggers an SError */ - status= "disable"; + status = "disable"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts index 2a552d817b03..b0315eeb1320 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -509,7 +509,7 @@ }; codec { - sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; + sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; }; }; @@ -539,7 +539,7 @@ }; codec { - sound-dai = <&wcd9340 2>; + sound-dai = <&wcd9340 2>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index 871ccbba445b..0aad2e94e757 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -42,11 +42,9 @@ gpio-keys { status = "okay"; compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - vol-dn { + key-vol-dn { label = "Volume Down"; gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -88,11 +86,19 @@ status = "okay"; }; -&sdc2_state_off { +&sdc2_off_state { sd-cd { pins = "gpio98"; + drive-strength = <2>; bias-disable; + }; +}; + +&sdc2_on_state { + sd-cd { + pins = "gpio98"; drive-strength = <2>; + bias-pull-up; }; }; @@ -102,32 +108,6 @@ &tlmm { gpio-reserved-ranges = <22 2>, <28 6>; - - sdc2_state_on: sdc2-on { - clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <16>; - }; - - cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - - sd-cd { - pins = "gpio98"; - bias-pull-up; - drive-strength = <2>; - }; - }; }; &usb3 { diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 135e6e0da27a..8c582a9e4ada 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -386,23 +386,43 @@ interrupt-controller; #interrupt-cells = <2>; - sdc2_state_off: sdc2-off { + sdc2_off_state: sdc2-off-state { clk { pins = "sdc2_clk"; - bias-disable; drive-strength = <2>; + bias-disable; }; cmd { pins = "sdc2_cmd"; + drive-strength = <2>; bias-pull-up; + }; + + data { + pins = "sdc2_data"; drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_on_state: sdc2-on-state { + clk { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd { + pins = "sdc2_cmd"; + drive-strength = <10>; + bias-pull-up; }; data { pins = "sdc2_data"; + drive-strength = <10>; bias-pull-up; - drive-strength = <2>; }; }; }; @@ -435,7 +455,7 @@ reg = <0x045f0000 0x7000>; }; - sdhc_1: sdhci@4744000 { + sdhc_1: mmc@4744000 { compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; reg = <0x04744000 0x1000>, <0x04745000 0x1000>; reg-names = "hc", "core"; @@ -451,12 +471,15 @@ power-domains = <&rpmpd SM6125_VDDCX>; + qcom,dll-config = <0x000f642c>; + qcom,ddr-config = <0x80040873>; + bus-width = <8>; non-removable; status = "disabled"; }; - sdhc_2: sdhci@4784000 { + sdhc_2: mmc@4784000 { compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; reg = <0x04784000 0x1000>; reg-names = "hc"; @@ -470,12 +493,15 @@ <&xo_board>; clock-names = "iface", "core", "xo"; - pinctrl-0 = <&sdc2_state_on>; - pinctrl-1 = <&sdc2_state_off>; + pinctrl-0 = <&sdc2_on_state>; + pinctrl-1 = <&sdc2_off_state>; pinctrl-names = "default", "sleep"; power-domains = <&rpmpd SM6125_VDDCX>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040873>; + bus-width = <4>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index d4f8f33f3f0c..bb9349bc2d35 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -472,7 +472,7 @@ clock-names = "core"; }; - sdhc_1: sdhci@7c4000 { + sdhc_1: mmc@7c4000 { compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x007c4000 0 0x1000>, <0 0x007c5000 0 0x1000>, @@ -497,7 +497,7 @@ status = "disabled"; - sdhc1_opp_table: sdhc1-opp-table { + sdhc1_opp_table: opp-table { compatible = "operating-points-v2"; opp-19200000 { @@ -921,7 +921,7 @@ }; }; - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -941,7 +941,7 @@ status = "disabled"; - sdhc2_opp_table: sdhc2-opp-table { + sdhc2_opp_table: opp-table { compatible = "operating-points-v2"; opp-100000000 { @@ -1304,57 +1304,57 @@ compatible = "arm,armv7-timer-mem"; reg = <0x0 0x17c20000 0x0 0x1000>; clock-frequency = <19200000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; frame@17c21000 { frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c21000 0x0 0x1000>, - <0x0 0x17c22000 0x0 0x1000>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; }; frame@17c23000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c23000 0x0 0x1000>; + reg = <0x17c23000 0x1000>; status = "disabled"; }; frame@17c25000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c25000 0x0 0x1000>; + reg = <0x17c25000 0x1000>; status = "disabled"; }; frame@17c27000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c27000 0x0 0x1000>; + reg = <0x17c27000 0x1000>; status = "disabled"; }; frame@17c29000 { frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c29000 0x0 0x1000>; + reg = <0x17c29000 0x1000>; status = "disabled"; }; frame@17c2b000 { frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c2b000 0x0 0x1000>; + reg = <0x17c2b000 0x1000>; status = "disabled"; }; frame@17c2d000 { frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c2d000 0x0 0x1000>; + reg = <0x17c2d000 0x1000>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 61925216f5e3..c76abe7587b4 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -48,7 +48,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin>; - volume-up { + key-volume-up { label = "volume_up"; linux,code = <KEY_VOLUMEUP>; gpios = <&pm6350_gpios 2 GPIO_ACTIVE_LOW>; @@ -339,7 +339,7 @@ }; &pm6350_gpios { - gpio_keys_pin: gpio-keys-pin { + gpio_keys_pin: gpio-keys-state { pins = "gpio2"; function = PMIC_GPIO_FUNC_NORMAL; bias-pull-up; diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index 37ddca0f0223..3331ee957d64 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -44,10 +44,10 @@ vin-supply = <&vph_pwr>; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - vol-up { + key-vol-up { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts index a73317e1a824..bb278ecac3fa 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts @@ -49,10 +49,10 @@ vin-supply = <&vph_pwr>; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - vol_up { + key-vol-up { label = "Volume Up"; gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 8ea44c4b56b4..7d509ecd44da 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -288,7 +288,7 @@ }; }; - cpu0_opp_table: cpu0_opp_table { + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; @@ -383,7 +383,7 @@ }; }; - cpu4_opp_table: cpu4_opp_table { + cpu4_opp_table: opp-table-cpu4 { compatible = "operating-points-v2"; opp-shared; @@ -473,7 +473,7 @@ }; }; - cpu7_opp_table: cpu7_opp_table { + cpu7_opp_table: opp-table-cpu7 { compatible = "operating-points-v2"; opp-shared; @@ -2187,7 +2187,7 @@ }; gmu: gmu@2c6a000 { - compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; + compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; reg = <0 0x02c6a000 0 0x30000>, <0 0x0b290000 0 0x10000>, @@ -3543,7 +3543,7 @@ }; }; - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -3563,7 +3563,7 @@ status = "disabled"; - sdhc2_opp_table: sdhc2-opp-table { + sdhc2_opp_table: opp-table { compatible = "operating-points-v2"; opp-19200000 { @@ -3718,7 +3718,7 @@ }; aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8150-aoss-qmp"; + compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x400>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; mboxes = <&apss_shared 0>; @@ -3944,9 +3944,9 @@ }; timer@17c20000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; compatible = "arm,armv7-timer-mem"; reg = <0x0 0x17c20000 0x0 0x1000>; clock-frequency = <19200000>; @@ -3955,49 +3955,49 @@ frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c21000 0x0 0x1000>, - <0x0 0x17c22000 0x0 0x1000>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; }; frame@17c23000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c23000 0x0 0x1000>; + reg = <0x17c23000 0x1000>; status = "disabled"; }; frame@17c25000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c25000 0x0 0x1000>; + reg = <0x17c25000 0x1000>; status = "disabled"; }; frame@17c27000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c26000 0x0 0x1000>; + reg = <0x17c26000 0x1000>; status = "disabled"; }; frame@17c29000 { frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c29000 0x0 0x1000>; + reg = <0x17c29000 0x1000>; status = "disabled"; }; frame@17c2b000 { frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c2b000 0x0 0x1000>; + reg = <0x17c2b000 0x1000>; status = "disabled"; }; frame@17c2d000 { frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c2d000 0x0 0x1000>; + reg = <0x17c2d000 0x1000>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts index 3b082472062b..632e98193d27 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts @@ -53,10 +53,10 @@ vin-supply = <&vph_pwr>; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - vol-up { + key-vol-up { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index e819b5b77363..549e0a2aa9fe 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -57,7 +57,7 @@ * case, they are both on &pm8150b_gpios: camera focus(2), camera snapshot(1). */ - vol-down { + key-vol-down { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index cf0c97bd5ad3..92fb49beda15 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -8,6 +8,8 @@ #include <dt-bindings/clock/qcom,gcc-sm8250.h> #include <dt-bindings/clock/qcom,gpucc-sm8250.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h> +#include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> @@ -336,7 +338,7 @@ }; }; - cpu0_opp_table: cpu0_opp_table { + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; @@ -426,7 +428,7 @@ }; }; - cpu4_opp_table: cpu4_opp_table { + cpu4_opp_table: opp-table-cpu4 { compatible = "operating-points-v2"; opp-shared; @@ -521,7 +523,7 @@ }; }; - cpu7_opp_table: cpu7_opp_table { + cpu7_opp_table: opp-table-cpu7 { compatible = "operating-points-v2"; opp-shared; @@ -628,7 +630,7 @@ firmware { scm: scm { - compatible = "qcom,scm"; + compatible = "qcom,scm-sm8250", "qcom,scm"; #reset-cells = <1>; }; }; @@ -702,6 +704,25 @@ }; }; + qup_opp_table: opp-table-qup { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -914,25 +935,6 @@ clock-names = "core"; }; - qup_opp_table: qup-opp-table { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-120000000 { - opp-hz = /bits/ 64 <120000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - }; - gpi_dma2: dma-controller@800000 { compatible = "qcom,sm8250-gpi-dma"; reg = <0 0x00800000 0 0x70000>; @@ -1884,6 +1886,8 @@ clock-names = "pipe0"; #phy-cells = <0>; + + #clock-cells = <0>; clock-output-names = "pcie_0_pipe_clk"; }; }; @@ -1990,6 +1994,8 @@ clock-names = "pipe0"; #phy-cells = <0>; + + #clock-cells = <0>; clock-output-names = "pcie_1_pipe_clk"; }; }; @@ -2096,6 +2102,8 @@ clock-names = "pipe0"; #phy-cells = <0>; + + #clock-cells = <0>; clock-output-names = "pcie_2_pipe_clk"; }; }; @@ -2188,11 +2196,11 @@ wsamacro: codec@3240000 { compatible = "qcom,sm8250-lpass-wsa-macro"; reg = <0 0x03240000 0 0x1000>; - clocks = <&audiocc 1>, - <&audiocc 0>, + clocks = <&audiocc LPASS_CDC_WSA_MCLK>, + <&audiocc LPASS_CDC_WSA_NPL>, <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&aoncc 0>, + <&aoncc LPASS_CDC_VA_MCLK>, <&vamacro>; clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; @@ -2239,7 +2247,7 @@ vamacro: codec@3370000 { compatible = "qcom,sm8250-lpass-va-macro"; reg = <0 0x03370000 0 0x1000>; - clocks = <&aoncc 0>, + clocks = <&aoncc LPASS_CDC_VA_MCLK>, <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; @@ -2569,7 +2577,7 @@ }; gmu: gmu@3d6a000 { - compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; + compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; reg = <0 0x03d6a000 0 0x30000>, <0 0x3de0000 0 0x10000>, @@ -2623,7 +2631,7 @@ }; adreno_smmu: iommu@3da0000 { - compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; + compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; reg = <0 0x03da0000 0 0x10000>; #iommu-cells = <2>; #global-interrupts = <2>; @@ -2917,7 +2925,7 @@ }; }; - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -2937,7 +2945,7 @@ status = "disabled"; - sdhc2_opp_table: sdhc2-opp-table { + sdhc2_opp_table: opp-table { compatible = "operating-points-v2"; opp-19200000 { @@ -3123,7 +3131,7 @@ compatible = "venus-encoder"; }; - venus_opp_table: venus-opp-table { + venus_opp_table: opp-table { compatible = "operating-points-v2"; opp-720000000 { @@ -3407,6 +3415,7 @@ clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; power-domains = <&rpmhpd SM8250_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; + status = "disabled"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -3429,9 +3438,6 @@ <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "bus", "nrt_bus", "core"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <460000000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; @@ -3456,10 +3462,8 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "iface", "bus", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <460000000>, - <19200000>; + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SM8250_MMCX>; @@ -3486,7 +3490,7 @@ }; }; - mdp_opp_table: mdp-opp-table { + mdp_opp_table: opp-table { compatible = "operating-points-v2"; opp-200000000 { @@ -3656,7 +3660,7 @@ status = "disabled"; - dsi_opp_table: dsi-opp-table { + dsi_opp_table: opp-table { compatible = "operating-points-v2"; opp-187500000 { @@ -3734,7 +3738,7 @@ }; aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8250-aoss-qmp"; + compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP @@ -4867,9 +4871,9 @@ }; timer@17c20000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; compatible = "arm,armv7-timer-mem"; reg = <0x0 0x17c20000 0x0 0x1000>; clock-frequency = <19200000>; @@ -4878,49 +4882,49 @@ frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c21000 0x0 0x1000>, - <0x0 0x17c22000 0x0 0x1000>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; }; frame@17c23000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c23000 0x0 0x1000>; + reg = <0x17c23000 0x1000>; status = "disabled"; }; frame@17c25000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c25000 0x0 0x1000>; + reg = <0x17c25000 0x1000>; status = "disabled"; }; frame@17c27000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c27000 0x0 0x1000>; + reg = <0x17c27000 0x1000>; status = "disabled"; }; frame@17c29000 { frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c29000 0x0 0x1000>; + reg = <0x17c29000 0x1000>; status = "disabled"; }; frame@17c2b000 { frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c2b000 0x0 0x1000>; + reg = <0x17c2b000 0x1000>; status = "disabled"; }; frame@17c2d000 { frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c2d000 0x0 0x1000>; + reg = <0x17c2d000 0x1000>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts index 9a6faa9393dc..9c4cfd995ff2 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts @@ -336,9 +336,7 @@ status = "okay"; vdda-phy-supply = <&vreg_l5b_0p88>; - vdda-max-microamp = <91600>; vdda-pll-supply = <&vreg_l6b_1p2>; - vdda-pll-max-microamp = <19000>; }; &usb_1 { diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index 90b13cbe2fa6..cb9bbd234b7b 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -49,7 +49,7 @@ /* For reasons still unknown, GAssist key and Camera Focus/Shutter don't work.. */ - vol-down { + key-vol-down { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; gpios = <&pmk8350_gpios 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 743cba9b683c..65c7fe54613d 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,dispcc-sm8350.h> #include <dt-bindings/clock/qcom,gcc-sm8350.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/dma/qcom-gpi.h> @@ -341,6 +342,44 @@ }; }; + qup_opp_table_100mhz: opp-table-qup100mhz { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + + qup_opp_table_120mhz: opp-table-qup120mhz { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -638,44 +677,6 @@ #mbox-cells = <2>; }; - qup_opp_table_100mhz: qup-100mhz-opp-table { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - }; - - qup_opp_table_120mhz: qup-120mhz-opp-table { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-120000000 { - opp-hz = /bits/ 64 <120000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - }; - gpi_dma2: dma-controller@800000 { compatible = "qcom,sm8350-gpi-dma"; reg = <0 0x00800000 0 0x60000>; @@ -1656,8 +1657,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd 0>, - <&rpmhpd 12>; + power-domains = <&rpmhpd SM8350_CX>, + <&rpmhpd SM8350_MSS>; power-domain-names = "cx", "mss"; interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; @@ -1677,7 +1678,6 @@ IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_GLINK_QMP>; - interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; label = "modem"; qcom,remote-pid = <1>; }; @@ -1718,7 +1718,7 @@ }; aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8350-aoss-qmp"; + compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; @@ -1933,9 +1933,9 @@ timer@17c20000 { compatible = "arm,armv7-timer-mem"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; reg = <0x0 0x17c20000 0x0 0x1000>; clock-frequency = <19200000>; @@ -1943,49 +1943,49 @@ frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c21000 0x0 0x1000>, - <0x0 0x17c22000 0x0 0x1000>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; }; frame@17c23000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c23000 0x0 0x1000>; + reg = <0x17c23000 0x1000>; status = "disabled"; }; frame@17c25000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c25000 0x0 0x1000>; + reg = <0x17c25000 0x1000>; status = "disabled"; }; frame@17c27000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c27000 0x0 0x1000>; + reg = <0x17c27000 0x1000>; status = "disabled"; }; frame@17c29000 { frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c29000 0x0 0x1000>; + reg = <0x17c29000 0x1000>; status = "disabled"; }; frame@17c2b000 { frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c2b000 0x0 0x1000>; + reg = <0x17c2b000 0x1000>; status = "disabled"; }; frame@17c2d000 { frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c2d000 0x0 0x1000>; + reg = <0x17c2d000 0x1000>; status = "disabled"; }; }; @@ -2148,7 +2148,6 @@ <0 0x01d87800 0 0x108>, <0 0x01d87a00 0 0x1e0>; #phy-cells = <0>; - #clock-cells = <0>; }; }; @@ -2167,8 +2166,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd 4>, - <&rpmhpd 5>; + power-domains = <&rpmhpd SM8350_LCX>, + <&rpmhpd SM8350_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&pil_slpi_mem>; @@ -2235,8 +2234,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd 0>, - <&rpmhpd 10>; + power-domains = <&rpmhpd SM8350_CX>, + <&rpmhpd SM8350_MXC>; power-domain-names = "cx", "mxc"; interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; @@ -2381,7 +2380,7 @@ <0 0x088e9800 0 0x200>, <0 0x088e9a00 0 0x100>; #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "usb3_phy_pipe_clk_src"; @@ -2411,7 +2410,7 @@ <0 0x088ec000 0 0x200>, <0 0x088eb200 0 0x1100>; #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "usb3_uni_phy_pipe_clk_src"; @@ -2532,6 +2531,31 @@ }; }; + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8350-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + power-domains = <&rpmhpd SM8350_MMCX>; + power-domain-names = "mmcx"; + }; + adsp: remoteproc@17300000 { compatible = "qcom,sm8350-adsp-pas"; reg = <0 0x17300000 0 0x100>; @@ -2547,8 +2571,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd 4>, - <&rpmhpd 5>; + power-domains = <&rpmhpd SM8350_LCX>, + <&rpmhpd SM8350_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&pil_adsp_mem>; diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 4e51a9d6af98..38ccd44620d0 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -418,8 +418,6 @@ vdda-phy-supply = <&vreg_l5b_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; - vdda-max-microamp = <173000>; - vdda-pll-max-microamp = <24900>; }; &usb_1 { diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 236e53974fdd..e58fc7399799 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -424,8 +424,6 @@ vdda-phy-supply = <&vreg_l5b_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; - vdda-max-microamp = <173000>; - vdda-pll-max-microamp = <24900>; }; &usb_1 { diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 7d08fad76371..4978c5ba5dd0 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-sm8450.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sm8450-camcc.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/mailbox/qcom-ipcc.h> @@ -258,17 +259,18 @@ firmware { scm: scm { compatible = "qcom,scm-sm8450", "qcom,scm"; + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; #reset-cells = <1>; }; }; - clk_virt: interconnect@0 { + clk_virt: interconnect-0 { compatible = "qcom,sm8450-clk-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; - mc_virt: interconnect@1 { + mc_virt: interconnect-1 { compatible = "qcom,sm8450-mc-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -343,7 +345,7 @@ }; }; - qup_opp_table_100mhz: qup-100mhz-opp-table { + qup_opp_table_100mhz: opp-table-qup { compatible = "operating-points-v2"; opp-50000000 { @@ -976,6 +978,19 @@ status = "disabled"; }; + uart20: serial@894000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart20_default>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spi20: spi@894000 { compatible = "qcom,geni-spi"; reg = <0 0x00894000 0 0x4000>; @@ -2001,7 +2016,7 @@ <0 0x088e9800 0 0x200>, <0 0x088e9a00 0 0x100>; #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "usb3_phy_pipe_clk_src"; @@ -2012,7 +2027,7 @@ compatible = "qcom,sm8450-slpi-pas"; reg = <0 0x02400000 0 0x4000>; - interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, @@ -2079,7 +2094,7 @@ compatible = "qcom,sm8450-adsp-pas"; reg = <0 0x030000000 0 0x100>; - interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, @@ -2145,7 +2160,7 @@ compatible = "qcom,sm8450-cdsp-pas"; reg = <0 0x032300000 0 0x1400000>; - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, @@ -2251,7 +2266,7 @@ compatible = "qcom,sm8450-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>; - interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, @@ -2282,12 +2297,26 @@ IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_GLINK_QMP>; - interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; label = "modem"; qcom,remote-pid = <1>; }; }; + camcc: clock-controller@ade0000 { + compatible = "qcom,sm8450-camcc"; + reg = <0 0x0ade0000 0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd SM8450_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + status = "disabled"; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8450-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; @@ -2738,6 +2767,12 @@ drive-strength = <2>; bias-disable; }; + + qup_uart20_default: qup-uart20-default { + pins = "gpio76", "gpio77", "gpio78", "gpio79"; + function = "qup20"; + }; + }; apps_smmu: iommu@15000000 { @@ -2853,13 +2888,23 @@ reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic_its: msi-controller@17140000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x17140000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; }; timer@17420000 { compatible = "arm,armv7-timer-mem"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; reg = <0x0 0x17420000 0x0 0x1000>; clock-frequency = <19200000>; @@ -2867,49 +2912,49 @@ frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17421000 0x0 0x1000>, - <0x0 0x17422000 0x0 0x1000>; + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; }; frame@17423000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17423000 0x0 0x1000>; + reg = <0x17423000 0x1000>; status = "disabled"; }; frame@17425000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17425000 0x0 0x1000>; + reg = <0x17425000 0x1000>; status = "disabled"; }; frame@17427000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17427000 0x0 0x1000>; + reg = <0x17427000 0x1000>; status = "disabled"; }; frame@17429000 { frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17429000 0x0 0x1000>; + reg = <0x17429000 0x1000>; status = "disabled"; }; frame@1742b000 { frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x1742b000 0x0 0x1000>; + reg = <0x1742b000 0x1000>; status = "disabled"; }; frame@1742d000 { frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x1742d000 0x0 0x1000>; + reg = <0x1742d000 0x1000>; status = "disabled"; }; }; @@ -3037,8 +3082,8 @@ iommus = <&apps_smmu 0xe0 0x0>; - interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; interconnect-names = "ufs-ddr", "cpu-ufs"; clock-names = "core_clk", @@ -3092,7 +3137,6 @@ <0 0x01d87800 0 0x108>, <0 0x01d87a00 0 0x1e0>; #phy-cells = <0>; - #clock-cells = <0>; }; }; diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h new file mode 120000 index 000000000000..0312b4544acb --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h @@ -0,0 +1 @@ +qcom,dispcc-sm8250.h
\ No newline at end of file diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index 8e2bec1c91bf..55f8322a1e50 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -367,4 +367,7 @@ #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 +#define USB0_GDSC 0 +#define USB1_GDSC 1 + #endif diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8350.h b/include/dt-bindings/clock/qcom,gpucc-sm8350.h new file mode 100644 index 000000000000..2ca857f5bfd2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sm8350.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CX_QDSS_AT_CLK 5 +#define GPU_CC_CX_QDSS_TRIG_CLK 6 +#define GPU_CC_CX_QDSS_TSCTR_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_FREQ_MEASURE_CLK 11 +#define GPU_CC_GMU_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_GX_QDSS_TSCTR_CLK 14 +#define GPU_CC_GX_VSENSE_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21 +#define GPU_CC_MND1X_0_GFX3D_CLK 22 +#define GPU_CC_MND1X_1_GFX3D_CLK 23 +#define GPU_CC_PLL0 24 +#define GPU_CC_PLL1 25 +#define GPU_CC_SLEEP_CLK 26 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 + +/* GPU_CC GDSCRs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm8450-camcc.h b/include/dt-bindings/clock/qcom,sm8450-camcc.h new file mode 100644 index 000000000000..7ff67acf301a --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8450-camcc.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8450_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8450_H + +/* CAM_CC clocks */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_CLK 1 +#define CAM_CC_BPS_CLK_SRC 2 +#define CAM_CC_BPS_FAST_AHB_CLK 3 +#define CAM_CC_CAMNOC_AXI_CLK 4 +#define CAM_CC_CAMNOC_AXI_CLK_SRC 5 +#define CAM_CC_CAMNOC_DCD_XO_CLK 6 +#define CAM_CC_CCI_0_CLK 7 +#define CAM_CC_CCI_0_CLK_SRC 8 +#define CAM_CC_CCI_1_CLK 9 +#define CAM_CC_CCI_1_CLK_SRC 10 +#define CAM_CC_CORE_AHB_CLK 11 +#define CAM_CC_CPAS_AHB_CLK 12 +#define CAM_CC_CPAS_BPS_CLK 13 +#define CAM_CC_CPAS_FAST_AHB_CLK 14 +#define CAM_CC_CPAS_IFE_0_CLK 15 +#define CAM_CC_CPAS_IFE_1_CLK 16 +#define CAM_CC_CPAS_IFE_2_CLK 17 +#define CAM_CC_CPAS_IFE_LITE_CLK 18 +#define CAM_CC_CPAS_IPE_NPS_CLK 19 +#define CAM_CC_CPAS_SBI_CLK 20 +#define CAM_CC_CPAS_SFE_0_CLK 21 +#define CAM_CC_CPAS_SFE_1_CLK 22 +#define CAM_CC_CPHY_RX_CLK_SRC 23 +#define CAM_CC_CSI0PHYTIMER_CLK 24 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 25 +#define CAM_CC_CSI1PHYTIMER_CLK 26 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 27 +#define CAM_CC_CSI2PHYTIMER_CLK 28 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 29 +#define CAM_CC_CSI3PHYTIMER_CLK 30 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 31 +#define CAM_CC_CSI4PHYTIMER_CLK 32 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 33 +#define CAM_CC_CSI5PHYTIMER_CLK 34 +#define CAM_CC_CSI5PHYTIMER_CLK_SRC 35 +#define CAM_CC_CSID_CLK 36 +#define CAM_CC_CSID_CLK_SRC 37 +#define CAM_CC_CSID_CSIPHY_RX_CLK 38 +#define CAM_CC_CSIPHY0_CLK 39 +#define CAM_CC_CSIPHY1_CLK 40 +#define CAM_CC_CSIPHY2_CLK 41 +#define CAM_CC_CSIPHY3_CLK 42 +#define CAM_CC_CSIPHY4_CLK 43 +#define CAM_CC_CSIPHY5_CLK 44 +#define CAM_CC_FAST_AHB_CLK_SRC 45 +#define CAM_CC_GDSC_CLK 46 +#define CAM_CC_ICP_AHB_CLK 47 +#define CAM_CC_ICP_CLK 48 +#define CAM_CC_ICP_CLK_SRC 49 +#define CAM_CC_IFE_0_CLK 50 +#define CAM_CC_IFE_0_CLK_SRC 51 +#define CAM_CC_IFE_0_DSP_CLK 52 +#define CAM_CC_IFE_0_FAST_AHB_CLK 53 +#define CAM_CC_IFE_1_CLK 54 +#define CAM_CC_IFE_1_CLK_SRC 55 +#define CAM_CC_IFE_1_DSP_CLK 56 +#define CAM_CC_IFE_1_FAST_AHB_CLK 57 +#define CAM_CC_IFE_2_CLK 58 +#define CAM_CC_IFE_2_CLK_SRC 59 +#define CAM_CC_IFE_2_DSP_CLK 60 +#define CAM_CC_IFE_2_FAST_AHB_CLK 61 +#define CAM_CC_IFE_LITE_AHB_CLK 62 +#define CAM_CC_IFE_LITE_CLK 63 +#define CAM_CC_IFE_LITE_CLK_SRC 64 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 65 +#define CAM_CC_IFE_LITE_CSID_CLK 66 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 67 +#define CAM_CC_IPE_NPS_AHB_CLK 68 +#define CAM_CC_IPE_NPS_CLK 69 +#define CAM_CC_IPE_NPS_CLK_SRC 70 +#define CAM_CC_IPE_NPS_FAST_AHB_CLK 71 +#define CAM_CC_IPE_PPS_CLK 72 +#define CAM_CC_IPE_PPS_FAST_AHB_CLK 73 +#define CAM_CC_JPEG_CLK 74 +#define CAM_CC_JPEG_CLK_SRC 75 +#define CAM_CC_MCLK0_CLK 76 +#define CAM_CC_MCLK0_CLK_SRC 77 +#define CAM_CC_MCLK1_CLK 78 +#define CAM_CC_MCLK1_CLK_SRC 79 +#define CAM_CC_MCLK2_CLK 80 +#define CAM_CC_MCLK2_CLK_SRC 81 +#define CAM_CC_MCLK3_CLK 82 +#define CAM_CC_MCLK3_CLK_SRC 83 +#define CAM_CC_MCLK4_CLK 84 +#define CAM_CC_MCLK4_CLK_SRC 85 +#define CAM_CC_MCLK5_CLK 86 +#define CAM_CC_MCLK5_CLK_SRC 87 +#define CAM_CC_MCLK6_CLK 88 +#define CAM_CC_MCLK6_CLK_SRC 89 +#define CAM_CC_MCLK7_CLK 90 +#define CAM_CC_MCLK7_CLK_SRC 91 +#define CAM_CC_PLL0 92 +#define CAM_CC_PLL0_OUT_EVEN 93 +#define CAM_CC_PLL0_OUT_ODD 94 +#define CAM_CC_PLL1 95 +#define CAM_CC_PLL1_OUT_EVEN 96 +#define CAM_CC_PLL2 97 +#define CAM_CC_PLL3 98 +#define CAM_CC_PLL3_OUT_EVEN 99 +#define CAM_CC_PLL4 100 +#define CAM_CC_PLL4_OUT_EVEN 101 +#define CAM_CC_PLL5 102 +#define CAM_CC_PLL5_OUT_EVEN 103 +#define CAM_CC_PLL6 104 +#define CAM_CC_PLL6_OUT_EVEN 105 +#define CAM_CC_PLL7 106 +#define CAM_CC_PLL7_OUT_EVEN 107 +#define CAM_CC_PLL8 108 +#define CAM_CC_PLL8_OUT_EVEN 109 +#define CAM_CC_QDSS_DEBUG_CLK 110 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 111 +#define CAM_CC_QDSS_DEBUG_XO_CLK 112 +#define CAM_CC_SBI_AHB_CLK 113 +#define CAM_CC_SBI_CLK 114 +#define CAM_CC_SFE_0_CLK 115 +#define CAM_CC_SFE_0_CLK_SRC 116 +#define CAM_CC_SFE_0_FAST_AHB_CLK 117 +#define CAM_CC_SFE_1_CLK 118 +#define CAM_CC_SFE_1_CLK_SRC 119 +#define CAM_CC_SFE_1_FAST_AHB_CLK 120 +#define CAM_CC_SLEEP_CLK 121 +#define CAM_CC_SLEEP_CLK_SRC 122 +#define CAM_CC_SLOW_AHB_CLK_SRC 123 +#define CAM_CC_XO_CLK_SRC 124 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_ICP_BCR 1 +#define CAM_CC_IFE_0_BCR 2 +#define CAM_CC_IFE_1_BCR 3 +#define CAM_CC_IFE_2_BCR 4 +#define CAM_CC_IPE_0_BCR 5 +#define CAM_CC_QDSS_DEBUG_BCR 6 +#define CAM_CC_SBI_BCR 7 +#define CAM_CC_SFE_0_BCR 8 +#define CAM_CC_SFE_1_BCR 9 + +/* CAM_CC GDSCRs */ +#define BPS_GDSC 0 +#define IPE_0_GDSC 1 +#define SBI_GDSC 2 +#define IFE_0_GDSC 3 +#define IFE_1_GDSC 4 +#define IFE_2_GDSC 5 +#define SFE_0_GDSC 6 +#define SFE_1_GDSC 7 +#define TITAN_TOP_GDSC 8 + +#endif diff --git a/include/dt-bindings/mailbox/qcom-ipcc.h b/include/dt-bindings/mailbox/qcom-ipcc.h index 9296d0bb5f34..fbfa3febc66d 100644 --- a/include/dt-bindings/mailbox/qcom-ipcc.h +++ b/include/dt-bindings/mailbox/qcom-ipcc.h @@ -30,6 +30,7 @@ #define IPCC_CLIENT_PCIE1 14 #define IPCC_CLIENT_PCIE2 15 #define IPCC_CLIENT_SPSS 16 +#define IPCC_CLIENT_NSP1 18 #define IPCC_CLIENT_TME 23 #define IPCC_CLIENT_WPSS 24 |