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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-01-28 11:37:52 +0100 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-02-01 10:33:23 +0100 |
| commit | 6d6c932daef5c5b3cd5e3692e79507d2a3306031 (patch) | |
| tree | f9aaba886511157022396f4e405c5e7301ded89a | |
| parent | drm/i915: Extract can_enable_drrs() (diff) | |
| download | linux-6d6c932daef5c5b3cd5e3692e79507d2a3306031.tar.xz linux-6d6c932daef5c5b3cd5e3692e79507d2a3306031.zip | |
drm/i915: Fix transcoder_has_m2_n2()
M2/N2 values are present for all ilk-ivb,vlv,chv (and hsw edp).
Make the code reflect that.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220128103757.22461-13-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 76c6ccfce56b..319c73d96d96 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3154,11 +3154,7 @@ static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv, if (IS_HASWELL(dev_priv)) return transcoder == TRANSCODER_EDP; - /* - * Strictly speaking some registers are available before - * gen7, but we only support DRRS on gen7+ - */ - return DISPLAY_VER(dev_priv) == 7 || IS_CHERRYVIEW(dev_priv); + return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); } void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, |