diff options
| author | Dinh Nguyen <dinguyen@kernel.org> | 2022-01-07 00:53:31 +0100 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2022-02-09 20:18:48 +0100 |
| commit | 268a491aebc25e6dc7c618903b09ac3a2e8af530 (patch) | |
| tree | 23fc1267882b55a98c6610b1c949b446bf92258a | |
| parent | dt-bindings: usb: dwc2: add compatible "intel,socfpga-agilex-hsotg" (diff) | |
| download | linux-268a491aebc25e6dc7c618903b09ac3a2e8af530.tar.xz linux-268a491aebc25e6dc7c618903b09ac3a2e8af530.zip | |
arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"
The DWC2 USB controller on the Agilex platform does not support clock
gating, so use the chip specific "intel,socfpga-agilex-hsotg"
compatible.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 0dd2d2ee765a..f4270cf18996 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -502,7 +502,7 @@ }; usb0: usb@ffb00000 { - compatible = "snps,dwc2"; + compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; reg = <0xffb00000 0x40000>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; phys = <&usbphy0>; @@ -515,7 +515,7 @@ }; usb1: usb@ffb40000 { - compatible = "snps,dwc2"; + compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; reg = <0xffb40000 0x40000>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; phys = <&usbphy0>; |