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| author | Ravi Bangoria <ravi.bangoria@linux.ibm.com> | 2020-09-02 06:29:39 +0200 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2020-09-15 14:13:18 +0200 |
| commit | 4441eb02333a9b46a0d919aa7a6d3b137b5f2562 (patch) | |
| tree | 2fbf40cc8c367b0ba1b3e0d9afac9c69fca41719 | |
| parent | powerpc/watchpoint: Fix quadword instruction handling on p10 predecessors (diff) | |
| download | linux-4441eb02333a9b46a0d919aa7a6d3b137b5f2562.tar.xz linux-4441eb02333a9b46a0d919aa7a6d3b137b5f2562.zip | |
powerpc/watchpoint: Fix handling of vector instructions
Vector load/store instructions are special because they are always
aligned. Thus unaligned EA needs to be aligned down before comparing
it with watch ranges. Otherwise we might consider valid event as
invalid.
Fixes: 74c6881019b7 ("powerpc/watchpoint: Prepare handler to handle more than one watchpoint")
Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200902042945.129369-3-ravi.bangoria@linux.ibm.com
| -rw-r--r-- | arch/powerpc/kernel/hw_breakpoint.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c index 9f7df1c37233..f6b24838ca3c 100644 --- a/arch/powerpc/kernel/hw_breakpoint.c +++ b/arch/powerpc/kernel/hw_breakpoint.c @@ -644,6 +644,8 @@ static void get_instr_detail(struct pt_regs *regs, struct ppc_inst *instr, if (*type == CACHEOP) { *size = cache_op_size(); *ea &= ~(*size - 1); + } else if (*type == LOAD_VMX || *type == STORE_VMX) { + *ea &= ~(*size - 1); } } |