diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2022-08-19 01:41:45 +0200 |
|---|---|---|
| committer | Radhakrishna Sripada <radhakrishna.sripada@intel.com> | 2022-08-25 20:00:43 +0200 |
| commit | 068a0f5c8260dcc4ccbaefd2dbf21ea84162ac17 (patch) | |
| tree | 310fcd9d7721486f3bb39528416c3e3bd34c2346 | |
| parent | drm/i915/mtl: MMIO range is now 4MB (diff) | |
| download | linux-068a0f5c8260dcc4ccbaefd2dbf21ea84162ac17.tar.xz linux-068a0f5c8260dcc4ccbaefd2dbf21ea84162ac17.zip | |
drm/i915/mtl: Don't mask off CCS according to DSS fusing
Unlike the Xe_HP platforms, MTL only has a single CCS engine; the
quad-based engine masking logic does not apply to this platform (or
presumably any future platforms that only have 0 or 1 CCS).
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220818234202.451742-5-radhakrishna.sripada@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 37fa813af766..17e7f20bbb48 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -672,7 +672,7 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt) unsigned long ccs_mask; unsigned int i; - if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) + if (hweight32(CCS_MASK(gt)) <= 1) return; ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask, |