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| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2019-05-20 10:30:57 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2019-05-24 13:50:47 +0200 |
| commit | 13531e5d359e30d9e3d1cabd246a24cf6fdf084a (patch) | |
| tree | 6d7e7bc5dcab6b0076385d35f57aab76e34df6bd | |
| parent | pinctrl: meson: add output support in pinconf (diff) | |
| download | linux-13531e5d359e30d9e3d1cabd246a24cf6fdf084a.tar.xz linux-13531e5d359e30d9e3d1cabd246a24cf6fdf084a.zip | |
dt-bindings: pinctrl: Modify pinctrl memory map
Earlier, the PWM registers were included as part of the pinctrl memory
map, but this turned to be useless as the muxing is being handled by the
SoC pin controller itself. So, lets modify the pinctrl memory map to
reflect the same.
Fixes: 07b734fbdea2 ("dt-bindings: pinctrl: Add BM1880 pinctrl binding")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| -rw-r--r-- | Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt index ed34bb1ee81c..cc9a89aa4170 100644 --- a/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt @@ -85,9 +85,9 @@ Required Properties: spi0 Example: - pinctrl: pinctrl@50 { + pinctrl: pinctrl@400 { compatible = "bitmain,bm1880-pinctrl"; - reg = <0x50 0x4B0>; + reg = <0x400 0x120>; pinctrl_uart0_default: uart0-default { pinmux { |