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| author | Fugang Duan <fugang.duan@nxp.com> | 2020-09-03 12:05:21 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2020-09-05 09:56:22 +0200 |
| commit | 3ee99f6a2379eca87ab11122b7e9abd68f3441e2 (patch) | |
| tree | 9bf50ba7c7c3c3742ae3e06bc52168c6085f04d6 | |
| parent | arm64: dts: imx8mp: correct sdma1 clk setting (diff) | |
| download | linux-3ee99f6a2379eca87ab11122b7e9abd68f3441e2.tar.xz linux-3ee99f6a2379eca87ab11122b7e9abd68f3441e2.zip | |
ARM: dts: imx6sx: fix the pad QSPI1B_SCLK mux mode for uart3
The pad QSPI1B_SCLK mux mode 0x1 is for function UART3_DTE_TX,
correct the mux mode.
Fixes: 743636f25f1d ("ARM: dts: imx: add pin function header for imx6sx")
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| -rw-r--r-- | arch/arm/boot/dts/imx6sx-pinfunc.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6sx-pinfunc.h b/arch/arm/boot/dts/imx6sx-pinfunc.h index 0b02c7e60c17..f4dc46207954 100644 --- a/arch/arm/boot/dts/imx6sx-pinfunc.h +++ b/arch/arm/boot/dts/imx6sx-pinfunc.h @@ -1026,7 +1026,7 @@ #define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0 #define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0 #define MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x01B4 0x04FC 0x0840 0x1 0x4 -#define MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX 0x01B4 0x04FC 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX 0x01B4 0x04FC 0x0000 0x1 0x0 #define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1 #define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2 #define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1 |