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| author | Ziyuan Xu <xzy.xu@rock-chips.com> | 2018-10-11 09:26:43 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2018-10-11 14:36:01 +0200 |
| commit | 82f4b67f018c88a7cc9337f0067ed3d6ec352648 (patch) | |
| tree | 5cca1de112a03a24227f12a8d5cf8dfbab40373c | |
| parent | clk: rockchip: improve rk3288 pll rates for better hdmi output (diff) | |
| download | linux-82f4b67f018c88a7cc9337f0067ed3d6ec352648.tar.xz linux-82f4b67f018c88a7cc9337f0067ed3d6ec352648.zip | |
clk: rockchip: fix wrong mmc sample phase shift for rk3328
mmc sample shift is 0 for RK3328 referring to the TRM.
So fix them.
Fixes: fe3511ad8a1c ("clk: rockchip: add clock controller for rk3328")
Cc: stable@vger.kernel.org
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3328.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c index 252366a5231f..2c5426607790 100644 --- a/drivers/clk/rockchip/clk-rk3328.c +++ b/drivers/clk/rockchip/clk-rk3328.c @@ -813,22 +813,22 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3328_SDMMC_CON0, 1), MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", - RK3328_SDMMC_CON1, 1), + RK3328_SDMMC_CON1, 0), MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3328_SDIO_CON0, 1), MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", - RK3328_SDIO_CON1, 1), + RK3328_SDIO_CON1, 0), MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", RK3328_EMMC_CON0, 1), MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", - RK3328_EMMC_CON1, 1), + RK3328_EMMC_CON1, 0), MMC(SCLK_SDMMC_EXT_DRV, "sdmmc_ext_drv", "clk_sdmmc_ext", RK3328_SDMMC_EXT_CON0, 1), MMC(SCLK_SDMMC_EXT_SAMPLE, "sdmmc_ext_sample", "clk_sdmmc_ext", - RK3328_SDMMC_EXT_CON1, 1), + RK3328_SDMMC_EXT_CON1, 0), }; static const char *const rk3328_critical_clocks[] __initconst = { |