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| author | Markos Chandras <markos.chandras@imgtec.com> | 2015-03-03 19:48:49 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-04-10 15:41:46 +0200 |
| commit | aebac99384f7a6d83a3dcd42bf2481eed2670083 (patch) | |
| tree | 48bddc71c508aadf31138acdd6c3fe81a76c7370 | |
| parent | MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case (diff) | |
| download | linux-aebac99384f7a6d83a3dcd42bf2481eed2670083.tar.xz linux-aebac99384f7a6d83a3dcd42bf2481eed2670083.zip | |
MIPS: kernel: entry.S: Set correct ISA level for mips_ihb
Commit 6ebb496ffc7e("MIPS: kernel: entry.S: Add MIPS R6 related
definitions") added the MIPSR6 definition but it did not update the
ISA level of the actual assembly code so a pre-MIPSR6 jr.hb instruction
was generated instead. Fix this by using the MISP_ISA_LEVEL_RAW macro.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Fixes: 6ebb496ffc7e("MIPS: kernel: entry.S: Add MIPS R6 related definitions")
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9386/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/kernel/entry.S | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S index af41ba6db960..7791840cf22c 100644 --- a/arch/mips/kernel/entry.S +++ b/arch/mips/kernel/entry.S @@ -10,6 +10,7 @@ #include <asm/asm.h> #include <asm/asmmacro.h> +#include <asm/compiler.h> #include <asm/regdef.h> #include <asm/mipsregs.h> #include <asm/stackframe.h> @@ -185,7 +186,7 @@ syscall_exit_work: * For C code use the inline version named instruction_hazard(). */ LEAF(mips_ihb) - .set mips32r2 + .set MIPS_ISA_LEVEL_RAW jr.hb ra nop END(mips_ihb) |