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author | Shengyang Chen <shengyang.chen@starfivetech.com> | 2024-04-18 05:50:19 +0200 |
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committer | Vinod Koul <vkoul@kernel.org> | 2024-06-15 14:08:30 +0200 |
commit | e4a8e87250fc2c1ed2aec5d1e8521dc7d799ea77 (patch) | |
tree | 9a7dc62f4d2ecdaef24d5978bd31340a18068623 | |
parent | dt-bindings: phy: qcom,usb-hs-phy: Add compatible (diff) | |
download | linux-e4a8e87250fc2c1ed2aec5d1e8521dc7d799ea77.tar.xz linux-e4a8e87250fc2c1ed2aec5d1e8521dc7d799ea77.zip |
dt-bindings: phy: Add starfive,jh7110-dphy-tx
StarFive SoCs like the jh7110 use a MIPI D-PHY TX
controller based on a M31 IP. Add a binding for it.
Signed-off-by: Shengyang Chen <shengyang.chen@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240418035020.47876-2-shengyang.chen@starfivetech.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
-rw-r--r-- | Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-tx.yaml | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-tx.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-tx.yaml new file mode 100644 index 000000000000..4a06a2642b4a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-tx.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-tx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Starfive SoC MIPI D-PHY Tx Controller + +maintainers: + - Keith Zhao <keith.zhao@starfivetech.com> + - Shengyang Chen <shengyang.chen@starfivetech.com> + +description: + The Starfive SoC uses the MIPI DSI D-PHY based on M31 IP to transfer + DSI data. + +properties: + compatible: + const: starfive,jh7110-dphy-tx + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: txesc + + resets: + items: + - description: MIPITX_DPHY_SYS reset + + reset-names: + items: + - const: sys + + power-domains: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - power-domains + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@295e0000 { + compatible = "starfive,jh7110-dphy-tx"; + reg = <0x295e0000 0x10000>; + clocks = <&voutcrg 14>; + clock-names = "txesc"; + resets = <&syscrg 10>; + reset-names = "sys"; + power-domains = <&aon_syscon 0>; + #phy-cells = <0>; + }; |