diff options
| author | Biao Huang <biao.huang@mediatek.com> | 2019-05-24 08:26:09 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2019-05-25 20:02:31 +0200 |
| commit | f4ca7a9260dfe700f2a16f0881825de625067515 (patch) | |
| tree | 5c28de197a879032f2fa9be19eb49c6eddad048c | |
| parent | net: stmmac: fix csr_clk can't be zero issue (diff) | |
| download | linux-f4ca7a9260dfe700f2a16f0881825de625067515.tar.xz linux-f4ca7a9260dfe700f2a16f0881825de625067515.zip | |
net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail
1. the frequency of csr clock is 66.5MHz, so the csr_clk value should
be 0 other than 5.
2. the csr_clk can be got from device tree, so remove initialization here.
Fixes: 9992f37e346b ("stmmac: dwmac-mediatek: add support for mt2712")
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c index bf2562995fc8..126b66bb73a6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -346,8 +346,6 @@ static int mediatek_dwmac_probe(struct platform_device *pdev) return PTR_ERR(plat_dat); plat_dat->interface = priv_plat->phy_mode; - /* clk_csr_i = 250-300MHz & MDC = clk_csr_i/124 */ - plat_dat->clk_csr = 5; plat_dat->has_gmac4 = 1; plat_dat->has_gmac = 0; plat_dat->pmt = 0; |