diff options
| author | Paul Burton <paul.burton@imgtec.com> | 2015-09-22 19:26:38 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-10-26 09:49:46 +0100 |
| commit | 03b1b85d3d6c4f4153472afb7e015f1352e0c8f2 (patch) | |
| tree | cf205e231c93d84f9b330aa5e7196f0378feea58 | |
| parent | MIPS: Clarify mips_cm_is64 documentation (diff) | |
| download | linux-03b1b85d3d6c4f4153472afb7e015f1352e0c8f2.tar.xz linux-03b1b85d3d6c4f4153472afb7e015f1352e0c8f2.zip | |
MIPS: Don't read GCRs when a CM is not present
Commit 3885c2b463f6 ("MIPS: CM: Add support for reporting CM cache
errors") leads to Malta boards unconditionally reading CM GCRs upon bus
errors, regardless of whether a CM is present. This is incorrect & will
lead to further exceptions. Fix by moving the GCR reads to after the
check for whether a CM is present.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11186/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/kernel/mips-cm.c | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index b8ceee576cdf..10524ce769ae 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -252,7 +252,6 @@ int mips_cm_probe(void) void mips_cm_error_report(void) { - unsigned long revision = mips_cm_revision(); /* * CM3 has a 64-bit Error cause register with 0:57 containing the error * info and 63:58 the error type. For old CMs, everything is contained @@ -260,17 +259,21 @@ void mips_cm_error_report(void) * though the cm_error is u64, we will simply ignore the upper word * for CM2. */ - u64 cm_error = read_gcr_error_cause(); - int cm_error_cause_sft = CM_GCR_ERROR_CAUSE_ERRTYPE_SHF + - ((revision >= CM_REV_CM3) ? 31 : 0); - unsigned long cm_addr = read_gcr_error_addr(); - unsigned long cm_other = read_gcr_error_mult(); - int ocause, cause; + u64 cm_error; + unsigned long revision, cm_addr, cm_other; + int ocause, cause, cm_error_cause_sft; char buf[256]; if (!mips_cm_present()) return; + revision = mips_cm_revision(); + cm_error = read_gcr_error_cause(); + cm_addr = read_gcr_error_addr(); + cm_other = read_gcr_error_mult(); + + cm_error_cause_sft = CM_GCR_ERROR_CAUSE_ERRTYPE_SHF + + ((revision >= CM_REV_CM3) ? 31 : 0); cause = cm_error >> cm_error_cause_sft; if (!cause) |