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| author | Petr Cvek <petrcvekcz@gmail.com> | 2019-06-20 23:39:33 +0200 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2019-06-24 23:15:03 +0200 |
| commit | aa0f58b4666f7662d178905ac45d94914f72d3d4 (patch) | |
| tree | 225a7f1a9d91c6e1d88a340b0236e5073f354212 | |
| parent | mips: Remove q-accessors from non-64bit platforms (diff) | |
| download | linux-aa0f58b4666f7662d178905ac45d94914f72d3d4.tar.xz linux-aa0f58b4666f7662d178905ac45d94914f72d3d4.zip | |
MIPS: lantiq: Move macro directly to iomem function
Using the variable as a temporary holder for the macro of the register
offset value is not necessary. Move it directly to the IOMEM read/write
call.
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: hauke@hauke-m.de
Cc: john@phrozen.org
Cc: linux-mips@vger.kernel.org
Cc: openwrt-devel@lists.openwrt.org
Cc: pakahmar@hotmail.com
| -rw-r--r-- | arch/mips/lantiq/irq.c | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index 6549499eb202..fb3e1cc2cf6b 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -77,44 +77,42 @@ int ltq_eiu_get_irq(int exin) void ltq_disable_irq(struct irq_data *d) { - u32 ier = LTQ_ICU_IM0_IER; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; int im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); + ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) & ~BIT(offset), + LTQ_ICU_IM0_IER); } void ltq_mask_and_ack_irq(struct irq_data *d) { - u32 ier = LTQ_ICU_IM0_IER; - u32 isr = LTQ_ICU_IM0_ISR; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; int im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); - ltq_icu_w32(im, BIT(offset), isr); + ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) & ~BIT(offset), + LTQ_ICU_IM0_IER); + ltq_icu_w32(im, BIT(offset), LTQ_ICU_IM0_ISR); } static void ltq_ack_irq(struct irq_data *d) { - u32 isr = LTQ_ICU_IM0_ISR; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; int im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, BIT(offset), isr); + ltq_icu_w32(im, BIT(offset), LTQ_ICU_IM0_ISR); } void ltq_enable_irq(struct irq_data *d) { - u32 ier = LTQ_ICU_IM0_IER; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; int im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier); + ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) | BIT(offset), + LTQ_ICU_IM0_IER); } static int ltq_eiu_settype(struct irq_data *d, unsigned int type) |