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| author | Kan Liang <kan.liang@linux.intel.com> | 2021-06-30 23:08:29 +0200 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2021-07-02 15:58:38 +0200 |
| commit | f85ef898f8842b2a9a8f51a64eaf45ee2a8bb1f7 (patch) | |
| tree | 554bc6eb9a4d2d2b3c462b5e067fa71f110af067 | |
| parent | perf/x86/intel/uncore: Add Sapphire Rapids server IRP support (diff) | |
| download | linux-f85ef898f8842b2a9a8f51a64eaf45ee2a8bb1f7.tar.xz linux-f85ef898f8842b2a9a8f51a64eaf45ee2a8bb1f7.zip | |
perf/x86/intel/uncore: Add Sapphire Rapids server M2PCIe support
M2PCIe* blocks manage the interface between the mesh and each IIO stack.
The layout of the control registers for a M2PCIe uncore unit is similar
to a IRP uncore unit.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-6-git-send-email-kan.liang@linux.intel.com
| -rw-r--r-- | arch/x86/events/intel/uncore_snbep.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c index de5a6d1f1735..890a98279fca 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -5628,13 +5628,18 @@ static struct intel_uncore_type spr_uncore_irp = { }; +static struct intel_uncore_type spr_uncore_m2pcie = { + SPR_UNCORE_COMMON_FORMAT(), + .name = "m2pcie", +}; + #define UNCORE_SPR_NUM_UNCORE_TYPES 12 static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = { &spr_uncore_chabox, &spr_uncore_iio, &spr_uncore_irp, - NULL, + &spr_uncore_m2pcie, NULL, NULL, NULL, |