diff options
| author | Thierry Reding <treding@nvidia.com> | 2016-06-23 12:52:30 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-06-23 17:46:33 +0200 |
| commit | 2e34c2ac16ee6574743c73caa3d796e307f028a6 (patch) | |
| tree | b9e52b5e1af7a7e4670bc2a40e4ffc7f0b49d89b | |
| parent | clk: tegra: Mark timer clock as critical (diff) | |
| download | linux-2e34c2ac16ee6574743c73caa3d796e307f028a6.tar.xz linux-2e34c2ac16ee6574743c73caa3d796e307f028a6.zip | |
clk: tegra: Make sor_safe the parent of dpaux and dpaux1
It turns out that sor_safe, rather than pll_p, is the parent of the
dpaux and dpaux1 clocks.
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | drivers/clk/tegra/clk-tegra210.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index aab32af77aa2..fe295b4102ca 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2466,11 +2466,11 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, 1, 2); clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk; - clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base, + clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base, 1, 17, 181); clks[TEGRA210_CLK_DPAUX] = clk; - clk = tegra_clk_register_periph_fixed("dpaux1", "pll_p", 0, clk_base, + clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base, 1, 17, 207); clks[TEGRA210_CLK_DPAUX1] = clk; |