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authorChen-Yu Tsai <wens@csie.org>2014-11-26 08:16:53 +0100
committerMaxime Ripard <maxime.ripard@free-electrons.com>2014-12-21 23:51:37 +0100
commit42cc71365ebf1ec35a667d76d32be8503c6d84e9 (patch)
tree91c1f68e27b6db1faef734a139d5e34c0ad00d88
parentclk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider (diff)
downloadlinux-42cc71365ebf1ec35a667d76d32be8503c6d84e9.tar.xz
linux-42cc71365ebf1ec35a667d76d32be8503c6d84e9.zip
ARM: dts: sun6i: Unify ahb1 clock nodes
The clock driver has unified support for the ahb1 clock. Unify the clock nodes so it works. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi14
1 files changed, 3 insertions, 11 deletions
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index f47156b6572b..62d932e9b7d1 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -174,19 +174,11 @@
clock-output-names = "axi";
};
- ahb1_mux: ahb1_mux@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
- clock-output-names = "ahb1_mux";
- };
-
ahb1: ahb1@01c20054 {
#clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-ahb-clk";
+ compatible = "allwinner,sun6i-a31-ahb1-clk";
reg = <0x01c20054 0x4>;
- clocks = <&ahb1_mux>;
+ clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
clock-output-names = "ahb1";
};
@@ -367,7 +359,7 @@
#dma-cells = <1>;
/* DMA controller requires AHB1 clocked from PLL6 */
- assigned-clocks = <&ahb1_mux>;
+ assigned-clocks = <&ahb1>;
assigned-clock-parents = <&pll6 0>;
};