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| author | Marc Zyngier <marc.zyngier@arm.com> | 2018-03-20 19:21:37 +0100 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2018-03-20 20:12:15 +0100 |
| commit | 66569052fe5328729ff696c1ec17913907d00b5f (patch) | |
| tree | 4350bd64bf5b1297a5b1bf42123fc5134c7aaffb | |
| parent | irqchip/gic-v3: Do not check trigger configuration of partitionned LPIs (diff) | |
| download | linux-66569052fe5328729ff696c1ec17913907d00b5f.tar.xz linux-66569052fe5328729ff696c1ec17913907d00b5f.zip | |
irqchip/gic-v3: Don't try to reset AP0Rn
Clearing AP0Rn has created a number of regressions, due to systems
that have SCR_EL3.FIQ set. Even when addressing some obvious bugs,
GIC500 platforms seem to act bizarrely (we are supposed to have
5 bits of priority, but PMR seems to behave as if we had 6...).
Drop the AP0Rn reset for the time being, it is unlikely to have any
effect if kexec-ing.
Fixes: d6062a6d62c6 irqchip/gic-v3: Reset APgRn registers at boot time
Reported-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| -rw-r--r-- | drivers/irqchip/irq-gic-v3.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 0d8e326ebf19..e2b90bec1473 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -570,16 +570,12 @@ static void gic_cpu_sys_reg_init(void) switch(val + 1) { case 8: case 7: - write_gicreg(0, ICC_AP0R3_EL1); write_gicreg(0, ICC_AP1R3_EL1); - write_gicreg(0, ICC_AP0R2_EL1); write_gicreg(0, ICC_AP1R2_EL1); case 6: - write_gicreg(0, ICC_AP0R1_EL1); write_gicreg(0, ICC_AP1R1_EL1); case 5: case 4: - write_gicreg(0, ICC_AP0R0_EL1); write_gicreg(0, ICC_AP1R0_EL1); } |