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author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2013-03-10 13:34:36 +0100 |
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committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2013-06-15 15:17:08 +0200 |
commit | f1741fda07fb1808ac58f7c97634cc28b8dd1727 (patch) | |
tree | 3455a483ecb36845a1bbe5d0ecad1e60d1995d5a | |
parent | ARM: sunxi: dt: Register the pio node as interrupt controller (diff) | |
download | linux-f1741fda07fb1808ac58f7c97634cc28b8dd1727.tar.xz linux-f1741fda07fb1808ac58f7c97634cc28b8dd1727.zip |
ARM: sunxi: dt: Add i2c controller nodes to the DTSI
The Allwinner A10 and A13 both have 3 i2c controller embedded.
Add those to the common sunxi dtsi.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com>
-rw-r--r-- | arch/arm/boot/dts/sun4i-a10.dtsi | 27 | ||||
-rw-r--r-- | arch/arm/boot/dts/sun5i-a13.dtsi | 27 |
2 files changed, 54 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 9b3c99c83892..ba15178f04ba 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -294,5 +294,32 @@ clocks = <&apb1_gates 23>; status = "disabled"; }; + + i2c0: i2c@01c2ac00 { + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <7>; + clocks = <&apb1_gates 0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@01c2b000 { + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <8>; + clocks = <&apb1_gates 1>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c2: i2c@01c2b400 { + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <9>; + clocks = <&apb1_gates 2>; + clock-frequency = <100000>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index f34db19d17d7..31ebfd721195 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -217,5 +217,32 @@ clocks = <&apb1_gates 19>; status = "disabled"; }; + + i2c0: i2c@01c2ac00 { + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <7>; + clocks = <&apb1_gates 0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@01c2b000 { + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <8>; + clocks = <&apb1_gates 1>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c2: i2c@01c2b400 { + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <9>; + clocks = <&apb1_gates 2>; + clock-frequency = <100000>; + status = "disabled"; + }; }; }; |