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authorMarc Zyngier <marc.zyngier@arm.com>2015-03-12 09:40:37 +0100
committerShawn Guo <shawn.guo@linaro.org>2015-03-30 10:43:50 +0200
commite33b67523f556aa7ddb09f1c7fa4de5c080670c9 (patch)
treeb6fc0ec34e3766a796191fd0255d2f27d151ad3e
parentARM: imx6qdl-sabreauto.dtsi: add max7310 support (diff)
downloadlinux-e33b67523f556aa7ddb09f1c7fa4de5c080670c9.tar.xz
linux-e33b67523f556aa7ddb09f1c7fa4de5c080670c9.zip
ARM: imx6: Allow GPC interrupts affinity to be changed
While converting the GPC code to a stacked irqchip, we lost the possibility to change the CPU affinity of an interrupt routed through the GPC. This patch restore the expected behaviour by forwarding the affinity setup to the underlying irqchip (GIC). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-rw-r--r--arch/arm/mach-imx/gpc.c15
1 files changed, 9 insertions, 6 deletions
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 6f1f77ed0c71..5d32e35fbe47 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -170,12 +170,15 @@ static void imx_gpc_irq_mask(struct irq_data *d)
}
static struct irq_chip imx_gpc_chip = {
- .name = "GPC",
- .irq_eoi = irq_chip_eoi_parent,
- .irq_mask = imx_gpc_irq_mask,
- .irq_unmask = imx_gpc_irq_unmask,
- .irq_retrigger = irq_chip_retrigger_hierarchy,
- .irq_set_wake = imx_gpc_irq_set_wake,
+ .name = "GPC",
+ .irq_eoi = irq_chip_eoi_parent,
+ .irq_mask = imx_gpc_irq_mask,
+ .irq_unmask = imx_gpc_irq_unmask,
+ .irq_retrigger = irq_chip_retrigger_hierarchy,
+ .irq_set_wake = imx_gpc_irq_set_wake,
+#ifdef CONFIG_SMP
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+#endif
};
static int imx_gpc_domain_xlate(struct irq_domain *domain,