diff options
author | Bjorn Helgaas <bhelgaas@google.com> | 2012-12-07 20:11:52 +0100 |
---|---|---|
committer | Bjorn Helgaas <bhelgaas@google.com> | 2012-12-07 20:11:52 +0100 |
commit | 27e1c8ee0170e80f6426c35d54f3b5cd9dadb25b (patch) | |
tree | 5188300ea7cc05db7aebee53366c0556e5d8eaf9 | |
parent | Merge branch 'pci/mjg-pci-roms-from-efi' into next (diff) | |
parent | ath9k: Use standard #defines for PCIe Capability ASPM fields (diff) | |
download | linux-27e1c8ee0170e80f6426c35d54f3b5cd9dadb25b.tar.xz linux-27e1c8ee0170e80f6426c35d54f3b5cd9dadb25b.zip |
Merge branch 'pci/bjorn-pcie-cap' into next
* pci/bjorn-pcie-cap:
ath9k: Use standard #defines for PCIe Capability ASPM fields
iwlwifi: Use standard #defines for PCIe Capability ASPM fields
iwlwifi: collapse wrapper for pcie_capability_read_word()
iwlegacy: Use standard #defines for PCIe Capability ASPM fields
iwlegacy: collapse wrapper for pcie_capability_read_word()
cxgb3: Use standard #defines for PCIe Capability ASPM fields
PCI: Add standard PCIe Capability Link ASPM field names
PCI/portdrv: Use PCI Express Capability accessors
PCI: Use standard PCIe Capability Link register field names
PCI: Add and use standard PCI-X Capability register names
-rw-r--r-- | drivers/net/ethernet/chelsio/cxgb3/t3_hw.c | 2 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/pci.c | 8 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/4965.h | 4 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/common.c | 10 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/common.h | 12 | ||||
-rw-r--r-- | drivers/net/wireless/iwlwifi/pcie/trans.c | 20 | ||||
-rw-r--r-- | drivers/pci/pcie/aspm.c | 11 | ||||
-rw-r--r-- | drivers/pci/pcie/portdrv_core.c | 3 | ||||
-rw-r--r-- | drivers/pci/probe.c | 19 | ||||
-rw-r--r-- | include/uapi/linux/pci_regs.h | 17 |
10 files changed, 49 insertions, 57 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c index aef45d3113ba..3dee68612c9e 100644 --- a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c +++ b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c @@ -3307,7 +3307,7 @@ static void config_pcie(struct adapter *adap) G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE)); log2_width = fls(adap->params.pci.width) - 1; acklat = ack_lat[log2_width][pldsize]; - if (val & 1) /* check LOsEnable */ + if (val & PCI_EXP_LNKCTL_ASPM_L0S) /* check LOsEnable */ acklat += fst_trn_tx * 4; rpllmt = rpl_tmr[log2_width][pldsize] + fst_trn_rx * 4; diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c index f088f4bf9a26..71d82078fc7f 100644 --- a/drivers/net/wireless/ath/ath9k/pci.c +++ b/drivers/net/wireless/ath/ath9k/pci.c @@ -125,23 +125,23 @@ static void ath_pci_aspm_init(struct ath_common *common) if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) && (AR_SREV_9285(ah))) { - /* Bluetooth coexistance requires disabling ASPM. */ + /* Bluetooth coexistence requires disabling ASPM. */ pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, - PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); + PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1); /* * Both upstream and downstream PCIe components should * have the same ASPM settings. */ pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, - PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); + PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1); ath_info(common, "Disabling ASPM since BTCOEX is enabled\n"); return; } pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm); - if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) { + if (aspm & (PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1)) { ah->aspm_enabled = true; /* Initialize PCIe PM and SERDES registers. */ ath9k_hw_configpcipowersave(ah, false); diff --git a/drivers/net/wireless/iwlegacy/4965.h b/drivers/net/wireless/iwlegacy/4965.h index 2d092f328547..1b15b0b2292b 100644 --- a/drivers/net/wireless/iwlegacy/4965.h +++ b/drivers/net/wireless/iwlegacy/4965.h @@ -917,10 +917,6 @@ struct il4965_scd_bc_tbl { /* PCI registers */ #define PCI_CFG_RETRY_TIMEOUT 0x041 -/* PCI register values */ -#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01 -#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02 - #define IL4965_DEFAULT_TX_RETRY 15 /* EEPROM */ diff --git a/drivers/net/wireless/iwlegacy/common.c b/drivers/net/wireless/iwlegacy/common.c index 318ed3c9fe74..7e16d10a7f14 100644 --- a/drivers/net/wireless/iwlegacy/common.c +++ b/drivers/net/wireless/iwlegacy/common.c @@ -1183,9 +1183,10 @@ EXPORT_SYMBOL(il_power_update_mode); void il_power_initialize(struct il_priv *il) { - u16 lctl = il_pcie_link_ctl(il); + u16 lctl; - il->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN); + pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl); + il->power_data.pci_pm = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); il->power_data.debug_sleep_level_override = -1; @@ -4233,9 +4234,8 @@ il_apm_init(struct il_priv *il) * power savings, even without L1. */ if (il->cfg->set_l0s) { - lctl = il_pcie_link_ctl(il); - if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == - PCI_CFG_LINK_CTRL_VAL_L1_EN) { + pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl); + if (lctl & PCI_EXP_LNKCTL_ASPM_L1) { /* L1-ASPM enabled; disable(!) L0S */ il_set_bit(il, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); diff --git a/drivers/net/wireless/iwlegacy/common.h b/drivers/net/wireless/iwlegacy/common.h index b4bb813362bd..e181f3b573d9 100644 --- a/drivers/net/wireless/iwlegacy/common.h +++ b/drivers/net/wireless/iwlegacy/common.h @@ -1829,14 +1829,6 @@ int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd); * PCI * *****************************************************/ -static inline u16 -il_pcie_link_ctl(struct il_priv *il) -{ - u16 pci_lnk_ctl; - pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &pci_lnk_ctl); - return pci_lnk_ctl; -} - void il_bg_watchdog(unsigned long data); u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval); __le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon, @@ -2434,10 +2426,6 @@ struct il_tfd { /* PCI registers */ #define PCI_CFG_RETRY_TIMEOUT 0x041 -/* PCI register values */ -#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01 -#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02 - struct il_rate_info { u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */ u8 plcp_siso; /* uCode API: RATE_SISO_6M_PLCP, etc. */ diff --git a/drivers/net/wireless/iwlwifi/pcie/trans.c b/drivers/net/wireless/iwlwifi/pcie/trans.c index fe0fffd04304..1dfa6be03058 100644 --- a/drivers/net/wireless/iwlwifi/pcie/trans.c +++ b/drivers/net/wireless/iwlwifi/pcie/trans.c @@ -670,21 +670,12 @@ static void iwl_set_pwr_vmain(struct iwl_trans *trans) /* PCI registers */ #define PCI_CFG_RETRY_TIMEOUT 0x041 -#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01 -#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02 -static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans) +static void iwl_apm_config(struct iwl_trans *trans) { struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); - u16 pci_lnk_ctl; - - pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, - &pci_lnk_ctl); - return pci_lnk_ctl; -} + u16 lctl; -static void iwl_apm_config(struct iwl_trans *trans) -{ /* * HW bug W/A for instability in PCIe bus L0S->L1 transition. * Check if BIOS (or OS) enabled L1-ASPM on this device. @@ -693,10 +684,9 @@ static void iwl_apm_config(struct iwl_trans *trans) * If not (unlikely), enable L0S, so there is at least some * power savings, even without L1. */ - u16 lctl = iwl_pciexp_link_ctrl(trans); - if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == - PCI_CFG_LINK_CTRL_VAL_L1_EN) { + pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); + if (lctl & PCI_EXP_LNKCTL_ASPM_L1) { /* L1-ASPM enabled; disable(!) L0S */ iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); dev_printk(KERN_INFO, trans->dev, @@ -707,7 +697,7 @@ static void iwl_apm_config(struct iwl_trans *trans) dev_printk(KERN_INFO, trans->dev, "L1 Disabled; Enabling L0S\n"); } - trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN); + trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); } /* diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 3da9ecc9ab84..b52630b8eada 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -426,7 +426,8 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val) { - pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL, 0x3, val); + pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_ASPMC, val); } static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state) @@ -441,12 +442,12 @@ static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state) return; /* Convert ASPM state to upstream/downstream ASPM register state */ if (state & ASPM_STATE_L0S_UP) - dwstream |= PCIE_LINK_STATE_L0S; + dwstream |= PCI_EXP_LNKCTL_ASPM_L0S; if (state & ASPM_STATE_L0S_DW) - upstream |= PCIE_LINK_STATE_L0S; + upstream |= PCI_EXP_LNKCTL_ASPM_L0S; if (state & ASPM_STATE_L1) { - upstream |= PCIE_LINK_STATE_L1; - dwstream |= PCIE_LINK_STATE_L1; + upstream |= PCI_EXP_LNKCTL_ASPM_L1; + dwstream |= PCI_EXP_LNKCTL_ASPM_L1; } /* * Spec 2.0 suggests all functions should be configured the diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index ed129b414624..b42133afca98 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -120,8 +120,7 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask) * the value in this field indicates which MSI-X Table entry is * used to generate the interrupt message." */ - pos = pci_pcie_cap(dev); - pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); + pcie_capability_read_word(dev, PCI_EXP_FLAGS, ®16); entry = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9; if (entry >= nr_entries) goto Error; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 293af5a6f912..d46ef2df23da 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -521,7 +521,7 @@ static unsigned char pcie_link_speed[] = { void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) { - bus->cur_bus_speed = pcie_link_speed[linksta & 0xf]; + bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; } EXPORT_SYMBOL_GPL(pcie_update_link_speed); @@ -579,14 +579,16 @@ static void pci_set_bus_speed(struct pci_bus *bus) if (pos) { u16 status; enum pci_bus_speed max; - pci_read_config_word(bridge, pos + 2, &status); - if (status & 0x8000) { + pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, + &status); + + if (status & PCI_X_SSTATUS_533MHZ) { max = PCI_SPEED_133MHz_PCIX_533; - } else if (status & 0x4000) { + } else if (status & PCI_X_SSTATUS_266MHZ) { max = PCI_SPEED_133MHz_PCIX_266; - } else if (status & 0x0002) { - if (((status >> 12) & 0x3) == 2) { + } else if (status & PCI_X_SSTATUS_133MHZ) { + if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) { max = PCI_SPEED_133MHz_PCIX_ECC; } else { max = PCI_SPEED_133MHz_PCIX; @@ -596,7 +598,8 @@ static void pci_set_bus_speed(struct pci_bus *bus) } bus->max_bus_speed = max; - bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf]; + bus->cur_bus_speed = pcix_bus_speed[ + (status & PCI_X_SSTATUS_FREQ) >> 6]; return; } @@ -607,7 +610,7 @@ static void pci_set_bus_speed(struct pci_bus *bus) u16 linksta; pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); - bus->max_bus_speed = pcie_link_speed[linkcap & 0xf]; + bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); pcie_update_link_speed(bus, linksta); diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 259763d2df71..6b7b6f1e2fd6 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -349,7 +349,7 @@ #define PCI_AF_STATUS_TP 0x01 #define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */ -/* PCI-X registers */ +/* PCI-X registers (Type 0 (non-bridge) devices) */ #define PCI_X_CMD 2 /* Modes & Features */ #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ @@ -389,6 +389,19 @@ #define PCI_CAP_PCIX_SIZEOF_V1 24 /* size for Version 1 */ #define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */ +/* PCI-X registers (Type 1 (bridge) devices) */ + +#define PCI_X_BRIDGE_SSTATUS 2 /* Secondary Status */ +#define PCI_X_SSTATUS_64BIT 0x0001 /* Secondary AD interface is 64 bits */ +#define PCI_X_SSTATUS_133MHZ 0x0002 /* 133 MHz capable */ +#define PCI_X_SSTATUS_FREQ 0x03c0 /* Secondary Bus Mode and Frequency */ +#define PCI_X_SSTATUS_VERS 0x3000 /* PCI-X Capability Version */ +#define PCI_X_SSTATUS_V1 0x1000 /* Mode 2, not Mode 1 */ +#define PCI_X_SSTATUS_V2 0x2000 /* Mode 1 or Modes 1 and 2 */ +#define PCI_X_SSTATUS_266MHZ 0x4000 /* 266 MHz capable */ +#define PCI_X_SSTATUS_533MHZ 0x8000 /* 533 MHz capable */ +#define PCI_X_BRIDGE_STATUS 4 /* Bridge Status */ + /* PCI Bridge Subsystem ID registers */ #define PCI_SSVID_VENDOR_ID 4 /* PCI-Bridge subsystem vendor id register */ @@ -456,6 +469,8 @@ #define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ #define PCI_EXP_LNKCTL 16 /* Link Control */ #define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */ +#define PCI_EXP_LNKCTL_ASPM_L0S 0x01 /* L0s Enable */ +#define PCI_EXP_LNKCTL_ASPM_L1 0x02 /* L1 Enable */ #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ #define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */ #define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */ |