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| author | Guilherme G. Piccoli <gpiccoli@linux.vnet.ibm.com> | 2017-09-21 21:29:01 +0200 |
|---|---|---|
| committer | Paul E. McKenney <paulmck@linux.vnet.ibm.com> | 2017-10-20 20:09:32 +0200 |
| commit | 5692fcc671ac8a10bfd0e75d52f0259fe767b56c (patch) | |
| tree | 46b532f50defd2f014896f0287074a18f52770e9 | |
| parent | memory-barriers.txt: Fix typo in pairing example (diff) | |
| download | linux-5692fcc671ac8a10bfd0e75d52f0259fe767b56c.tar.xz linux-5692fcc671ac8a10bfd0e75d52f0259fe767b56c.zip | |
doc: Rewrite confusing statement about memory barriers
The "Write (or store) memory barriers" bullet of the "Variety of memory
barriers" section, calls out a sequential order of stores, which is
confusing since sequential ordering is not guaranteed.
This commit therefore rewords to avoid mentioning a sequence of stores
to clarify the intent.
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Signed-off-by: Guilherme G. Piccoli <gpiccoli@linux.vnet.ibm.com>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
| -rw-r--r-- | Documentation/memory-barriers.txt | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index f37375544d71..519940ec767f 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -383,8 +383,8 @@ Memory barriers come in four basic varieties: to have any effect on loads. A CPU can be viewed as committing a sequence of store operations to the - memory system as time progresses. All stores before a write barrier will - occur in the sequence _before_ all the stores after the write barrier. + memory system as time progresses. All stores _before_ a write barrier + will occur _before_ all the stores after the write barrier. [!] Note that write barriers should normally be paired with read or data dependency barriers; see the "SMP barrier pairing" subsection. |