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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-04-03 11:54:14 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-04-03 12:34:24 +0200 |
| commit | 57ff9d736e05bede56fdb47599fdddb3408d4651 (patch) | |
| tree | da27211724cbe327aad6edccbaaf1f18d8f92df3 | |
| parent | ARM: dts: r8a7792: Correct Z clock (diff) | |
| download | linux-57ff9d736e05bede56fdb47599fdddb3408d4651.tar.xz linux-57ff9d736e05bede56fdb47599fdddb3408d4651.zip | |
ARM: dts: r8a7794: Add Z2 clock
Add the Z2 clock (Cortex-A7 CPU core clock), which uses a fixed divider,
and link the first CPU node to it.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| -rw-r--r-- | arch/arm/boot/dts/r8a7794.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 2f6e94fd408c..a19b884fb258 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -43,6 +43,7 @@ compatible = "arm,cortex-a7"; reg = <0>; clock-frequency = <1000000000>; + clocks = <&z2_clk>; power-domains = <&sysc R8A7794_PD_CA7_CPU0>; next-level-cache = <&L2_CA7>; }; @@ -1064,6 +1065,13 @@ clock-div = <2>; clock-mult = <1>; }; + z2_clk: z2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL0>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; zg_clk: zg { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |