diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2022-03-28 20:52:53 +0200 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2022-03-28 20:52:53 +0200 |
| commit | ff61bc81b3feebcef4d0431a92e2e40e8d4fe8b3 (patch) | |
| tree | 7a8a2e21ba46d6f8651f992e817781fcda884e40 | |
| parent | Reinstate some of "swiotlb: rework "fix info leak with DMA_FROM_DEVICE"" (diff) | |
| parent | pinctrl: mediatek: common-v1: fix semicolon.cocci warnings (diff) | |
| download | linux-ff61bc81b3feebcef4d0431a92e2e40e8d4fe8b3.tar.xz linux-ff61bc81b3feebcef4d0431a92e2e40e8d4fe8b3.zip | |
Merge tag 'pinctrl-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"No core changes this time. Just new driver code and improvements!
New drivers:
- New driver for the Broadcom BCM4908 SoC.
- New subdriver for Tesla FSD (Full Self Driving) SoC, a derivative
of the Samsung Exynos pin control driver.
- New driver for the Amlogic Meson S4 SoC.
- New driver for the Sunplus SP7021 SoC.
- New driver for the Microsemi Ocelot family ServalT SoC.
- New subdriver for Intel Alder Lake-M SoC.
- New subdriver for Intel Ice Lake-N SoC, including PCH support.
- New subdriver for Renesas R8A779F0 SoC.
- New subdriver for Mediatek MT8186 SoC.
- New subdriver for NXP Freescale i.MX93 SoC.
- New driver for Nuvoton WPCM450 SoC.
- New driver for Qualcomm SC8280XP SoC.
Improvements:
- Wakeup support on Samsung Exynos850 and ExynosAutov9.
- Serious and voluminous maintenance cleanup and refactoring in the
Renesas drivers. Mainly sharing similar data between the different
SoC subdrivers.
- Qualcomm SM8450 EGPIO support.
- Drive strength support on the Mediatek MT8195.
- Add some missing groups and functions to the Ralink RT2880"
* tag 'pinctrl-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (188 commits)
pinctrl: mediatek: common-v1: fix semicolon.cocci warnings
pinctrl: nuvoton: wpcm450: Fix build error without OF
pinctrl: qcom-pmic-gpio: Add support for pm8450
dt-bindings: pinctrl: aspeed: Update gfx node in example
dt-bindings: pinctrl: rt2880: add missing pin groups and functions
pinctrl: ingenic: Fix regmap on X series SoCs
pinctrl: nuvoton: Fix return value check in wpcm450_gpio_register()
pinctrl: nuvoton: wpcm450: off by one in wpcm450_gpio_register()
pinctrl: nuvoton: wpcm450: select GENERIC_PINCTRL_GROUPS
pinctrl: nuvoton: Fix sparse warning
pinctrl: mediatek: mt8186: Account for probe refactoring
pinctrl: mediatek: common-v1: Commonize spec_ies_smt_set callback
pinctrl: mediatek: common-v1: Commonize spec_pupd callback
pinctrl: mediatek: common-v1: Use common probe function
pinctrl: mediatek: common-v1: Add common probe function
pinctrl: mediatek: paris: Unify probe function by using OF match data
pinctrl/rockchip: Add missing of_node_put() in rockchip_pinctrl_probe
pinctrl: nomadik: Add missing of_node_put() in nmk_pinctrl_probe
pinctrl: berlin: fix error return code of berlin_pinctrl_build_state()
pinctrl: qcom: Introduce sc8280xp TLMM driver
...
135 files changed, 19104 insertions, 3941 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml index acd60c85b4cc..7c25c8d51116 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml @@ -75,6 +75,7 @@ additionalProperties: false examples: - | + #include <dt-bindings/clock/aspeed-clock.h> apb { compatible = "simple-bus"; #address-cells = <1>; @@ -84,6 +85,8 @@ examples: syscon: scu@1e6e2000 { compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0x1a8>; + #clock-cells = <1>; + #reset-cells = <1>; pinctrl: pinctrl { compatible = "aspeed,ast2500-pinctrl"; @@ -104,6 +107,12 @@ examples: gfx: display@1e6e6000 { compatible = "aspeed,ast2500-gfx", "syscon"; reg = <0x1e6e6000 0x1000>; + reg-io-width = <4>; + clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; + resets = <&syscon ASPEED_RESET_CRT1>; + interrupts = <0x19>; + syscon = <&syscon>; + memory-region = <&gfx_memory>; }; }; @@ -130,3 +139,10 @@ examples: }; }; }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt index 4eaae32821ae..e047a198db38 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt @@ -85,7 +85,7 @@ Optional Properties (for I2C pins): - function: String. Specifies the pin mux selection. Values must be one of: "alt1", "alt2", "alt3", "alt4" - bias-pull-up: Integer. Pull up strength in Ohm. There are 3 - pull-up resisitors (1.2k, 1.8k, 2.7k) available + pull-up resistors (1.2k, 1.8k, 2.7k) available in parallel for I2C pins, so the valid values are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm. - bias-disable: No arguments. Disable pin bias. diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml new file mode 100644 index 000000000000..175a992f15e1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm4908-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM4908 pin controller + +maintainers: + - RafaÅ‚ MiÅ‚ecki <rafal@milecki.pl> + +description: + Binding for pin controller present on BCM4908 family SoCs. + +properties: + compatible: + const: brcm,bcm4908-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + $ref: pinmux-node.yaml# + + properties: + function: + enum: [ led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7, led_8, + led_9, led_10, led_11, led_12, led_13, led_14, led_15, led_16, + led_17, led_18, led_19, led_20, led_21, led_22, led_23, led_24, + led_25, led_26, led_27, led_28, led_29, led_30, led_31, + hs_uart, i2c, i2s, nand_ctrl, nand_data, emmc_ctrl, usb0_pwr, + usb1_pwr ] + + groups: + minItems: 1 + maxItems: 2 + items: + enum: [ led_0_grp_a, led_1_grp_a, led_2_grp_a, led_3_grp_a, + led_4_grp_a, led_5_grp_a, led_6_grp_a, led_7_grp_a, + led_8_grp_a, led_9_grp_a, led_10_grp_a, led_10_grp_b, + led_11_grp_a, led_11_grp_b, led_12_grp_a, led_12_grp_b, + led_13_grp_a, led_13_grp_b, led_14_grp_a, led_15_grp_a, + led_16_grp_a, led_17_grp_a, led_18_grp_a, led_19_grp_a, + led_20_grp_a, led_21_grp_a, led_22_grp_a, led_23_grp_a, + led_24_grp_a, led_25_grp_a, led_26_grp_a, led_27_grp_a, + led_28_grp_a, led_29_grp_a, led_30_grp_a, led_31_grp_a, + led_31_grp_b, hs_uart_grp, i2c_grp_a, i2c_grp_b, i2s_grp, + nand_ctrl_grp, nand_data_grp, emmc_ctrl_grp, usb0_pwr_grp, + usb1_pwr_grp ] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + pinctrl@ff800560 { + compatible = "brcm,bcm4908-pinctrl"; + reg = <0xff800560 0x10>; + + led_0-a-pins { + function = "led_0"; + groups = "led_0_grp_a"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml new file mode 100644 index 000000000000..66baa6082a4f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx93-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMX93 IOMUX Controller + +maintainers: + - Peng Fan <peng.fan@nxp.com> + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +allOf: + - $ref: "pinctrl.yaml#" + +properties: + compatible: + const: fsl,imx93-iomuxc + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg + mux_val input_val> are specified using a PIN_FUNC_ID macro, which can + be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last + integer CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MX8M Plus Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + # Pinmux controller node + - | + iomuxc: pinctrl@443c0000 { + compatible = "fsl,imx93-iomuxc"; + reg = <0x30330000 0x10000>; + + pinctrl_uart3: uart3grp { + fsl,pins = + <0x48 0x1f8 0x41c 0x1 0x0 0x49>, + <0x4c 0x1fc 0x418 0x1 0x0 0x49>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt index 0aff1f28495c..8146193bd8ac 100644 --- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt @@ -16,6 +16,7 @@ Required properties for the root node: "amlogic,meson-g12a-periphs-pinctrl" "amlogic,meson-g12a-aobus-pinctrl" "amlogic,meson-a1-periphs-pinctrl" + "amlogic,meson-s4-periphs-pinctrl" - reg: address and size of registers controlling irq functionality === GPIO sub-nodes === diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml index cb554084bdf1..0df4e114fdd6 100644 --- a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml @@ -145,7 +145,7 @@ examples: clocks = <&sys_clk>; pinctrl-0 = <&sgpio2_pins>; pinctrl-names = "default"; - reg = <0x1101059c 0x100>; + reg = <0x1101059c 0x118>; microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>; bus-frequency = <25000000>; sgpio_in2: gpio@0 { diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt index 3bb76487669f..5d84fd299ccf 100644 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt @@ -4,8 +4,8 @@ Microsemi Ocelot pin controller Device Tree Bindings Required properties: - compatible : Should be "mscc,ocelot-pinctrl", "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl", - "mscc,luton-pinctrl", "mscc,serval-pinctrl" or - "microchip,lan966x-pinctrl" + "mscc,luton-pinctrl", "mscc,serval-pinctrl", + "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl" - reg : Address and length of the register set for the device - gpio-controller : Indicates this device is a GPIO controller - #gpio-cells : Must be 2. diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml new file mode 100644 index 000000000000..47a56b83a610 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 pin control and GPIO + +maintainers: + - Jonathan Neuschäfer <j.neuschaefer@gmx.net> + +properties: + compatible: + const: nuvoton,wpcm450-pinctrl + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + # There are three kinds of subnodes: + # 1. a GPIO controller node for each GPIO bank + # 2. a pinmux node configures pin muxing for a group of pins (e.g. rmii2) + # 3. a pinconf node configures properties of a single pin + + "^gpio@[0-7]$": + type: object + + description: + Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18 + GPIOs. Some GPIOs support interrupts. + + properties: + reg: + minimum: 0 + maximum: 7 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: + maxItems: 3 + description: + The interrupts associated with this GPIO bank + + required: + - reg + - gpio-controller + - '#gpio-cells' + + "^mux-": + $ref: pinmux-node.yaml# + + properties: + groups: + description: + One or more groups of pins to mux to a certain function + items: + enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp, + hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo, + clko, smi, uinc, gspi, mben, xcs2, xcs1, sdio, sspi, fi0, + fi1, fi2, fi3, fi4, fi5, fi6, fi7, fi8, fi9, fi10, fi11, + fi12, fi13, fi14, fi15, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, + pwm6, pwm7, hg0, hg1, hg2, hg3, hg4, hg5, hg6, hg7 ] + function: + description: + The function that a group of pins is muxed to + enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp, + hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo0, + dvo1, dvo2, dvo3, dvo4, dvo5, dvo6, dvo7, clko, smi, uinc, + gspi, mben, xcs2, xcs1, sdio, sspi, fi0, fi1, fi2, fi3, fi4, + fi5, fi6, fi7, fi8, fi9, fi10, fi11, fi12, fi13, fi14, fi15, + pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, hg0, hg1, + hg2, hg3, hg4, hg5, hg6, hg7, gpio ] + + dependencies: + groups: [ function ] + function: [ groups ] + + additionalProperties: false + + "^cfg-": + $ref: pincfg-node.yaml# + + properties: + pins: + description: + A list of pins to configure in certain ways, such as enabling + debouncing + items: + pattern: "^gpio1?[0-9]{1,2}$" + + input-debounce: true + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/gpio/gpio.h> + pinctrl: pinctrl@b8003000 { + compatible = "nuvoton,wpcm450-pinctrl"; + reg = <0xb8003000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + gpio0: gpio@0 { + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, + <3 IRQ_TYPE_LEVEL_HIGH>, + <4 IRQ_TYPE_LEVEL_HIGH>; + }; + + mux-rmii2 { + groups = "rmii2"; + function = "rmii2"; + }; + + pinmux_uid: mux-uid { + groups = "gspi", "sspi"; + function = "gpio"; + }; + + pinctrl_uid: cfg-uid { + pins = "gpio14"; + input-debounce = <1>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uid>, <&pinmux_uid>; + + uid { + label = "UID"; + linux,code = <102>; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml new file mode 100644 index 000000000000..8a2bb8608291 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml @@ -0,0 +1,297 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8186.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8186 Pin Controller + +maintainers: + - Sean Wang <sean.wang@mediatek.com> + +description: | + The Mediatek's Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8186-pinctrl + + gpio-controller: true + + '#gpio-cells': + description: | + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + const: 2 + + gpio-ranges: + maxItems: 1 + + reg: + description: | + Physical address base for gpio base registers. There are 8 different GPIO + physical address base in mt8186. + maxItems: 8 + + reg-names: + description: | + Gpio base register names. + items: + - const: iocfg0 + - const: iocfg_bm + - const: iocfg_bl + - const: iocfg_br + - const: iocfg_lm + - const: iocfg_rb + - const: iocfg_tl + - const: eint + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + description: The interrupt outputs to sysirq + maxItems: 1 + + mediatek,rsel-resistance-in-si-unit: + type: boolean + description: | + Identifying i2c pins pull up/down type which is RSEL. It can support + RSEL define or si unit value(ohm) to set different resistance. + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + patternProperties: + '^pins': + type: object + additionalProperties: false + description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and + input schmitt. + An example of using macro: + pincontroller { + /* GPIO0 set as multifunction GPIO0 */ + gpio-pins { + pins { + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>; + } + }; + /* GPIO128 set as multifunction SDA0 */ + i2c0-pins { + pins { + pinmux = <PINMUX_GPIO128__FUNC_SDA0>; + } + }; + }; + $ref: "pinmux-node.yaml" + + properties: + pinmux: + description: | + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h + directly. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + mediatek,drive-strength-adv: + description: | + Describe the specific driving setup property. + For I2C pins, the existing generic driving setup can only support + 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they + can support 0.125/0.25/0.5/1mA adjustment. If we enable specific + driving setup, the existing generic setup will be disabled. + The specific driving setup is controlled by E1E0EN. + When E1=0/E0=0, the strength is 0.125mA. + When E1=0/E0=1, the strength is 0.25mA. + When E1=1/E0=0, the strength is 0.5mA. + When E1=1/E0=1, the strength is 1mA. + EN is used to enable or disable the specific driving setup. + Valid arguments are described as below: + 0: (E1, E0, EN) = (0, 0, 0) + 1: (E1, E0, EN) = (0, 0, 1) + 2: (E1, E0, EN) = (0, 1, 0) + 3: (E1, E0, EN) = (0, 1, 1) + 4: (E1, E0, EN) = (1, 0, 0) + 5: (E1, E0, EN) = (1, 0, 1) + 6: (E1, E0, EN) = (1, 1, 0) + 7: (E1, E0, EN) = (1, 1, 1) + So the valid arguments are from 0 to 7. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8186 pull down PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203] + description: mt8186 pull down RSEL type define value. + - enum: [75000, 5000] + description: mt8186 pull down RSEL type si unit value(ohm). + description: | + For pull down type is normal, it don't need add RSEL & R1R0 define + and resistance value. + For pull down type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8186. + For pull down type is RSEL, it can add RSEL define & resistance + value(ohm) to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" + & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" + define in mt8186. It can also support resistance value(ohm) + "75000" & "5000" in mt8186. + An example of using RSEL define: + pincontroller { + i2c0_pin { + pins { + pinmux = <PINMUX_GPIO128__FUNC_SDA0>; + bias-pull-down = <MTK_PULL_SET_RSEL_001>; + } + }; + }; + An example of using si unit resistance value(ohm): + &pio { + mediatek,rsel-resistance-in-si-unit; + } + pincontroller { + i2c0_pin { + pins { + pinmux = <PINMUX_GPIO128__FUNC_SDA0>; + bias-pull-down = <75000>; + } + }; + }; + + bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8186 pull up PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203] + description: mt8186 pull up RSEL type define value. + - enum: [1000, 5000, 10000, 75000] + description: mt8186 pull up RSEL type si unit value(ohm). + description: | + For pull up type is normal, it don't need add RSEL & R1R0 define + and resistance value. + For pull up type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8186. + For pull up type is RSEL, it can add RSEL define & resistance + value(ohm) to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" + & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" + define in mt8186. It can also support resistance value(ohm) + "1000" & "5000" & "10000" & "75000" in mt8186. + An example of using si unit resistance value(ohm): + &pio { + mediatek,rsel-resistance-in-si-unit; + } + pincontroller { + i2c0-pins { + pins { + pinmux = <PINMUX_GPIO128__FUNC_SDA0>; + bias-pull-up = <1000>; + } + }; + }; + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/mt8186-pinfunc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8186-pinctrl"; + reg = <0x10005000 0x1000>, + <0x10002000 0x0200>, + <0x10002200 0x0200>, + <0x10002400 0x0200>, + <0x10002600 0x0200>, + <0x10002A00 0x0200>, + <0x10002c00 0x0200>, + <0x1000b000 0x1000>; + reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", + "iocfg_br", "iocfg_lm", "iocfg_rb", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 185>; + interrupt-controller; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + + pio-pins { + pins { + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>; + output-low; + }; + }; + + spi0-pins { + pins-spi { + pinmux = <PINMUX_GPIO0__FUNC_SPI0_CLK_B>, + <PINMUX_GPIO1__FUNC_SPI0_CSB_B>, + <PINMUX_GPIO2__FUNC_SPI0_MO_B>; + bias-disable; + }; + pins-spi-mi { + pinmux = <PINMUX_GPIO3__FUNC_SPI0_MI_B>; + bias-pull-down; + }; + }; + + i2c0-pins { + pins { + pinmux = <PINMUX_GPIO127__FUNC_SCL0>, + <PINMUX_GPIO128__FUNC_SDA0>; + bias-pull-up = <MTK_PULL_SET_RSEL_001>; + mediatek,drive-strength-adv = <7>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml index 328ea59c5466..c5b755514c46 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml @@ -98,7 +98,41 @@ patternProperties: drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] + mediatek,drive-strength-adv: + description: | + Describe the specific driving setup property. + For I2C pins, the existing generic driving setup can only support + 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they + can support 0.125/0.25/0.5/1mA adjustment. If we enable specific + driving setup, the existing generic setup will be disabled. + The specific driving setup is controlled by E1E0EN. + When E1=0/E0=0, the strength is 0.125mA. + When E1=0/E0=1, the strength is 0.25mA. + When E1=1/E0=0, the strength is 0.5mA. + When E1=1/E0=1, the strength is 1mA. + EN is used to enable or disable the specific driving setup. + Valid arguments are described as below: + 0: (E1, E0, EN) = (0, 0, 0) + 1: (E1, E0, EN) = (0, 0, 1) + 2: (E1, E0, EN) = (0, 1, 0) + 3: (E1, E0, EN) = (0, 1, 1) + 4: (E1, E0, EN) = (1, 0, 0) + 5: (E1, E0, EN) = (1, 0, 1) + 6: (E1, E0, EN) = (1, 1, 0) + 7: (E1, E0, EN) = (1, 1, 1) + So the valid arguments are from 0 to 7. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8195 pull down PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + description: mt8195 pull down RSEL type define value. + - enum: [75000, 5000] + description: mt8195 pull down RSEL type si unit value(ohm). description: | For pull down type is normal, it don't need add RSEL & R1R0 define and resistance value. @@ -115,13 +149,6 @@ patternProperties: & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" define in mt8195. It can also support resistance value(ohm) "75000" & "5000" in mt8195. - oneOf: - - enum: [100, 101, 102, 103] - - description: mt8195 pull down PUPD/R0/R1 type define value. - - enum: [200, 201, 202, 203, 204, 205, 206, 207] - - description: mt8195 pull down RSEL type define value. - - enum: [75000, 5000] - - description: mt8195 pull down RSEL type si unit value(ohm). An example of using RSEL define: pincontroller { @@ -146,6 +173,14 @@ patternProperties: }; bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8195 pull up PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + description: mt8195 pull up RSEL type define value. + - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000] + description: mt8195 pull up RSEL type si unit value(ohm). description: | For pull up type is normal, it don't need add RSEL & R1R0 define and resistance value. @@ -163,13 +198,6 @@ patternProperties: define in mt8195. It can also support resistance value(ohm) "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" in mt8195. - oneOf: - - enum: [100, 101, 102, 103] - - description: mt8195 pull up PUPD/R0/R1 type define value. - - enum: [200, 201, 202, 203, 204, 205, 206, 207] - - description: mt8195 pull up RSEL type define value. - - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000] - - description: mt8195 pull up RSEL type si unit value(ohm). An example of using RSEL define: pincontroller { i2c0-pins { @@ -268,4 +296,13 @@ examples: bias-pull-down; }; }; + + i2c0-pins { + pins { + pinmux = <PINMUX_GPIO8__FUNC_SDA0>, + <PINMUX_GPIO9__FUNC_SCL0>; + bias-disable; + mediatek,drive-strength-adv = <7>; + }; + }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml index 64c0a41ca0c3..d4da558cde54 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml @@ -34,6 +34,8 @@ properties: gpio-controller: true + gpio-reserved-ranges: true + '#gpio-cells': description: Specifying the pin number and flags, as defined in include/dt-bindings/gpio/gpio.h diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index 9400b665a46f..fe2bcf0694d9 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -36,6 +36,7 @@ properties: - qcom,pm8350-gpio - qcom,pm8350b-gpio - qcom,pm8350c-gpio + - qcom,pm8450-gpio - qcom,pm8916-gpio - qcom,pm8917-gpio - qcom,pm8921-gpio diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml index 35c846f59979..df79274d0ec3 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml @@ -21,6 +21,7 @@ properties: - qcom,pm8019-mpp - qcom,pm8038-mpp - qcom,pm8058-mpp + - qcom,pm8226-mpp - qcom,pm8821-mpp - qcom,pm8841-mpp - qcom,pm8916-mpp diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml new file mode 100644 index 000000000000..87a381c9a19d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SC8280XP TLMM block + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + SC8280XP platform. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sc8280xp-tlmm + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + '#interrupt-cells': true + gpio-controller: true + gpio-reserved-ranges: true + '#gpio-cells': true + gpio-ranges: true + wakeup-parent: true + +required: + - compatible + - reg + +additionalProperties: false + +patternProperties: + '-state$': + oneOf: + - $ref: "#/$defs/qcom-sc8280xp-tlmm-state" + - patternProperties: + ".*": + $ref: "#/$defs/qcom-sc8280xp-tlmm-state" + +'$defs': + qcom-sc8280xp-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$" + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset, ufs1_reset ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9, + cmu_rng, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, + ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, + ddr_pxi6, ddr_pxi7, dp2_hot, dp3_hot, edp0_lcd, edp1_lcd, + edp2_lcd, edp3_lcd, edp_hot, emac0_dll, emac0_mcg0, emac0_mcg1, + emac0_mcg2, emac0_mcg3, emac0_phy, emac0_ptp, emac1_dll0, + emac1_dll1, emac1_mcg0, emac1_mcg1, emac1_mcg2, emac1_mcg3, + emac1_phy, emac1_ptp, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4, + gcc_gp5, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s, ibi_i3c, + jitter_bist, lpass_slimbus, mdp0_vsync0, mdp0_vsync1, + mdp0_vsync2, mdp0_vsync3, mdp0_vsync4, mdp0_vsync5, + mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, mdp1_vsync0, + mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4, + mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync, + mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s1_data0, + mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, mi2s2_data1, + mi2s2_sck, mi2s2_ws, mi2s_mclk1, mi2s_mclk2, pcie2a_clkreq, + pcie2b_clkreq, pcie3a_clkreq, pcie3b_clkreq, pcie4_clkreq, + phase_flag, pll_bist, pll_clk, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qspi, qspi_clk, + qspi_cs, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8, + qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17, + qup18, qup19, qup20, qup21, qup22, qup23, rgmii_0, rgmii_1, + sd_write, sdc40, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig, + tgu, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, + usb0_dp, usb0_phy, usb0_sbrx, usb0_sbtx, usb0_usb4, usb1_dp, + usb1_phy, usb1_sbrx, usb1_sbtx, usb1_usb4, usb2phy_ac, + vsense_trigger ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + - function + + additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@f100000 { + compatible = "qcom,sc8280xp-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 230>; + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx { + pins = "gpio4"; + function = "qup14"; + bias-pull-up; + }; + + tx { + pins = "gpio5"; + function = "qup14"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml index be8cb0ead62f..780f15bb5e40 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml @@ -73,7 +73,6 @@ $defs: properties: drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] - default: 2 description: Selects the drive strength for the specified pins, in mA. diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml index f0c52feb24d7..9de8b0c075e2 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml @@ -10,7 +10,7 @@ maintainers: - Sergio Paracuellos <sergio.paracuellos@gmail.com> description: - The rt2880 pinmux can only set the muxing of pin groups. muxing indiviual pins + The rt2880 pinmux can only set the muxing of pin groups. Muxing indiviual pins is not supported. There is no pinconf support. properties: @@ -29,12 +29,13 @@ patternProperties: properties: groups: description: Name of the pin group to use for the functions. - enum: [i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2, mdio, - pcie, sdhci] + enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi, + uart1, uart2, uart3, wdt] function: description: The mux function to select - enum: [gpio, i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2, - mdio, nand1, nand2, sdhci] + enum: [gpio, i2c, i2s, jtag, mdio, nand1, nand2, pcie refclk, + pcie rst, pcm, rgmii1, rgmii2, sdhci, spdif2, spdif3, + spi, uart1, uart2, uart3, wdt refclk, wdt rst] required: - groups diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml index 8548e3639b75..2a57df75d832 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml @@ -44,6 +44,7 @@ properties: - renesas,pfc-r8a77990 # R-Car E3 - renesas,pfc-r8a77995 # R-Car D3 - renesas,pfc-r8a779a0 # R-Car V3U + - renesas,pfc-r8a779f0 # R-Car S4-8 - renesas,pfc-sh73a0 # SH-Mobile AG5 reg: diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index b749c82edebd..9ccf54870aa4 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/G2L combined Pin and GPIO controller +title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller maintainers: - Geert Uytterhoeven <geert+renesas@glider.be> - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> description: - The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO + The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO controller. Pin multiplexing and GPIO configuration is performed on a per-pin basis. Each port features up to 8 pins, each of them configurable for GPIO function @@ -20,8 +20,15 @@ description: properties: compatible: - enum: - - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} + oneOf: + - items: + - enum: + - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} + + - items: + - enum: + - renesas,r9a07g054-pinctrl # RZ/V2L + - const: renesas,r9a07g044-pinctrl # RZ/G2{L,LC} fallback for RZ/V2L reg: maxItems: 1 @@ -76,6 +83,7 @@ additionalProperties: output-impedance-ohms: enum: [ 33, 50, 66, 100 ] power-source: + description: I/O voltage in millivolt. enum: [ 1800, 2500, 3300 ] slew-rate: true gpio-hog: true diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index 28f0851d07bb..989e48c051cf 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -56,6 +56,7 @@ properties: - samsung,exynos7885-pinctrl - samsung,exynos850-pinctrl - samsung,exynosautov9-pinctrl + - tesla,fsd-pinctrl interrupts: description: diff --git a/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml new file mode 100644 index 000000000000..d8e75b3e64f1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml @@ -0,0 +1,374 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 Pin Controller Device Tree Bindings + +maintainers: + - Dvorkin Dmitry <dvorkin@tibbo.com> + - Wells Lu <wellslutw@gmail.com> + +description: | + The Sunplus SP7021 pin controller is used to control SoC pins. Please + refer to pinctrl-bindings.txt in this directory for details of the common + pinctrl bindings used by client devices. + + SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All + are multiplexed with some special function pins. SP7021 has 3 types of + special function pins: + + (1) function-group pins: + Ex 1 (SPI-NOR flash): + If control-field SPI_FLASH_SEL is set to 1, GPIO 83, 84, 86 and 87 + will be pins of SPI-NOR flash. If it is set to 2, GPIO 76, 78, 79 + and 81 will be pins of SPI-NOR flash. + + Ex 2 (UART_0): + If control-bit UA0_SEL is set to 1, GPIO 88 and 89 will be TX and + RX pins of UART_0 (UART channel 0). + + Ex 3 (eMMC): + If control-bit EMMC_SEL is set to 1, GPIO 72, 73, 74, 75, 76, 77, + 78, 79, 80, 81 will be pins of an eMMC device. + + Properties "function" and "groups" are used to select function-group + pins. + + (2) fully pin-mux (like phone exchange mux) pins: + GPIO 8 to 71 are 'fully pin-mux' pins. Any pins of peripherals of + SP7021 (ex: UART_1, UART_2, UART_3, UART_4, I2C_0, I2C_1, and etc.) + can be routed to any pins of fully pin-mux pins. + + Ex 1 (UART channel 1): + If control-field UA1_TX_SEL is set to 3, TX pin of UART_1 will be + routed to GPIO 10 (3 - 1 + 8 = 10). + If control-field UA1_RX_SEL is set to 4, RX pin of UART_1 will be + routed to GPIO 11 (4 - 1 + 8 = 11). + If control-field UA1_RTS_SEL is set to 5, RTS pin of UART_1 will + be routed to GPIO 12 (5 - 1 + 8 = 12). + If control-field UA1_CTS_SEL is set to 6, CTS pin of UART_1 will + be routed to GPIO 13 (6 - 1 + 8 = 13). + + Ex 2 (I2C channel 0): + If control-field I2C0_CLK_SEL is set to 20, CLK pin of I2C_0 will + be routed to GPIO 27 (20 - 1 + 8 = 27). + If control-field I2C0_DATA_SEL is set to 21, DATA pin of I2C_0 + will be routed to GPIO 28 (21 - 1 + 9 = 28). + + Totally, SP7021 has 120 peripheral pins. The peripheral pins can be + routed to any of 64 'fully pin-mux' pins. + + (3) I/O processor pins + SP7021 has a built-in I/O processor. + Any GPIO pins (GPIO 0 to 98) can be set to pins of I/O processor. + + Vendor property "sunplus,pins" is used to select "fully pin-mux" pins, + "I/O processor pins" and "digital GPIO" pins. + + The device node of pin controller of Sunplus SP7021 has following + properties. + +properties: + compatible: + const: sunplus,sp7021-pctl + + gpio-controller: true + + '#gpio-cells': + const: 2 + + reg: + items: + - description: the MOON2 registers + - description: the GPIOXT registers + - description: the FIRST registers + - description: the MOON1 registers + + reg-names: + items: + - const: moon2 + - const: gpioxt + - const: first + - const: moon1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnodes representing the + pins or function-pins group available on the machine. Each subnode + will list the pins it needs, and how they should be configured. + + Pinctrl node's client devices use subnodes for desired pin + configuration. Client device subnodes use below standard properties. + $ref: pinmux-node.yaml# + + properties: + sunplus,pins: + description: | + Define 'sunplus,pins' which are used by pinctrl node's client + device. + + It consists of one or more integers which represents the config + setting for corresponding pin. Each integer defines a individual + pin in which: + + Bit 32~24: defines GPIO number. Its range is 0 ~ 98. + Bit 23~16: defines types: (1) fully pin-mux pins + (2) IO processor pins + (3) digital GPIO pins + Bit 15~8: defines pins of peripherals (which are defined in + 'include/dt-binging/pinctrl/sppctl.h'). + Bit 7~0: defines types or initial-state of digital GPIO pins. + + Please use macro SPPCTL_IOPAD to define the integers for pins. + + $ref: /schemas/types.yaml#/definitions/uint32-array + + function: + description: | + Define pin-function which is used by pinctrl node's client device. + The name should be one of string in the following enumeration. + $ref: "/schemas/types.yaml#/definitions/string" + enum: [ SPI_FLASH, SPI_FLASH_4BIT, SPI_NAND, CARD0_EMMC, SD_CARD, + UA0, FPGA_IFX, HDMI_TX, LCDIF, USB0_OTG, USB1_OTG ] + + groups: + description: | + Define pin-group in a specified pin-function. + The name should be one of string in the following enumeration. + $ref: "/schemas/types.yaml#/definitions/string" + enum: [ SPI_FLASH1, SPI_FLASH2, SPI_FLASH_4BIT1, SPI_FLASH_4BIT2, + SPI_NAND, CARD0_EMMC, SD_CARD, UA0, FPGA_IFX, HDMI_TX1, + HDMI_TX2, HDMI_TX3, LCDIF, USB0_OTG, USB1_OTG ] + + sunplus,zerofunc: + description: | + This is a vendor specific property. It is used to disable pins + which are not used by pinctrl node's client device. + Some pins may be enabled by boot-loader. We can use this + property to disable them. + $ref: /schemas/types.yaml#/definitions/uint32-array + + additionalProperties: false + + allOf: + - if: + properties: + function: + enum: + - SPI_FLASH + then: + properties: + groups: + enum: + - SPI_FLASH1 + - SPI_FLASH2 + - if: + properties: + function: + enum: + - SPI_FLASH_4BIT + then: + properties: + groups: + enum: + - SPI_FLASH_4BIT1 + - SPI_FLASH_4BIT2 + - if: + properties: + function: + enum: + - SPI_NAND + then: + properties: + groups: + enum: + - SPI_NAND + - if: + properties: + function: + enum: + - CARD0_EMMC + then: + properties: + groups: + enum: + - CARD0_EMMC + - if: + properties: + function: + enum: + - SD_CARD + then: + properties: + groups: + enum: + - SD_CARD + - if: + properties: + function: + enum: + - UA0 + then: + properties: + groups: + enum: + - UA0 + - if: + properties: + function: + enum: + - FPGA_IFX + then: + properties: + groups: + enum: + - FPGA_IFX + - if: + properties: + function: + enum: + - HDMI_TX + then: + properties: + groups: + enum: + - HDMI_TX1 + - HDMI_TX2 + - HDMI_TX3 + - if: + properties: + function: + enum: + - LCDIF + then: + properties: + groups: + enum: + - LCDIF + - if: + properties: + function: + enum: + - USB0_OTG + then: + properties: + groups: + enum: + - USB0_OTG + - if: + properties: + function: + enum: + - USB1_OTG + then: + properties: + groups: + enum: + - USB1_OTG + +required: + - compatible + - reg + - reg-names + - "#gpio-cells" + - gpio-controller + - clocks + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/sppctl-sp7021.h> + + pinctl@9c000100 { + compatible = "sunplus,sp7021-pctl"; + reg = <0x9c000100 0x100>, <0x9c000300 0x100>, + <0x9c0032e4 0x1c>, <0x9c000080 0x20>; + reg-names = "moon2", "gpioxt", "first", "moon1"; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clkc 0x83>; + resets = <&rstc 0x73>; + + uart0-pins { + function = "UA0"; + groups = "UA0"; + }; + + spinand0-pins { + function = "SPI_NAND"; + groups = "SPI_NAND"; + }; + + uart1-pins { + sunplus,pins = < + SPPCTL_IOPAD(11, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0) + SPPCTL_IOPAD(10, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0) + >; + }; + + uart2-pins { + sunplus,pins = < + SPPCTL_IOPAD(20, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0) + SPPCTL_IOPAD(21, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0) + SPPCTL_IOPAD(22, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RTS, 0) + SPPCTL_IOPAD(23, SPPCTL_PCTL_G_PMUX, MUXF_UA1_CTS, 0) + >; + }; + + emmc-pins { + function = "CARD0_EMMC"; + groups = "CARD0_EMMC"; + }; + + sdcard-pins { + function = "SD_CARD"; + groups = "SD_CARD"; + sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >; + }; + + hdmi_A_tx1-pins { + function = "HDMI_TX"; + groups = "HDMI_TX1"; + }; + hdmi_A_tx2-pins { + function = "HDMI_TX"; + groups = "HDMI_TX2"; + }; + hdmi_A_tx3-pins { + function = "HDMI_TX"; + groups = "HDMI_TX3"; + }; + + ethernet-pins { + sunplus,pins = < + SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0) + SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0) + SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0) + SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0) + SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0) + SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0) + SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0) + SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0) + SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0) + >; + sunplus,zerofunc = < + MUXF_L2SW_LED_FLASH0 + MUXF_L2SW_LED_ON0 + MUXF_L2SW_P0_MAC_RMII_RXER + >; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index b555a5e8704f..5debe27f4f23 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2383,6 +2383,7 @@ W: https://github.com/neuschaefer/wpcm450/wiki F: Documentation/devicetree/bindings/*/*wpcm* F: arch/arm/boot/dts/nuvoton-wpcm450* F: arch/arm/mach-npcm/wpcm450.c +F: drivers/*/*/*wpcm* F: drivers/*/*wpcm* ARM/NXP S32G ARCHITECTURE @@ -3716,6 +3717,14 @@ F: Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml F: drivers/net/ethernet/broadcom/bcm4908_enet.* F: drivers/net/ethernet/broadcom/unimac.h +BROADCOM BCM4908 PINMUX DRIVER +M: RafaÅ‚ MiÅ‚ecki <rafal@milecki.pl> +M: bcm-kernel-feedback-list@broadcom.com +L: linux-gpio@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml +F: drivers/pinctrl/bcm/pinctrl-bcm4908.c + BROADCOM BCM5301X ARM ARCHITECTURE M: Florian Fainelli <f.fainelli@gmail.com> M: Hauke Mehrtens <hauke@hauke-m.de> @@ -15478,6 +15487,16 @@ M: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> S: Supported F: drivers/pinctrl/pinctrl-thunderbay.c +PIN CONTROLLER - SUNPLUS / TIBBO +M: Dvorkin Dmitry <dvorkin@tibbo.com> +M: Wells Lu <wellslutw@gmail.com> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +W: https://sunplus.atlassian.net/wiki/spaces/doc/overview +F: Documentation/devicetree/bindings/pinctrl/sunplus,* +F: drivers/pinctrl/sunplus/ +F: include/dt-bindings/pinctrl/sppctl*.h + PKTCDVD DRIVER M: linux-block@vger.kernel.org S: Orphan diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 6fc56d6598e2..f52960d2dfbe 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -527,6 +527,7 @@ source "drivers/pinctrl/samsung/Kconfig" source "drivers/pinctrl/spear/Kconfig" source "drivers/pinctrl/sprd/Kconfig" source "drivers/pinctrl/stm32/Kconfig" +source "drivers/pinctrl/sunplus/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" source "drivers/pinctrl/tegra/Kconfig" source "drivers/pinctrl/ti/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index f64d29f614ec..e76f5cdc64b0 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -62,7 +62,7 @@ obj-y += mediatek/ obj-$(CONFIG_PINCTRL_MESON) += meson/ obj-y += mvebu/ obj-y += nomadik/ -obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/ +obj-y += nuvoton/ obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_PINCTRL_RALINK) += ralink/ @@ -71,6 +71,7 @@ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-$(CONFIG_PINCTRL_SPEAR) += spear/ obj-y += sprd/ obj-$(CONFIG_PINCTRL_STM32) += stm32/ +obj-y += sunplus/ obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig index ac1e400bbbac..8f4d89806fcb 100644 --- a/drivers/pinctrl/bcm/Kconfig +++ b/drivers/pinctrl/bcm/Kconfig @@ -29,6 +29,20 @@ config PINCTRL_BCM2835 help Say Y here to enable the Broadcom BCM2835 GPIO driver. +config PINCTRL_BCM4908 + tristate "Broadcom BCM4908 pinmux driver" + depends on OF && (ARCH_BCM4908 || COMPILE_TEST) + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + default ARCH_BCM4908 + help + Driver for BCM4908 family SoCs with integrated pin controller. + + If compiled as module it will be called pinctrl-bcm4908. + config PINCTRL_BCM63XX bool select PINMUX diff --git a/drivers/pinctrl/bcm/Makefile b/drivers/pinctrl/bcm/Makefile index 00c7b7775e63..82b868ec1471 100644 --- a/drivers/pinctrl/bcm/Makefile +++ b/drivers/pinctrl/bcm/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o +obj-$(CONFIG_PINCTRL_BCM4908) += pinctrl-bcm4908.o obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o obj-$(CONFIG_PINCTRL_BCM6318) += pinctrl-bcm6318.o obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o diff --git a/drivers/pinctrl/bcm/pinctrl-bcm4908.c b/drivers/pinctrl/bcm/pinctrl-bcm4908.c new file mode 100644 index 000000000000..cdfa165fc033 --- /dev/null +++ b/drivers/pinctrl/bcm/pinctrl-bcm4908.c @@ -0,0 +1,563 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2021 RafaÅ‚ MiÅ‚ecki <rafal@milecki.pl> */ + +#include <linux/err.h> +#include <linux/io.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/string_helpers.h> + +#include "../core.h" +#include "../pinmux.h" + +#define BCM4908_NUM_PINS 86 + +#define BCM4908_TEST_PORT_BLOCK_EN_LSB 0x00 +#define BCM4908_TEST_PORT_BLOCK_DATA_MSB 0x04 +#define BCM4908_TEST_PORT_BLOCK_DATA_LSB 0x08 +#define BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT 12 +#define BCM4908_TEST_PORT_COMMAND 0x0c +#define BCM4908_TEST_PORT_CMD_LOAD_MUX_REG 0x00000021 + +struct bcm4908_pinctrl { + struct device *dev; + void __iomem *base; + struct mutex mutex; + struct pinctrl_dev *pctldev; + struct pinctrl_desc pctldesc; +}; + +/* + * Groups + */ + +struct bcm4908_pinctrl_pin_setup { + unsigned int number; + unsigned int function; +}; + +static const struct bcm4908_pinctrl_pin_setup led_0_pins_a[] = { + { 0, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_1_pins_a[] = { + { 1, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_2_pins_a[] = { + { 2, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_3_pins_a[] = { + { 3, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_4_pins_a[] = { + { 4, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_5_pins_a[] = { + { 5, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_6_pins_a[] = { + { 6, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_7_pins_a[] = { + { 7, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_8_pins_a[] = { + { 8, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_9_pins_a[] = { + { 9, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_10_pins_a[] = { + { 10, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_11_pins_a[] = { + { 11, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_12_pins_a[] = { + { 12, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_13_pins_a[] = { + { 13, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_14_pins_a[] = { + { 14, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_15_pins_a[] = { + { 15, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_16_pins_a[] = { + { 16, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_17_pins_a[] = { + { 17, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_18_pins_a[] = { + { 18, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_19_pins_a[] = { + { 19, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_20_pins_a[] = { + { 20, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_21_pins_a[] = { + { 21, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_22_pins_a[] = { + { 22, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_23_pins_a[] = { + { 23, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_24_pins_a[] = { + { 24, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_25_pins_a[] = { + { 25, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_26_pins_a[] = { + { 26, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_27_pins_a[] = { + { 27, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_28_pins_a[] = { + { 28, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_29_pins_a[] = { + { 29, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_30_pins_a[] = { + { 30, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_31_pins_a[] = { + { 31, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_10_pins_b[] = { + { 8, 2 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_11_pins_b[] = { + { 9, 2 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_12_pins_b[] = { + { 0, 2 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_13_pins_b[] = { + { 1, 2 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_31_pins_b[] = { + { 30, 2 }, +}; + +static const struct bcm4908_pinctrl_pin_setup hs_uart_pins[] = { + { 10, 0 }, /* CTS */ + { 11, 0 }, /* RTS */ + { 12, 0 }, /* RXD */ + { 13, 0 }, /* TXD */ +}; + +static const struct bcm4908_pinctrl_pin_setup i2c_pins_a[] = { + { 18, 0 }, /* SDA */ + { 19, 0 }, /* SCL */ +}; + +static const struct bcm4908_pinctrl_pin_setup i2c_pins_b[] = { + { 22, 0 }, /* SDA */ + { 23, 0 }, /* SCL */ +}; + +static const struct bcm4908_pinctrl_pin_setup i2s_pins[] = { + { 27, 0 }, /* MCLK */ + { 28, 0 }, /* LRCK */ + { 29, 0 }, /* SDATA */ + { 30, 0 }, /* SCLK */ +}; + +static const struct bcm4908_pinctrl_pin_setup nand_ctrl_pins[] = { + { 32, 0 }, + { 33, 0 }, + { 34, 0 }, + { 43, 0 }, + { 44, 0 }, + { 45, 0 }, + { 56, 1 }, +}; + +static const struct bcm4908_pinctrl_pin_setup nand_data_pins[] = { + { 35, 0 }, + { 36, 0 }, + { 37, 0 }, + { 38, 0 }, + { 39, 0 }, + { 40, 0 }, + { 41, 0 }, + { 42, 0 }, +}; + +static const struct bcm4908_pinctrl_pin_setup emmc_ctrl_pins[] = { + { 46, 0 }, + { 47, 0 }, +}; + +static const struct bcm4908_pinctrl_pin_setup usb0_pwr_pins[] = { + { 63, 0 }, + { 64, 0 }, +}; + +static const struct bcm4908_pinctrl_pin_setup usb1_pwr_pins[] = { + { 66, 0 }, + { 67, 0 }, +}; + +struct bcm4908_pinctrl_grp { + const char *name; + const struct bcm4908_pinctrl_pin_setup *pins; + const unsigned int num_pins; +}; + +static const struct bcm4908_pinctrl_grp bcm4908_pinctrl_grps[] = { + { "led_0_grp_a", led_0_pins_a, ARRAY_SIZE(led_0_pins_a) }, + { "led_1_grp_a", led_1_pins_a, ARRAY_SIZE(led_1_pins_a) }, + { "led_2_grp_a", led_2_pins_a, ARRAY_SIZE(led_2_pins_a) }, + { "led_3_grp_a", led_3_pins_a, ARRAY_SIZE(led_3_pins_a) }, + { "led_4_grp_a", led_4_pins_a, ARRAY_SIZE(led_4_pins_a) }, + { "led_5_grp_a", led_5_pins_a, ARRAY_SIZE(led_5_pins_a) }, + { "led_6_grp_a", led_6_pins_a, ARRAY_SIZE(led_6_pins_a) }, + { "led_7_grp_a", led_7_pins_a, ARRAY_SIZE(led_7_pins_a) }, + { "led_8_grp_a", led_8_pins_a, ARRAY_SIZE(led_8_pins_a) }, + { "led_9_grp_a", led_9_pins_a, ARRAY_SIZE(led_9_pins_a) }, + { "led_10_grp_a", led_10_pins_a, ARRAY_SIZE(led_10_pins_a) }, + { "led_11_grp_a", led_11_pins_a, ARRAY_SIZE(led_11_pins_a) }, + { "led_12_grp_a", led_12_pins_a, ARRAY_SIZE(led_12_pins_a) }, + { "led_13_grp_a", led_13_pins_a, ARRAY_SIZE(led_13_pins_a) }, + { "led_14_grp_a", led_14_pins_a, ARRAY_SIZE(led_14_pins_a) }, + { "led_15_grp_a", led_15_pins_a, ARRAY_SIZE(led_15_pins_a) }, + { "led_16_grp_a", led_16_pins_a, ARRAY_SIZE(led_16_pins_a) }, + { "led_17_grp_a", led_17_pins_a, ARRAY_SIZE(led_17_pins_a) }, + { "led_18_grp_a", led_18_pins_a, ARRAY_SIZE(led_18_pins_a) }, + { "led_19_grp_a", led_19_pins_a, ARRAY_SIZE(led_19_pins_a) }, + { "led_20_grp_a", led_20_pins_a, ARRAY_SIZE(led_20_pins_a) }, + { "led_21_grp_a", led_21_pins_a, ARRAY_SIZE(led_21_pins_a) }, + { "led_22_grp_a", led_22_pins_a, ARRAY_SIZE(led_22_pins_a) }, + { "led_23_grp_a", led_23_pins_a, ARRAY_SIZE(led_23_pins_a) }, + { "led_24_grp_a", led_24_pins_a, ARRAY_SIZE(led_24_pins_a) }, + { "led_25_grp_a", led_25_pins_a, ARRAY_SIZE(led_25_pins_a) }, + { "led_26_grp_a", led_26_pins_a, ARRAY_SIZE(led_26_pins_a) }, + { "led_27_grp_a", led_27_pins_a, ARRAY_SIZE(led_27_pins_a) }, + { "led_28_grp_a", led_28_pins_a, ARRAY_SIZE(led_28_pins_a) }, + { "led_29_grp_a", led_29_pins_a, ARRAY_SIZE(led_29_pins_a) }, + { "led_30_grp_a", led_30_pins_a, ARRAY_SIZE(led_30_pins_a) }, + { "led_31_grp_a", led_31_pins_a, ARRAY_SIZE(led_31_pins_a) }, + { "led_10_grp_b", led_10_pins_b, ARRAY_SIZE(led_10_pins_b) }, + { "led_11_grp_b", led_11_pins_b, ARRAY_SIZE(led_11_pins_b) }, + { "led_12_grp_b", led_12_pins_b, ARRAY_SIZE(led_12_pins_b) }, + { "led_13_grp_b", led_13_pins_b, ARRAY_SIZE(led_13_pins_b) }, + { "led_31_grp_b", led_31_pins_b, ARRAY_SIZE(led_31_pins_b) }, + { "hs_uart_grp", hs_uart_pins, ARRAY_SIZE(hs_uart_pins) }, + { "i2c_grp_a", i2c_pins_a, ARRAY_SIZE(i2c_pins_a) }, + { "i2c_grp_b", i2c_pins_b, ARRAY_SIZE(i2c_pins_b) }, + { "i2s_grp", i2s_pins, ARRAY_SIZE(i2s_pins) }, + { "nand_ctrl_grp", nand_ctrl_pins, ARRAY_SIZE(nand_ctrl_pins) }, + { "nand_data_grp", nand_data_pins, ARRAY_SIZE(nand_data_pins) }, + { "emmc_ctrl_grp", emmc_ctrl_pins, ARRAY_SIZE(emmc_ctrl_pins) }, + { "usb0_pwr_grp", usb0_pwr_pins, ARRAY_SIZE(usb0_pwr_pins) }, + { "usb1_pwr_grp", usb1_pwr_pins, ARRAY_SIZE(usb1_pwr_pins) }, +}; + +/* + * Functions + */ + +struct bcm4908_pinctrl_function { + const char *name; + const char * const *groups; + const unsigned int num_groups; +}; + +static const char * const led_0_groups[] = { "led_0_grp_a" }; +static const char * const led_1_groups[] = { "led_1_grp_a" }; +static const char * const led_2_groups[] = { "led_2_grp_a" }; +static const char * const led_3_groups[] = { "led_3_grp_a" }; +static const char * const led_4_groups[] = { "led_4_grp_a" }; +static const char * const led_5_groups[] = { "led_5_grp_a" }; +static const char * const led_6_groups[] = { "led_6_grp_a" }; +static const char * const led_7_groups[] = { "led_7_grp_a" }; +static const char * const led_8_groups[] = { "led_8_grp_a" }; +static const char * const led_9_groups[] = { "led_9_grp_a" }; +static const char * const led_10_groups[] = { "led_10_grp_a", "led_10_grp_b" }; +static const char * const led_11_groups[] = { "led_11_grp_a", "led_11_grp_b" }; +static const char * const led_12_groups[] = { "led_12_grp_a", "led_12_grp_b" }; +static const char * const led_13_groups[] = { "led_13_grp_a", "led_13_grp_b" }; +static const char * const led_14_groups[] = { "led_14_grp_a" }; +static const char * const led_15_groups[] = { "led_15_grp_a" }; +static const char * const led_16_groups[] = { "led_16_grp_a" }; +static const char * const led_17_groups[] = { "led_17_grp_a" }; +static const char * const led_18_groups[] = { "led_18_grp_a" }; +static const char * const led_19_groups[] = { "led_19_grp_a" }; +static const char * const led_20_groups[] = { "led_20_grp_a" }; +static const char * const led_21_groups[] = { "led_21_grp_a" }; +static const char * const led_22_groups[] = { "led_22_grp_a" }; +static const char * const led_23_groups[] = { "led_23_grp_a" }; +static const char * const led_24_groups[] = { "led_24_grp_a" }; +static const char * const led_25_groups[] = { "led_25_grp_a" }; +static const char * const led_26_groups[] = { "led_26_grp_a" }; +static const char * const led_27_groups[] = { "led_27_grp_a" }; +static const char * const led_28_groups[] = { "led_28_grp_a" }; +static const char * const led_29_groups[] = { "led_29_grp_a" }; +static const char * const led_30_groups[] = { "led_30_grp_a" }; +static const char * const led_31_groups[] = { "led_31_grp_a", "led_31_grp_b" }; +static const char * const hs_uart_groups[] = { "hs_uart_grp" }; +static const char * const i2c_groups[] = { "i2c_grp_a", "i2c_grp_b" }; +static const char * const i2s_groups[] = { "i2s_grp" }; +static const char * const nand_ctrl_groups[] = { "nand_ctrl_grp" }; +static const char * const nand_data_groups[] = { "nand_data_grp" }; +static const char * const emmc_ctrl_groups[] = { "emmc_ctrl_grp" }; +static const char * const usb0_pwr_groups[] = { "usb0_pwr_grp" }; +static const char * const usb1_pwr_groups[] = { "usb1_pwr_grp" }; + +static const struct bcm4908_pinctrl_function bcm4908_pinctrl_functions[] = { + { "led_0", led_0_groups, ARRAY_SIZE(led_0_groups) }, + { "led_1", led_1_groups, ARRAY_SIZE(led_1_groups) }, + { "led_2", led_2_groups, ARRAY_SIZE(led_2_groups) }, + { "led_3", led_3_groups, ARRAY_SIZE(led_3_groups) }, + { "led_4", led_4_groups, ARRAY_SIZE(led_4_groups) }, + { "led_5", led_5_groups, ARRAY_SIZE(led_5_groups) }, + { "led_6", led_6_groups, ARRAY_SIZE(led_6_groups) }, + { "led_7", led_7_groups, ARRAY_SIZE(led_7_groups) }, + { "led_8", led_8_groups, ARRAY_SIZE(led_8_groups) }, + { "led_9", led_9_groups, ARRAY_SIZE(led_9_groups) }, + { "led_10", led_10_groups, ARRAY_SIZE(led_10_groups) }, + { "led_11", led_11_groups, ARRAY_SIZE(led_11_groups) }, + { "led_12", led_12_groups, ARRAY_SIZE(led_12_groups) }, + { "led_13", led_13_groups, ARRAY_SIZE(led_13_groups) }, + { "led_14", led_14_groups, ARRAY_SIZE(led_14_groups) }, + { "led_15", led_15_groups, ARRAY_SIZE(led_15_groups) }, + { "led_16", led_16_groups, ARRAY_SIZE(led_16_groups) }, + { "led_17", led_17_groups, ARRAY_SIZE(led_17_groups) }, + { "led_18", led_18_groups, ARRAY_SIZE(led_18_groups) }, + { "led_19", led_19_groups, ARRAY_SIZE(led_19_groups) }, + { "led_20", led_20_groups, ARRAY_SIZE(led_20_groups) }, + { "led_21", led_21_groups, ARRAY_SIZE(led_21_groups) }, + { "led_22", led_22_groups, ARRAY_SIZE(led_22_groups) }, + { "led_23", led_23_groups, ARRAY_SIZE(led_23_groups) }, + { "led_24", led_24_groups, ARRAY_SIZE(led_24_groups) }, + { "led_25", led_25_groups, ARRAY_SIZE(led_25_groups) }, + { "led_26", led_26_groups, ARRAY_SIZE(led_26_groups) }, + { "led_27", led_27_groups, ARRAY_SIZE(led_27_groups) }, + { "led_28", led_28_groups, ARRAY_SIZE(led_28_groups) }, + { "led_29", led_29_groups, ARRAY_SIZE(led_29_groups) }, + { "led_30", led_30_groups, ARRAY_SIZE(led_30_groups) }, + { "led_31", led_31_groups, ARRAY_SIZE(led_31_groups) }, + { "hs_uart", hs_uart_groups, ARRAY_SIZE(hs_uart_groups) }, + { "i2c", i2c_groups, ARRAY_SIZE(i2c_groups) }, + { "i2s", i2s_groups, ARRAY_SIZE(i2s_groups) }, + { "nand_ctrl", nand_ctrl_groups, ARRAY_SIZE(nand_ctrl_groups) }, + { "nand_data", nand_data_groups, ARRAY_SIZE(nand_data_groups) }, + { "emmc_ctrl", emmc_ctrl_groups, ARRAY_SIZE(emmc_ctrl_groups) }, + { "usb0_pwr", usb0_pwr_groups, ARRAY_SIZE(usb0_pwr_groups) }, + { "usb1_pwr", usb1_pwr_groups, ARRAY_SIZE(usb1_pwr_groups) }, +}; + +/* + * Groups code + */ + +static const struct pinctrl_ops bcm4908_pinctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +/* + * Functions code + */ + +static int bcm4908_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev, + unsigned int func_selector, + unsigned int group_selector) +{ + struct bcm4908_pinctrl *bcm4908_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + const struct bcm4908_pinctrl_grp *group; + struct group_desc *group_desc; + int i; + + group_desc = pinctrl_generic_get_group(pctrl_dev, group_selector); + if (!group_desc) + return -EINVAL; + group = group_desc->data; + + mutex_lock(&bcm4908_pinctrl->mutex); + for (i = 0; i < group->num_pins; i++) { + u32 lsb = 0; + + lsb |= group->pins[i].number; + lsb |= group->pins[i].function << BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT; + + writel(0x0, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_MSB); + writel(lsb, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_LSB); + writel(BCM4908_TEST_PORT_CMD_LOAD_MUX_REG, + bcm4908_pinctrl->base + BCM4908_TEST_PORT_COMMAND); + } + mutex_unlock(&bcm4908_pinctrl->mutex); + + return 0; +} + +static const struct pinmux_ops bcm4908_pinctrl_pmxops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = bcm4908_pinctrl_set_mux, +}; + +/* + * Controller code + */ + +static struct pinctrl_desc bcm4908_pinctrl_desc = { + .name = "bcm4908-pinctrl", + .pctlops = &bcm4908_pinctrl_ops, + .pmxops = &bcm4908_pinctrl_pmxops, +}; + +static const struct of_device_id bcm4908_pinctrl_of_match_table[] = { + { .compatible = "brcm,bcm4908-pinctrl", }, + { } +}; + +static int bcm4908_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct bcm4908_pinctrl *bcm4908_pinctrl; + struct pinctrl_desc *pctldesc; + struct pinctrl_pin_desc *pins; + char **pin_names; + int i; + + bcm4908_pinctrl = devm_kzalloc(dev, sizeof(*bcm4908_pinctrl), GFP_KERNEL); + if (!bcm4908_pinctrl) + return -ENOMEM; + pctldesc = &bcm4908_pinctrl->pctldesc; + platform_set_drvdata(pdev, bcm4908_pinctrl); + + /* Set basic properties */ + + bcm4908_pinctrl->dev = dev; + + bcm4908_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(bcm4908_pinctrl->base)) + return PTR_ERR(bcm4908_pinctrl->base); + + mutex_init(&bcm4908_pinctrl->mutex); + + memcpy(pctldesc, &bcm4908_pinctrl_desc, sizeof(*pctldesc)); + + /* Set pinctrl properties */ + + pin_names = devm_kasprintf_strarray(dev, "pin", BCM4908_NUM_PINS); + if (IS_ERR(pin_names)) + return PTR_ERR(pin_names); + + pins = devm_kcalloc(dev, BCM4908_NUM_PINS, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + for (i = 0; i < BCM4908_NUM_PINS; i++) { + pins[i].number = i; + pins[i].name = pin_names[i]; + } + pctldesc->pins = pins; + pctldesc->npins = BCM4908_NUM_PINS; + + /* Register */ + + bcm4908_pinctrl->pctldev = devm_pinctrl_register(dev, pctldesc, bcm4908_pinctrl); + if (IS_ERR(bcm4908_pinctrl->pctldev)) + return dev_err_probe(dev, PTR_ERR(bcm4908_pinctrl->pctldev), + "Failed to register pinctrl\n"); + + /* Groups */ + + for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_grps); i++) { + const struct bcm4908_pinctrl_grp *group = &bcm4908_pinctrl_grps[i]; + int *pins; + int j; + + pins = devm_kcalloc(dev, group->num_pins, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + for (j = 0; j < group->num_pins; j++) + pins[j] = group->pins[j].number; + + pinctrl_generic_add_group(bcm4908_pinctrl->pctldev, group->name, + pins, group->num_pins, (void *)group); + } + + /* Functions */ + + for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_functions); i++) { + const struct bcm4908_pinctrl_function *function = &bcm4908_pinctrl_functions[i]; + + pinmux_generic_add_function(bcm4908_pinctrl->pctldev, + function->name, + function->groups, + function->num_groups, NULL); + } + + return 0; +} + +static struct platform_driver bcm4908_pinctrl_driver = { + .probe = bcm4908_pinctrl_probe, + .driver = { + .name = "bcm4908-pinctrl", + .of_match_table = bcm4908_pinctrl_of_match_table, + }, +}; + +module_platform_driver(bcm4908_pinctrl_driver); + +MODULE_AUTHOR("RafaÅ‚ MiÅ‚ecki"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, bcm4908_pinctrl_of_match_table); diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c index b17a03cf87be..a073eedd71aa 100644 --- a/drivers/pinctrl/berlin/berlin.c +++ b/drivers/pinctrl/berlin/berlin.c @@ -233,6 +233,8 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev) pctrl->functions = krealloc(pctrl->functions, pctrl->nfunctions * sizeof(*pctrl->functions), GFP_KERNEL); + if (!pctrl->functions) + return -ENOMEM; /* map functions to theirs groups */ for (i = 0; i < pctrl->desc->ngroups; i++) { diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index 8bdafaf40b29..453dc47f4fa4 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -180,6 +180,13 @@ config PINCTRL_IMXRT1050 help Say Y here to enable the imxrt1050 pinctrl driver +config PINCTRL_IMX93 + tristate "IMX93 pinctrl driver" + depends on ARCH_MXC + select PINCTRL_IMX + help + Say Y here to enable the imx93 pinctrl driver + config PINCTRL_VF610 bool "Freescale Vybrid VF610 pinctrl driver" depends on SOC_VF610 diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index 565a0350bf09..9f5d1c090338 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o obj-$(CONFIG_PINCTRL_IMX8DXL) += pinctrl-imx8dxl.o obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o +obj-$(CONFIG_PINCTRL_IMX93) += pinctrl-imx93.o obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index fa3cc0b80ede..3a7d2de10b13 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -661,7 +661,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np, func->name = np->name; func->num_group_names = of_get_child_count(np); if (func->num_group_names == 0) { - dev_err(ipctl->dev, "no groups defined in %pOF\n", np); + dev_info(ipctl->dev, "no groups defined in %pOF\n", np); return -EINVAL; } diff --git a/drivers/pinctrl/freescale/pinctrl-imx93.c b/drivers/pinctrl/freescale/pinctrl-imx93.c new file mode 100644 index 000000000000..c0630f69e995 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx93.c @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2021 NXP + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-imx.h" + +enum imx93_pads { + IMX93_IOMUXC_DAP_TDI = 0, + IMX93_IOMUXC_DAP_TMS_SWDIO = 1, + IMX93_IOMUXC_DAP_TCLK_SWCLK = 2, + IMX93_IOMUXC_DAP_TDO_TRACESWO = 3, + IMX93_IOMUXC_GPIO_IO00 = 4, + IMX93_IOMUXC_GPIO_IO01 = 5, + IMX93_IOMUXC_GPIO_IO02 = 6, + IMX93_IOMUXC_GPIO_IO03 = 7, + IMX93_IOMUXC_GPIO_IO04 = 8, + IMX93_IOMUXC_GPIO_IO05 = 9, + IMX93_IOMUXC_GPIO_IO06 = 10, + IMX93_IOMUXC_GPIO_IO07 = 11, + IMX93_IOMUXC_GPIO_IO08 = 12, + IMX93_IOMUXC_GPIO_IO09 = 13, + IMX93_IOMUXC_GPIO_IO10 = 14, + IMX93_IOMUXC_GPIO_IO11 = 15, + IMX93_IOMUXC_GPIO_IO12 = 16, + IMX93_IOMUXC_GPIO_IO13 = 17, + IMX93_IOMUXC_GPIO_IO14 = 18, + IMX93_IOMUXC_GPIO_IO15 = 19, + IMX93_IOMUXC_GPIO_IO16 = 20, + IMX93_IOMUXC_GPIO_IO17 = 21, + IMX93_IOMUXC_GPIO_IO18 = 22, + IMX93_IOMUXC_GPIO_IO19 = 23, + IMX93_IOMUXC_GPIO_IO20 = 24, + IMX93_IOMUXC_GPIO_IO21 = 25, + IMX93_IOMUXC_GPIO_IO22 = 26, + IMX93_IOMUXC_GPIO_IO23 = 27, + IMX93_IOMUXC_GPIO_IO24 = 28, + IMX93_IOMUXC_GPIO_IO25 = 29, + IMX93_IOMUXC_GPIO_IO26 = 30, + IMX93_IOMUXC_GPIO_IO27 = 31, + IMX93_IOMUXC_GPIO_IO28 = 32, + IMX93_IOMUXC_GPIO_IO29 = 33, + IMX93_IOMUXC_CCM_CLKO1 = 34, + IMX93_IOMUXC_CCM_CLKO2 = 35, + IMX93_IOMUXC_CCM_CLKO3 = 36, + IMX93_IOMUXC_CCM_CLKO4 = 37, + IMX93_IOMUXC_ENET1_MDC = 38, + IMX93_IOMUXC_ENET1_MDIO = 39, + IMX93_IOMUXC_ENET1_TD3 = 40, + IMX93_IOMUXC_ENET1_TD2 = 41, + IMX93_IOMUXC_ENET1_TD1 = 42, + IMX93_IOMUXC_ENET1_TD0 = 43, + IMX93_IOMUXC_ENET1_TX_CTL = 44, + IMX93_IOMUXC_ENET1_TXC = 45, + IMX93_IOMUXC_ENET1_RX_CTL = 46, + IMX93_IOMUXC_ENET1_RXC = 47, + IMX93_IOMUXC_ENET1_RD0 = 48, + IMX93_IOMUXC_ENET1_RD1 = 49, + IMX93_IOMUXC_ENET1_RD2 = 50, + IMX93_IOMUXC_ENET1_RD3 = 51, + IMX93_IOMUXC_ENET2_MDC = 52, + IMX93_IOMUXC_ENET2_MDIO = 53, + IMX93_IOMUXC_ENET2_TD3 = 54, + IMX93_IOMUXC_ENET2_TD2 = 55, + IMX93_IOMUXC_ENET2_TD1 = 56, + IMX93_IOMUXC_ENET2_TD0 = 57, + IMX93_IOMUXC_ENET2_TX_CTL = 58, + IMX93_IOMUXC_ENET2_TXC = 59, + IMX93_IOMUXC_ENET2_RX_CTL = 60, + IMX93_IOMUXC_ENET2_RXC = 61, + IMX93_IOMUXC_ENET2_RD0 = 62, + IMX93_IOMUXC_ENET2_RD1 = 63, + IMX93_IOMUXC_ENET2_RD2 = 64, + IMX93_IOMUXC_ENET2_RD3 = 65, + IMX93_IOMUXC_SD1_CLK = 66, + IMX93_IOMUXC_SD1_CMD = 67, + IMX93_IOMUXC_SD1_DATA0 = 68, + IMX93_IOMUXC_SD1_DATA1 = 69, + IMX93_IOMUXC_SD1_DATA2 = 70, + IMX93_IOMUXC_SD1_DATA3 = 71, + IMX93_IOMUXC_SD1_DATA4 = 72, + IMX93_IOMUXC_SD1_DATA5 = 73, + IMX93_IOMUXC_SD1_DATA6 = 74, + IMX93_IOMUXC_SD1_DATA7 = 75, + IMX93_IOMUXC_SD1_STROBE = 76, + IMX93_IOMUXC_SD2_VSELECT = 77, + IMX93_IOMUXC_SD3_CLK = 78, + IMX93_IOMUXC_SD3_CMD = 79, + IMX93_IOMUXC_SD3_DATA0 = 80, + IMX93_IOMUXC_SD3_DATA1 = 81, + IMX93_IOMUXC_SD3_DATA2 = 82, + IMX93_IOMUXC_SD3_DATA3 = 83, + IMX93_IOMUXC_SD2_CD_B = 84, + IMX93_IOMUXC_SD2_CLK = 85, + IMX93_IOMUXC_SD2_CMD = 86, + IMX93_IOMUXC_SD2_DATA0 = 87, + IMX93_IOMUXC_SD2_DATA1 = 88, + IMX93_IOMUXC_SD2_DATA2 = 89, + IMX93_IOMUXC_SD2_DATA3 = 90, + IMX93_IOMUXC_SD2_RESET_B = 91, + IMX93_IOMUXC_I2C1_SCL = 92, + IMX93_IOMUXC_I2C1_SDA = 93, + IMX93_IOMUXC_I2C2_SCL = 94, + IMX93_IOMUXC_I2C2_SDA = 95, + IMX93_IOMUXC_UART1_RXD = 96, + IMX93_IOMUXC_UART1_TXD = 97, + IMX93_IOMUXC_UART2_RXD = 98, + IMX93_IOMUXC_UART2_TXD = 99, + IMX93_IOMUXC_PDM_CLK = 100, + IMX93_IOMUXC_PDM_BIT_STREAM0 = 101, + IMX93_IOMUXC_PDM_BIT_STREAM1 = 102, + IMX93_IOMUXC_SAI1_TXFS = 103, + IMX93_IOMUXC_SAI1_TXC = 104, + IMX93_IOMUXC_SAI1_TXD0 = 105, + IMX93_IOMUXC_SAI1_RXD0 = 106, + IMX93_IOMUXC_WDOG_ANY = 107, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx93_pinctrl_pads[] = { + IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TDI), + IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TMS_SWDIO), + IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TCLK_SWCLK), + IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TDO_TRACESWO), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO00), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO01), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO02), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO03), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO04), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO05), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO06), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO07), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO08), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO09), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO10), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO11), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO12), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO13), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO14), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO15), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO16), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO17), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO18), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO19), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO20), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO21), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO22), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO23), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO24), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO25), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO26), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO27), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO28), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO29), + IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO1), + IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO2), + IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO3), + IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO4), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_MDC), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_MDIO), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD3), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD2), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD1), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TX_CTL), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TXC), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RX_CTL), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RXC), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD1), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD2), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD3), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_MDC), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_MDIO), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD3), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD2), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD1), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TX_CTL), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TXC), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RX_CTL), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RXC), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD1), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD2), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD3), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_CLK), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_CMD), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA1), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA2), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA3), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA4), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA5), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA6), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA7), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_STROBE), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_VSELECT), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_CLK), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_CMD), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA1), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA2), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA3), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CD_B), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CLK), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CMD), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA1), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA2), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA3), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_RESET_B), + IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C1_SCL), + IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C1_SDA), + IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C2_SCL), + IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C2_SDA), + IMX_PINCTRL_PIN(IMX93_IOMUXC_UART1_RXD), + IMX_PINCTRL_PIN(IMX93_IOMUXC_UART1_TXD), + IMX_PINCTRL_PIN(IMX93_IOMUXC_UART2_RXD), + IMX_PINCTRL_PIN(IMX93_IOMUXC_UART2_TXD), + IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_CLK), + IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_BIT_STREAM0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_BIT_STREAM1), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXFS), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXC), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXD0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_RXD0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_WDOG_ANY), +}; + +static const struct imx_pinctrl_soc_info imx93_pinctrl_info = { + .pins = imx93_pinctrl_pads, + .npins = ARRAY_SIZE(imx93_pinctrl_pads), + .gpr_compatible = "fsl,imx93-iomuxc-gpr", +}; + +static const struct of_device_id imx93_pinctrl_of_match[] = { + { .compatible = "fsl,imx93-iomuxc", }, + { /* sentinel */ } +}; + +static int imx93_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx93_pinctrl_info); +} + +static struct platform_driver imx93_pinctrl_driver = { + .driver = { + .name = "imx93-pinctrl", + .of_match_table = imx93_pinctrl_of_match, + .suppress_bind_attrs = true, + }, + .probe = imx93_pinctrl_probe, +}; + +static int __init imx93_pinctrl_init(void) +{ + return platform_driver_register(&imx93_pinctrl_driver); +} +arch_initcall(imx93_pinctrl_init); + +MODULE_AUTHOR("Bai Ping <ping.bai@nxp.com>"); +MODULE_DESCRIPTION("NXP i.MX93 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/intel/pinctrl-alderlake.c b/drivers/pinctrl/intel/pinctrl-alderlake.c index efb664f12b5d..32ba50efbceb 100644 --- a/drivers/pinctrl/intel/pinctrl-alderlake.c +++ b/drivers/pinctrl/intel/pinctrl-alderlake.c @@ -2,7 +2,7 @@ /* * Intel Alder Lake PCH pinctrl/GPIO driver * - * Copyright (C) 2020, Intel Corporation + * Copyright (C) 2020, 2022 Intel Corporation * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> */ @@ -42,6 +42,319 @@ .ngpps = ARRAY_SIZE(g), \ } +/* Alder Lake-N */ +static const struct pinctrl_pin_desc adln_pins[] = { + /* GPP_B */ + PINCTRL_PIN(0, "CORE_VID_0"), + PINCTRL_PIN(1, "CORE_VID_1"), + PINCTRL_PIN(2, "GPPC_B_2"), + PINCTRL_PIN(3, "GPPC_B_3"), + PINCTRL_PIN(4, "GPPC_B_4"), + PINCTRL_PIN(5, "GPPC_B_5"), + PINCTRL_PIN(6, "GPPC_B_6"), + PINCTRL_PIN(7, "GPPC_B_7"), + PINCTRL_PIN(8, "GPPC_B_8"), + PINCTRL_PIN(9, "GPPC_B_9"), + PINCTRL_PIN(10, "GPPC_B_10"), + PINCTRL_PIN(11, "GPPC_B_11"), + PINCTRL_PIN(12, "SLP_S0B"), + PINCTRL_PIN(13, "PLTRSTB"), + PINCTRL_PIN(14, "GPPC_B_14"), + PINCTRL_PIN(15, "GPPC_B_15"), + PINCTRL_PIN(16, "GPPC_B_16"), + PINCTRL_PIN(17, "GPPC_B_17"), + PINCTRL_PIN(18, "GPPC_B_18"), + PINCTRL_PIN(19, "GPPC_B_19"), + PINCTRL_PIN(20, "GPPC_B_20"), + PINCTRL_PIN(21, "GPPC_B_21"), + PINCTRL_PIN(22, "GPPC_B_22"), + PINCTRL_PIN(23, "GPPC_B_23"), + PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"), + PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"), + /* GPP_T */ + PINCTRL_PIN(26, "GPPC_T_0"), + PINCTRL_PIN(27, "GPPC_T_1"), + PINCTRL_PIN(28, "FUSA_DIAGTEST_EN"), + PINCTRL_PIN(29, "FUSA_DIAGTEST_MODE"), + PINCTRL_PIN(30, "GPPC_T_4"), + PINCTRL_PIN(31, "GPPC_T_5"), + PINCTRL_PIN(32, "GPPC_T_6"), + PINCTRL_PIN(33, "GPPC_T_7"), + PINCTRL_PIN(34, "GPPC_T_8"), + PINCTRL_PIN(35, "GPPC_T_9"), + PINCTRL_PIN(36, "GPPC_T_10"), + PINCTRL_PIN(37, "GPPC_T_11"), + PINCTRL_PIN(38, "GPPC_T_12"), + PINCTRL_PIN(39, "GPPC_T_13"), + PINCTRL_PIN(40, "GPPC_T_14"), + PINCTRL_PIN(41, "GPPC_T_15"), + /* GPP_A */ + PINCTRL_PIN(42, "ESPI_IO_0"), + PINCTRL_PIN(43, "ESPI_IO_1"), + PINCTRL_PIN(44, "ESPI_IO_2"), + PINCTRL_PIN(45, "ESPI_IO_3"), + PINCTRL_PIN(46, "ESPI_CS0B"), + PINCTRL_PIN(47, "ESPI_ALERT0B"), + PINCTRL_PIN(48, "ESPI_ALERT1B"), + PINCTRL_PIN(49, "GPPC_A_7"), + PINCTRL_PIN(50, "GPPC_A_8"), + PINCTRL_PIN(51, "ESPI_CLK"), + PINCTRL_PIN(52, "ESPI_RESETB"), + PINCTRL_PIN(53, "GPPC_A_11"), + PINCTRL_PIN(54, "GPPC_A_12"), + PINCTRL_PIN(55, "GPPC_A_13"), + PINCTRL_PIN(56, "GPPC_A_14"), + PINCTRL_PIN(57, "GPPC_A_15"), + PINCTRL_PIN(58, "GPPC_A_16"), + PINCTRL_PIN(59, "GPPC_A_17"), + PINCTRL_PIN(60, "GPPC_A_18"), + PINCTRL_PIN(61, "GPPC_A_19"), + PINCTRL_PIN(62, "GPPC_A_20"), + PINCTRL_PIN(63, "GPPC_A_21"), + PINCTRL_PIN(64, "GPPC_A_22"), + PINCTRL_PIN(65, "ESPI_CS1B"), + PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"), + /* GPP_S */ + PINCTRL_PIN(67, "GPP_S_0"), + PINCTRL_PIN(68, "GPP_S_1"), + PINCTRL_PIN(69, "GPP_S_2"), + PINCTRL_PIN(70, "GPP_S_3"), + PINCTRL_PIN(71, "GPP_S_4"), + PINCTRL_PIN(72, "GPP_S_5"), + PINCTRL_PIN(73, "GPP_S_6"), + PINCTRL_PIN(74, "GPP_S_7"), + /* GPP_I */ + PINCTRL_PIN(75, "GPP_F_0_CNV_BRI_DT_UART0_RTSB"), + PINCTRL_PIN(76, "GPP_F_1_CNV_BRI_RSP_UART0_RXD"), + PINCTRL_PIN(77, "GPP_F_2_CNV_RGI_DT_UART0_TXD"), + PINCTRL_PIN(78, "GPP_F_3_CNV_RGI_RSP_UART0_CTSB"), + PINCTRL_PIN(79, "GPP_F_4_CNV_RF_RESET_B"), + PINCTRL_PIN(80, "GPP_F_5_MODEM_CLKREQ"), + PINCTRL_PIN(81, "GPP_F_6_CNV_PA_BLANKING"), + PINCTRL_PIN(82, "GPP_F_7_EMMC_CMD"), + PINCTRL_PIN(83, "GPP_F_8_EMMC_DATA0"), + PINCTRL_PIN(84, "GPP_F_9_EMMC_DATA1"), + PINCTRL_PIN(85, "GPP_F_10_EMMC_DATA2"), + PINCTRL_PIN(86, "GPP_F_11_EMMC_DATA3"), + PINCTRL_PIN(87, "GPP_F_12_EMMC_DATA4"), + PINCTRL_PIN(88, "GPP_F_13_EMMC_DATA5"), + PINCTRL_PIN(89, "GPP_F_14_EMMC_DATA6"), + PINCTRL_PIN(90, "GPP_F_15_EMMC_DATA7"), + PINCTRL_PIN(91, "GPP_F_16_EMMC_RCLK"), + PINCTRL_PIN(92, "GPP_F_17_EMMC_CLK"), + PINCTRL_PIN(93, "GPP_F_18_EMMC_RESETB"), + PINCTRL_PIN(94, "GPP_F_19_A4WP_PRESENT"), + /* GPP_H */ + PINCTRL_PIN(95, "GPPC_H_0"), + PINCTRL_PIN(96, "GPPC_H_1"), + PINCTRL_PIN(97, "GPPC_H_2"), + PINCTRL_PIN(98, "GPPC_H_3"), + PINCTRL_PIN(99, "GPPC_H_4"), + PINCTRL_PIN(100, "GPPC_H_5"), + PINCTRL_PIN(101, "GPPC_H_6"), + PINCTRL_PIN(102, "GPPC_H_7"), + PINCTRL_PIN(103, "GPPC_H_8"), + PINCTRL_PIN(104, "GPPC_H_9"), + PINCTRL_PIN(105, "GPPC_H_10"), + PINCTRL_PIN(106, "GPPC_H_11"), + PINCTRL_PIN(107, "I2C7_SDA"), + PINCTRL_PIN(108, "I2C7_SCL"), + PINCTRL_PIN(109, "GPPC_H_14"), + PINCTRL_PIN(110, "GPPC_H_15"), + PINCTRL_PIN(111, "GPPC_H_16"), + PINCTRL_PIN(112, "GPPC_H_17"), + PINCTRL_PIN(113, "CPU_C10_GATEB"), + PINCTRL_PIN(114, "GPPC_H_19"), + PINCTRL_PIN(115, "GPPC_H_20"), + PINCTRL_PIN(116, "GPPC_H_21"), + PINCTRL_PIN(117, "GPPC_H_22"), + PINCTRL_PIN(118, "GPPC_H_23"), + /* GPP_D */ + PINCTRL_PIN(119, "GPPC_D_0"), + PINCTRL_PIN(120, "GPPC_D_1"), + PINCTRL_PIN(121, "GPPC_D_2"), + PINCTRL_PIN(122, "GPPC_D_3"), + PINCTRL_PIN(123, "GPPC_D_4"), + PINCTRL_PIN(124, "GPPC_D_5"), + PINCTRL_PIN(125, "GPPC_D_6"), + PINCTRL_PIN(126, "GPPC_D_7"), + PINCTRL_PIN(127, "GPPC_D_8"), + PINCTRL_PIN(128, "BSSB_LS2_RX"), + PINCTRL_PIN(129, "BSSB_LS2_TX"), + PINCTRL_PIN(130, "BSSB_LS3_RX"), + PINCTRL_PIN(131, "BSSB_LS3_TX"), + PINCTRL_PIN(132, "GPPC_D_13"), + PINCTRL_PIN(133, "GPPC_D_14"), + PINCTRL_PIN(134, "GPPC_D_15"), + PINCTRL_PIN(135, "GPPC_D_16"), + PINCTRL_PIN(136, "GPPC_D_17"), + PINCTRL_PIN(137, "GPPC_D_18"), + PINCTRL_PIN(138, "GPPC_D_19"), + PINCTRL_PIN(139, "GSPI2_CLK_LOOPBK"), + /* vGPIO */ + PINCTRL_PIN(140, "CNV_BTEN"), + PINCTRL_PIN(141, "CNV_BT_HOST_WAKEB"), + PINCTRL_PIN(142, "CNV_BT_IF_SELECT"), + PINCTRL_PIN(143, "vCNV_BT_UART_TXD"), + PINCTRL_PIN(144, "vCNV_BT_UART_RXD"), + PINCTRL_PIN(145, "vCNV_BT_UART_CTS_B"), + PINCTRL_PIN(146, "vCNV_BT_UART_RTS_B"), + PINCTRL_PIN(147, "vCNV_MFUART1_TXD"), + PINCTRL_PIN(148, "vCNV_MFUART1_RXD"), + PINCTRL_PIN(149, "vCNV_MFUART1_CTS_B"), + PINCTRL_PIN(150, "vCNV_MFUART1_RTS_B"), + PINCTRL_PIN(151, "vUART0_TXD"), + PINCTRL_PIN(152, "vUART0_RXD"), + PINCTRL_PIN(153, "vUART0_CTS_B"), + PINCTRL_PIN(154, "vUART0_RTS_B"), + PINCTRL_PIN(155, "vISH_UART0_TXD"), + PINCTRL_PIN(156, "vISH_UART0_RXD"), + PINCTRL_PIN(157, "vISH_UART0_CTS_B"), + PINCTRL_PIN(158, "vISH_UART0_RTS_B"), + PINCTRL_PIN(159, "vCNV_BT_I2S_BCLK"), + PINCTRL_PIN(160, "vCNV_BT_I2S_WS_SYNC"), + PINCTRL_PIN(161, "vCNV_BT_I2S_SDO"), + PINCTRL_PIN(162, "vCNV_BT_I2S_SDI"), + PINCTRL_PIN(163, "vI2S2_SCLK"), + PINCTRL_PIN(164, "vI2S2_SFRM"), + PINCTRL_PIN(165, "vI2S2_TXD"), + PINCTRL_PIN(166, "vI2S2_RXD"), + PINCTRL_PIN(167, "THC0_WOT_INT"), + PINCTRL_PIN(168, "THC1_WOT_INT"), + /* GPP_C */ + PINCTRL_PIN(169, "SMBCLK"), + PINCTRL_PIN(170, "SMBDATA"), + PINCTRL_PIN(171, "SMBALERTB"), + PINCTRL_PIN(172, "SML0CLK"), + PINCTRL_PIN(173, "SML0DATA"), + PINCTRL_PIN(174, "GPPC_C_5"), + PINCTRL_PIN(175, "GPPC_C_6"), + PINCTRL_PIN(176, "GPPC_C_7"), + PINCTRL_PIN(177, "GPPC_C_8"), + PINCTRL_PIN(178, "GPPC_C_9"), + PINCTRL_PIN(179, "GPPC_C_10"), + PINCTRL_PIN(180, "GPPC_C_11"), + PINCTRL_PIN(181, "GPPC_C_12"), + PINCTRL_PIN(182, "GPPC_C_13"), + PINCTRL_PIN(183, "GPPC_C_14"), + PINCTRL_PIN(184, "GPPC_C_15"), + PINCTRL_PIN(185, "GPPC_C_16"), + PINCTRL_PIN(186, "GPPC_C_17"), + PINCTRL_PIN(187, "GPPC_C_18"), + PINCTRL_PIN(188, "GPPC_C_19"), + PINCTRL_PIN(189, "GPPC_C_20"), + PINCTRL_PIN(190, "GPPC_C_21"), + PINCTRL_PIN(191, "GPPC_C_22"), + PINCTRL_PIN(192, "GPPC_C_23"), + /* GPP_F */ + PINCTRL_PIN(193, "CNV_BRI_DT"), + PINCTRL_PIN(194, "CNV_BRI_RSP"), + PINCTRL_PIN(195, "CNV_RGI_DT"), + PINCTRL_PIN(196, "CNV_RGI_RSP"), + PINCTRL_PIN(197, "CNV_RF_RESET_B"), + PINCTRL_PIN(198, "MODEM_CLKREQ"), + PINCTRL_PIN(199, "GPPC_F_6"), + PINCTRL_PIN(200, "GPPC_F_7"), + PINCTRL_PIN(201, "GPPC_F_8"), + PINCTRL_PIN(202, "BOOTMPC"), + PINCTRL_PIN(203, "GPPC_F_10"), + PINCTRL_PIN(204, "GPPC_F_11"), + PINCTRL_PIN(205, "GPPC_F_12"), + PINCTRL_PIN(206, "GPPC_F_13"), + PINCTRL_PIN(207, "GPPC_F_14"), + PINCTRL_PIN(208, "GPPC_F_15"), + PINCTRL_PIN(209, "GPPC_F_16"), + PINCTRL_PIN(210, "GPPC_F_17"), + PINCTRL_PIN(211, "GPPC_F_18"), + PINCTRL_PIN(212, "GPPC_F_19"), + PINCTRL_PIN(213, "EXT_PWR_GATEB"), + PINCTRL_PIN(214, "EXT_PWR_GATE2B"), + PINCTRL_PIN(215, "GPPC_F_22"), + PINCTRL_PIN(216, "GPPC_F_23"), + PINCTRL_PIN(217, "GPPF_CLK_LOOPBACK"), + /* HVCMOS */ + PINCTRL_PIN(218, "L_BKLTEN"), + PINCTRL_PIN(219, "L_BKLTCTL"), + PINCTRL_PIN(220, "L_VDDEN"), + PINCTRL_PIN(221, "SYS_PWROK"), + PINCTRL_PIN(222, "SYS_RESETB"), + PINCTRL_PIN(223, "MLK_RSTB"), + /* GPP_E */ + PINCTRL_PIN(224, "GPPC_E_0"), + PINCTRL_PIN(225, "GPPC_E_1"), + PINCTRL_PIN(226, "GPPC_E_2"), + PINCTRL_PIN(227, "GPPC_E_3"), + PINCTRL_PIN(228, "GPPC_E_4"), + PINCTRL_PIN(229, "GPPC_E_5"), + PINCTRL_PIN(230, "GPPC_E_6"), + PINCTRL_PIN(231, "GPPC_E_7"), + PINCTRL_PIN(232, "GPPC_E_8"), + PINCTRL_PIN(233, "GPPC_E_9"), + PINCTRL_PIN(234, "GPPC_E_10"), + PINCTRL_PIN(235, "GPPC_E_11"), + PINCTRL_PIN(236, "GPPC_E_12"), + PINCTRL_PIN(237, "GPPC_E_13"), + PINCTRL_PIN(238, "GPPC_E_14"), + PINCTRL_PIN(239, "FIVR_DIGPB_0"), + PINCTRL_PIN(240, "FIVR_DIGPB_1"), + PINCTRL_PIN(241, "GPPC_E_17"), + PINCTRL_PIN(242, "BSSB_LS0_RX"), + PINCTRL_PIN(243, "BSSB_LS0_TX"), + PINCTRL_PIN(244, "BSSB_LS1_RX"), + PINCTRL_PIN(245, "BSSB_LS1_TX"), + PINCTRL_PIN(246, "DNX_FORCE_RELOAD"), + PINCTRL_PIN(247, "GPPC_E_23"), + PINCTRL_PIN(248, "GPPE_CLK_LOOPBACK"), + /* GPP_R */ + PINCTRL_PIN(249, "HDA_BCLK"), + PINCTRL_PIN(250, "HDA_SYNC"), + PINCTRL_PIN(251, "HDA_SDO"), + PINCTRL_PIN(252, "HDA_SDI_0"), + PINCTRL_PIN(253, "HDA_RSTB"), + PINCTRL_PIN(254, "GPP_R_5"), + PINCTRL_PIN(255, "GPP_R_6"), + PINCTRL_PIN(256, "GPP_R_7"), +}; + +static const struct intel_padgroup adln_community0_gpps[] = { + ADL_GPP(0, 0, 25, 0), /* GPP_B */ + ADL_GPP(1, 26, 41, 32), /* GPP_T */ + ADL_GPP(2, 42, 66, 64), /* GPP_A */ +}; + +static const struct intel_padgroup adln_community1_gpps[] = { + ADL_GPP(0, 67, 74, 96), /* GPP_S */ + ADL_GPP(1, 75, 94, 128), /* GPP_I */ + ADL_GPP(2, 95, 118, 160), /* GPP_H */ + ADL_GPP(3, 119, 139, 192), /* GPP_D */ + ADL_GPP(4, 140, 168, 224), /* vGPIO */ +}; + +static const struct intel_padgroup adln_community4_gpps[] = { + ADL_GPP(0, 169, 192, 256), /* GPP_C */ + ADL_GPP(1, 193, 217, 288), /* GPP_F */ + ADL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + ADL_GPP(3, 224, 248, 320), /* GPP_E */ +}; + +static const struct intel_padgroup adln_community5_gpps[] = { + ADL_GPP(0, 249, 256, 352), /* GPP_R */ +}; + +static const struct intel_community adln_communities[] = { + ADL_COMMUNITY(0, 0, 66, adln_community0_gpps), + ADL_COMMUNITY(1, 67, 168, adln_community1_gpps), + ADL_COMMUNITY(2, 169, 248, adln_community4_gpps), + ADL_COMMUNITY(3, 249, 256, adln_community5_gpps), +}; + +static const struct intel_pinctrl_soc_data adln_soc_data = { + .pins = adln_pins, + .npins = ARRAY_SIZE(adln_pins), + .communities = adln_communities, + .ncommunities = ARRAY_SIZE(adln_communities), +}; + /* Alder Lake-S */ static const struct pinctrl_pin_desc adls_pins[] = { /* GPP_I */ @@ -416,6 +729,8 @@ static const struct intel_pinctrl_soc_data adls_soc_data = { static const struct acpi_device_id adl_pinctrl_acpi_match[] = { { "INTC1056", (kernel_ulong_t)&adls_soc_data }, + { "INTC1057", (kernel_ulong_t)&adln_soc_data }, + { "INTC1085", (kernel_ulong_t)&adls_soc_data }, { } }; MODULE_DEVICE_TABLE(acpi, adl_pinctrl_acpi_match); diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 1cc660e6458e..f89c9fcd4e1b 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -32,6 +32,7 @@ #define BYT_VAL_REG 0x008 #define BYT_DFT_REG 0x00c #define BYT_INT_STAT_REG 0x800 +#define BYT_DIRECT_IRQ_REG 0x980 #define BYT_DEBOUNCE_REG 0x9d0 /* BYT_CONF0_REG register bits */ @@ -1475,6 +1476,51 @@ static void byt_gpio_irq_handler(struct irq_desc *desc) chip->irq_eoi(data); } +static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0) +{ + int direct_irq, ioapic_direct_irq_base; + u8 *match, direct_irq_mux[16]; + u32 trig; + + memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG, + sizeof(direct_irq_mux)); + match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux)); + if (!match) { + dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set but no IRQ assigned, clearing\n", pin); + return false; + } + + direct_irq = match - direct_irq_mux; + /* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */ + ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67; + dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin, + direct_irq, direct_irq + ioapic_direct_irq_base); + + /* + * Testing has shown that the way direct IRQs work is that the combination of the + * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ + * trigger block, which normally sets the status flag in the IRQ status reg at + * 0x800, to one of the IO-APIC pins according to the mux registers. + * + * This means that: + * 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block + * 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly + * passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set, + * selecting edge mode operation then on the first edge the IO-APIC pin goes + * high, but since no write-to-clear write will be done to the IRQ status reg + * at 0x800, the detected edge condition will never get cleared. + */ + trig = conf0 & BYT_TRIG_MASK; + if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) && + trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) { + dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set without trigger (conf0: %xh), clearing\n", + pin, conf0); + return false; + } + + return true; +} + static void byt_init_irq_valid_mask(struct gpio_chip *chip, unsigned long *valid_mask, unsigned int ngpios) @@ -1502,8 +1548,13 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip, value = readl(reg); if (value & BYT_DIRECT_IRQ_EN) { - clear_bit(i, valid_mask); - dev_dbg(vg->dev, "excluding GPIO %d from IRQ domain\n", i); + if (byt_direct_irq_sanity_check(vg, i, value)) { + clear_bit(i, valid_mask); + } else { + value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | + BYT_TRIG_NEG | BYT_TRIG_LVL); + writel(value, reg); + } } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) { byt_gpio_clear_triggering(vg, i); dev_dbg(vg->dev, "disabling GPIO %d\n", i); diff --git a/drivers/pinctrl/intel/pinctrl-icelake.c b/drivers/pinctrl/intel/pinctrl-icelake.c index 429b5a83acf0..27c248cc16f7 100644 --- a/drivers/pinctrl/intel/pinctrl-icelake.c +++ b/drivers/pinctrl/intel/pinctrl-icelake.c @@ -2,7 +2,7 @@ /* * Intel Ice Lake PCH pinctrl/GPIO driver * - * Copyright (C) 2018, Intel Corporation + * Copyright (C) 2018, 2022 Intel Corporation * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> * Mika Westerberg <mika.westerberg@linux.intel.com> */ @@ -19,7 +19,8 @@ #define ICL_PADCFGLOCK 0x080 #define ICL_HOSTSW_OWN 0x0b0 #define ICL_GPI_IS 0x100 -#define ICL_GPI_IE 0x110 +#define ICL_LP_GPI_IE 0x110 +#define ICL_N_GPI_IE 0x120 #define ICL_GPP(r, s, e, g) \ { \ @@ -29,20 +30,26 @@ .gpio_base = (g), \ } -#define ICL_COMMUNITY(b, s, e, g) \ +#define ICL_COMMUNITY(b, s, e, ie, g) \ { \ .barno = (b), \ .padown_offset = ICL_PAD_OWN, \ .padcfglock_offset = ICL_PADCFGLOCK, \ .hostown_offset = ICL_HOSTSW_OWN, \ .is_offset = ICL_GPI_IS, \ - .ie_offset = ICL_GPI_IE, \ + .ie_offset = (ie), \ .pin_base = (s), \ .npins = ((e) - (s) + 1), \ .gpps = (g), \ .ngpps = ARRAY_SIZE(g), \ } +#define ICL_LP_COMMUNITY(b, s, e, g) \ + ICL_COMMUNITY(b, s, e, ICL_LP_GPI_IE, g) + +#define ICL_N_COMMUNITY(b, s, e, g) \ + ICL_COMMUNITY(b, s, e, ICL_N_GPI_IE, g) + /* Ice Lake-LP */ static const struct pinctrl_pin_desc icllp_pins[] = { /* GPP_G */ @@ -329,10 +336,10 @@ static const struct intel_padgroup icllp_community5_gpps[] = { }; static const struct intel_community icllp_communities[] = { - ICL_COMMUNITY(0, 0, 58, icllp_community0_gpps), - ICL_COMMUNITY(1, 59, 152, icllp_community1_gpps), - ICL_COMMUNITY(2, 153, 215, icllp_community4_gpps), - ICL_COMMUNITY(3, 216, 240, icllp_community5_gpps), + ICL_LP_COMMUNITY(0, 0, 58, icllp_community0_gpps), + ICL_LP_COMMUNITY(1, 59, 152, icllp_community1_gpps), + ICL_LP_COMMUNITY(2, 153, 215, icllp_community4_gpps), + ICL_LP_COMMUNITY(3, 216, 240, icllp_community5_gpps), }; static const unsigned int icllp_spi0_pins[] = { 22, 23, 24, 25, 26 }; @@ -403,10 +410,278 @@ static const struct intel_pinctrl_soc_data icllp_soc_data = { .ncommunities = ARRAY_SIZE(icllp_communities), }; +/* Ice Lake-N */ +static const struct pinctrl_pin_desc icln_pins[] = { + /* SPI */ + PINCTRL_PIN(0, "SPI0_IO_2"), + PINCTRL_PIN(1, "SPI0_IO_3"), + PINCTRL_PIN(2, "SPI0_MOSI_IO_0"), + PINCTRL_PIN(3, "SPI0_MISO_IO_1"), + PINCTRL_PIN(4, "SPI0_TPM_CSB"), + PINCTRL_PIN(5, "SPI0_FLASH_0_CSB"), + PINCTRL_PIN(6, "SPI0_FLASH_1_CSB"), + PINCTRL_PIN(7, "SPI0_CLK"), + PINCTRL_PIN(8, "SPI0_CLK_LOOPBK"), + /* GPP_B */ + PINCTRL_PIN(9, "CORE_VID_0"), + PINCTRL_PIN(10, "CORE_VID_1"), + PINCTRL_PIN(11, "VRALERTB"), + PINCTRL_PIN(12, "CPU_GP_2"), + PINCTRL_PIN(13, "CPU_GP_3"), + PINCTRL_PIN(14, "SRCCLKREQB_0"), + PINCTRL_PIN(15, "SRCCLKREQB_1"), + PINCTRL_PIN(16, "SRCCLKREQB_2"), + PINCTRL_PIN(17, "SRCCLKREQB_3"), + PINCTRL_PIN(18, "SRCCLKREQB_4"), + PINCTRL_PIN(19, "SRCCLKREQB_5"), + PINCTRL_PIN(20, "EXT_PWR_GATEB"), + PINCTRL_PIN(21, "SLP_S0B"), + PINCTRL_PIN(22, "PLTRSTB"), + PINCTRL_PIN(23, "SPKR_GSPI0_CS1B"), + PINCTRL_PIN(24, "GSPI0_CS0B"), + PINCTRL_PIN(25, "GSPI0_CLK"), + PINCTRL_PIN(26, "GSPI0_MISO_TBT_LSX3_A"), + PINCTRL_PIN(27, "GSPI0_MOSI_TBT_LSX3_B"), + PINCTRL_PIN(28, "GSPI1_CS0B"), + PINCTRL_PIN(29, "GSPI1_CLK_NFC_CLK"), + PINCTRL_PIN(30, "GSPI1_MISO_NFC_CLKREQ"), + PINCTRL_PIN(31, "GSPI1_MOSI"), + PINCTRL_PIN(32, "GSPI1_CS1B"), + PINCTRL_PIN(33, "GSPI0_CLK_LOOPBK"), + PINCTRL_PIN(34, "GSPI1_CLK_LOOPBK"), + /* GPP_A */ + PINCTRL_PIN(35, "ESPI_IO_0"), + PINCTRL_PIN(36, "ESPI_IO_1"), + PINCTRL_PIN(37, "ESPI_IO_2"), + PINCTRL_PIN(38, "ESPI_IO_3"), + PINCTRL_PIN(39, "ESPI_CSB"), + PINCTRL_PIN(40, "ESPI_CLK"), + PINCTRL_PIN(41, "ESPI_RESETB"), + PINCTRL_PIN(42, "SMBCLK"), + PINCTRL_PIN(43, "SMBDATA"), + PINCTRL_PIN(44, "SMBALERTB"), + PINCTRL_PIN(45, "CPU_GP_0"), + PINCTRL_PIN(46, "CPU_GP_1"), + PINCTRL_PIN(47, "USB2_OCB_1"), + PINCTRL_PIN(48, "USB2_OCB_2"), + PINCTRL_PIN(49, "USB2_OCB_3"), + PINCTRL_PIN(50, "DDSP_HPD_A_TIME_SYNC_0"), + PINCTRL_PIN(51, "DDSP_HPD_B_TIME_SYNC_1"), + PINCTRL_PIN(52, "DDSP_HPD_C"), + PINCTRL_PIN(53, "USB2_OCB_0"), + PINCTRL_PIN(54, "PCHHOTB"), + PINCTRL_PIN(55, "ESPI_CLK_LOOPBK"), + /* GPP_S */ + PINCTRL_PIN(56, "SNDW1_CLK"), + PINCTRL_PIN(57, "SNDW1_DATA"), + PINCTRL_PIN(58, "SNDW2_CLK"), + PINCTRL_PIN(59, "SNDW2_DATA"), + PINCTRL_PIN(60, "SNDW3_CLK_DMIC_CLK_1"), + PINCTRL_PIN(61, "SNDW3_DATA_DMIC_DATA_1"), + PINCTRL_PIN(62, "SNDW4_CLK_DMIC_CLK_0"), + PINCTRL_PIN(63, "SNDW4_DATA_DMIC_DATA_0"), + /* GPP_R */ + PINCTRL_PIN(64, "HDA_BCLK"), + PINCTRL_PIN(65, "HDA_SYNC"), + PINCTRL_PIN(66, "HDA_SDO"), + PINCTRL_PIN(67, "HDA_SDI_0"), + PINCTRL_PIN(68, "HDA_RSTB"), + PINCTRL_PIN(69, "HDA_SDI_1_I2S1_RXD"), + PINCTRL_PIN(70, "I2S1_SFRM"), + PINCTRL_PIN(71, "I2S1_TXD"), + /* GPP_H */ + PINCTRL_PIN(72, "GPPC_H_0"), + PINCTRL_PIN(73, "CNV_RF_RESET_B"), + PINCTRL_PIN(74, "MODEM_CLKREQ"), + PINCTRL_PIN(75, "SX_EXIT_HOLDOFFB"), + PINCTRL_PIN(76, "I2C2_SDA"), + PINCTRL_PIN(77, "I2C2_SCL"), + PINCTRL_PIN(78, "I2C3_SDA"), + PINCTRL_PIN(79, "I2C3_SCL"), + PINCTRL_PIN(80, "I2C4_SDA"), + PINCTRL_PIN(81, "I2C4_SCL"), + PINCTRL_PIN(82, "CPU_VCCIO_PWR_GATEB"), + PINCTRL_PIN(83, "I2S2_SCLK"), + PINCTRL_PIN(84, "CNV_RF_RESET_B"), + PINCTRL_PIN(85, "MODEM_CLKREQ"), + PINCTRL_PIN(86, "I2S2_RXD"), + PINCTRL_PIN(87, "I2S1_SCLK"), + PINCTRL_PIN(88, "GPPC_H_16"), + PINCTRL_PIN(89, "GPPC_H_17"), + PINCTRL_PIN(90, "GPPC_H_18"), + PINCTRL_PIN(91, "GPPC_H_19"), + PINCTRL_PIN(92, "GPPC_H_20"), + PINCTRL_PIN(93, "GPPC_H_21"), + PINCTRL_PIN(94, "GPPC_H_22"), + PINCTRL_PIN(95, "GPPC_H_23"), + /* GPP_D */ + PINCTRL_PIN(96, "SPI1_CSB_BK_0_SBK_0"), + PINCTRL_PIN(97, "SPI1_CLK_BK_1_SBK_1"), + PINCTRL_PIN(98, "SPI1_MISO_IO_1_BK_2_SBK_2"), + PINCTRL_PIN(99, "SPI1_MOSI_IO_0_BK_3_SBK_3"), + PINCTRL_PIN(100, "ISH_I2C0_SDA"), + PINCTRL_PIN(101, "ISH_I2C0_SCL"), + PINCTRL_PIN(102, "ISH_I2C1_SDA"), + PINCTRL_PIN(103, "ISH_I2C1_SCL"), + PINCTRL_PIN(104, "ISH_SPI_CSB_GSPI2_CS0B_TBT_LSX4_A"), + PINCTRL_PIN(105, "ISH_SPI_CLK_GSPI2_CLK_TBT_LSX4_B"), + PINCTRL_PIN(106, "ISH_SPI_MISO_GSPI2_MISO_TBT_LSX5_A"), + PINCTRL_PIN(107, "ISH_SPI_MOSI_GSPI2_MOSI_TBT_LSX5_B"), + PINCTRL_PIN(108, "ISH_UART0_RXD_I2C4B_SDA"), + PINCTRL_PIN(109, "ISH_UART0_TXD_I2C4B_SCL"), + PINCTRL_PIN(110, "ISH_UART0_RTSB_GSPI2_CS1B"), + PINCTRL_PIN(111, "ISH_UART0_CTSB_CNV_WCEN"), + PINCTRL_PIN(112, "SPI1_IO_2"), + PINCTRL_PIN(113, "SPI1_IO_3"), + PINCTRL_PIN(114, "I2S_MCLK"), + PINCTRL_PIN(115, "CNV_MFUART2_RXD"), + PINCTRL_PIN(116, "CNV_MFUART2_TXD"), + PINCTRL_PIN(117, "CNV_PA_BLANKING"), + PINCTRL_PIN(118, "I2C5_SDA_ISH_I2C2_SDA"), + PINCTRL_PIN(119, "I2C5_SCL_ISH_I2C2_SCL"), + PINCTRL_PIN(120, "GSPI2_CLK_LOOPBK"), + PINCTRL_PIN(121, "SPI1_CLK_LOOPBK"), + /* vGPIO */ + PINCTRL_PIN(122, "CNV_BTEN"), + PINCTRL_PIN(123, "CNV_WCEN"), + PINCTRL_PIN(124, "CNV_BT_HOST_WAKEB"), + PINCTRL_PIN(125, "CNV_BT_IF_SELECT"), + PINCTRL_PIN(126, "vCNV_BT_UART_TXD"), + PINCTRL_PIN(127, "vCNV_BT_UART_RXD"), + PINCTRL_PIN(128, "vCNV_BT_UART_CTS_B"), + PINCTRL_PIN(129, "vCNV_BT_UART_RTS_B"), + PINCTRL_PIN(130, "vCNV_MFUART1_TXD"), + PINCTRL_PIN(131, "vCNV_MFUART1_RXD"), + PINCTRL_PIN(132, "vCNV_MFUART1_CTS_B"), + PINCTRL_PIN(133, "vCNV_MFUART1_RTS_B"), + PINCTRL_PIN(134, "vUART0_TXD"), + PINCTRL_PIN(135, "vUART0_RXD"), + PINCTRL_PIN(136, "vUART0_CTS_B"), + PINCTRL_PIN(137, "vUART0_RTS_B"), + PINCTRL_PIN(138, "vISH_UART0_TXD"), + PINCTRL_PIN(139, "vISH_UART0_RXD"), + PINCTRL_PIN(140, "vISH_UART0_CTS_B"), + PINCTRL_PIN(141, "vISH_UART0_RTS_B"), + PINCTRL_PIN(142, "vCNV_BT_I2S_BCLK"), + PINCTRL_PIN(143, "vCNV_BT_I2S_WS_SYNC"), + PINCTRL_PIN(144, "vCNV_BT_I2S_SDO"), + PINCTRL_PIN(145, "vCNV_BT_I2S_SDI"), + PINCTRL_PIN(146, "vI2S2_SCLK"), + PINCTRL_PIN(147, "vI2S2_SFRM"), + PINCTRL_PIN(148, "vI2S2_TXD"), + PINCTRL_PIN(149, "vI2S2_RXD"), + PINCTRL_PIN(150, "vSD3_CD_B"), + /* GPP_C */ + PINCTRL_PIN(151, "GPPC_C_0"), + PINCTRL_PIN(152, "GPPC_C_1"), + PINCTRL_PIN(153, "GPPC_C_2"), + PINCTRL_PIN(154, "GPPC_C_3"), + PINCTRL_PIN(155, "GPPC_C_4"), + PINCTRL_PIN(156, "GPPC_C_5"), + PINCTRL_PIN(157, "SUSWARNB_SUSPWRDNACK"), + PINCTRL_PIN(158, "SUSACKB"), + PINCTRL_PIN(159, "UART0_RXD"), + PINCTRL_PIN(160, "UART0_TXD"), + PINCTRL_PIN(161, "UART0_RTSB"), + PINCTRL_PIN(162, "UART0_CTSB"), + PINCTRL_PIN(163, "UART1_RXD_ISH_UART1_RXD"), + PINCTRL_PIN(164, "UART1_TXD_ISH_UART1_TXD"), + PINCTRL_PIN(165, "UART1_RTSB_ISH_UART1_RTSB"), + PINCTRL_PIN(166, "UART1_CTSB_ISH_UART1_CTSB"), + PINCTRL_PIN(167, "I2C0_SDA"), + PINCTRL_PIN(168, "I2C0_SCL"), + PINCTRL_PIN(169, "I2C1_SDA"), + PINCTRL_PIN(170, "I2C1_SCL"), + PINCTRL_PIN(171, "UART2_RXD_CNV_MFUART0_RXD"), + PINCTRL_PIN(172, "UART2_TXD_CNV_MFUART0_TXD"), + PINCTRL_PIN(173, "UART2_RTSB_CNV_MFUART0_RTS_B"), + PINCTRL_PIN(174, "UART2_CTSB_CNV_MFUART0_CTS_B"), + /* HVCMOS */ + PINCTRL_PIN(175, "L_BKLTEN"), + PINCTRL_PIN(176, "L_BKLTCTL"), + PINCTRL_PIN(177, "L_VDDEN"), + PINCTRL_PIN(178, "SYS_PWROK"), + PINCTRL_PIN(179, "SYS_RESETB"), + PINCTRL_PIN(180, "MLK_RSTB"), + /* GPP_E */ + PINCTRL_PIN(181, "ISH_GP_0_IMGCLKOUT_0"), + PINCTRL_PIN(182, "ISH_GP_1"), + PINCTRL_PIN(183, "IMGCLKOUT_1"), + PINCTRL_PIN(184, "ISH_GP_2_SATA_DEVSLP_0"), + PINCTRL_PIN(185, "IMGCLKOUT_2"), + PINCTRL_PIN(186, "SATA_LEDB_SPI1_CS1B"), + PINCTRL_PIN(187, "IMGCLKOUT_3"), + PINCTRL_PIN(188, "ISH_GP_3_SATA_DEVSLP_1"), + PINCTRL_PIN(189, "FIVR_DIGPB_0"), + PINCTRL_PIN(190, "SML0CLK"), + PINCTRL_PIN(191, "SML0DATA"), + PINCTRL_PIN(192, "BSSB_LS3_RX"), + PINCTRL_PIN(193, "BSSB_LS3_TX"), + PINCTRL_PIN(194, "BSSB_LS0_RX"), + PINCTRL_PIN(195, "BSSB_LS0_TX"), + PINCTRL_PIN(196, "BSSB_LS1_RX"), + PINCTRL_PIN(197, "BSSB_LS1_TX"), + PINCTRL_PIN(198, "BSSB_LS2_RX"), + PINCTRL_PIN(199, "BSSB_LS2_TX"), + PINCTRL_PIN(200, "FIVR_DIGPB_1"), + PINCTRL_PIN(201, "CNV_BRI_DT"), + PINCTRL_PIN(202, "CNV_BRI_RSP"), + PINCTRL_PIN(203, "CNV_RGI_DT"), + PINCTRL_PIN(204, "CNV_RGI_RSP"), + /* GPP_G */ + PINCTRL_PIN(205, "SD3_CMD"), + PINCTRL_PIN(206, "SD3_D0"), + PINCTRL_PIN(207, "SD3_D1"), + PINCTRL_PIN(208, "SD3_D2"), + PINCTRL_PIN(209, "SD3_D3"), + PINCTRL_PIN(210, "SD3_CDB"), + PINCTRL_PIN(211, "SD3_CLK"), + PINCTRL_PIN(212, "SD3_WP"), +}; + +static const struct intel_padgroup icln_community0_gpps[] = { + ICL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP), /* SPI */ + ICL_GPP(1, 9, 34, 32), /* GPP_B */ + ICL_GPP(2, 35, 55, 64), /* GPP_A */ + ICL_GPP(3, 56, 63, 96), /* GPP_S */ + ICL_GPP(4, 64, 71, 128), /* GPP_R */ +}; + +static const struct intel_padgroup icln_community1_gpps[] = { + ICL_GPP(0, 72, 95, 160), /* GPP_H */ + ICL_GPP(1, 96, 121, 192), /* GPP_D */ + ICL_GPP(2, 122, 150, 224), /* vGPIO */ + ICL_GPP(3, 151, 174, 256), /* GPP_C */ +}; + +static const struct intel_padgroup icln_community4_gpps[] = { + ICL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + ICL_GPP(1, 181, 204, 288), /* GPP_E */ +}; + +static const struct intel_padgroup icln_community5_gpps[] = { + ICL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO), /* GPP_G */ +}; + +static const struct intel_community icln_communities[] = { + ICL_N_COMMUNITY(0, 0, 71, icln_community0_gpps), + ICL_N_COMMUNITY(1, 72, 174, icln_community1_gpps), + ICL_N_COMMUNITY(2, 175, 204, icln_community4_gpps), + ICL_N_COMMUNITY(3, 205, 212, icln_community5_gpps), +}; + +static const struct intel_pinctrl_soc_data icln_soc_data = { + .pins = icln_pins, + .npins = ARRAY_SIZE(icln_pins), + .communities = icln_communities, + .ncommunities = ARRAY_SIZE(icln_communities), +}; + static INTEL_PINCTRL_PM_OPS(icl_pinctrl_pm_ops); static const struct acpi_device_id icl_pinctrl_acpi_match[] = { { "INT3455", (kernel_ulong_t)&icllp_soc_data }, + { "INT34C3", (kernel_ulong_t)&icln_soc_data }, { } }; MODULE_DEVICE_TABLE(acpi, icl_pinctrl_acpi_match); diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 66db4ac5d169..8dca1ef04965 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -147,6 +147,13 @@ config PINCTRL_MT8183 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS +config PINCTRL_MT8186 + bool "Mediatek MT8186 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_PARIS + config PINCTRL_MT8192 bool "Mediatek MT8192 pin control" depends on OF diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 1e3931d924e7..29018d6ad0de 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o +obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index 5bfaa84839c7..526faaebaf77 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -605,6 +605,7 @@ static int mtk_build_functions(struct mtk_pinctrl *hw) int mtk_moore_pinctrl_probe(struct platform_device *pdev, const struct mtk_pin_soc *soc) { + struct device *dev = &pdev->dev; struct pinctrl_pin_desc *pins; struct mtk_pinctrl *hw; int err, i; @@ -616,11 +617,9 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev, hw->soc = soc; hw->dev = &pdev->dev; - if (!hw->soc->nbase_names) { - dev_err(&pdev->dev, + if (!hw->soc->nbase_names) + return dev_err_probe(dev, -EINVAL, "SoC should be assigned at least one register base\n"); - return -EINVAL; - } hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names, sizeof(*hw->base), GFP_KERNEL); @@ -665,17 +664,13 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev, /* Setup groups descriptions per SoC types */ err = mtk_build_groups(hw); - if (err) { - dev_err(&pdev->dev, "Failed to build groups\n"); - return err; - } + if (err) + return dev_err_probe(dev, err, "Failed to build groups\n"); /* Setup functions descriptions per SoC types */ err = mtk_build_functions(hw); - if (err) { - dev_err(&pdev->dev, "Failed to build functions\n"); - return err; - } + if (err) + return dev_err_probe(dev, err, "Failed to build functions\n"); /* For able to make pinctrl_claim_hogs, we must not enable pinctrl * until all groups and functions are being added one. @@ -691,10 +686,8 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev, /* Build gpiochip should be after pinctrl_enable is done */ err = mtk_build_gpiochip(hw); - if (err) { - dev_err(&pdev->dev, "Failed to add gpio_chip\n"); - return err; - } + if (err) + return dev_err_probe(dev, err, "Failed to add gpio_chip\n"); platform_set_drvdata(pdev, hw); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/mediatek/pinctrl-mt2701.c index 37228dd5103e..d1583b4fdd9d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c @@ -270,13 +270,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt2701_spec_pupd[] = { MTK_PIN_PUPD_SPEC_SR(261, 0x140, 8, 9, 10), /* ms1 ins */ }; -static int mt2701_spec_pull_set(struct regmap *regmap, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0) -{ - return mtk_pctrl_spec_pull_set_samereg(regmap, mt2701_spec_pupd, - ARRAY_SIZE(mt2701_spec_pupd), pin, align, isup, r1r0); -} - static const struct mtk_pin_ies_smt_set mt2701_ies_set[] = { MTK_PIN_IES_SMT_SPEC(0, 6, 0xb20, 0), MTK_PIN_IES_SMT_SPEC(7, 9, 0xb20, 1), @@ -436,18 +429,6 @@ static const struct mtk_pin_ies_smt_set mt2701_smt_set[] = { MTK_PIN_IES_SMT_SPEC(278, 278, 0xb70, 13), }; -static int mt2701_ies_smt_set(struct regmap *regmap, unsigned int pin, - unsigned char align, int value, enum pin_config_param arg) -{ - if (arg == PIN_CONFIG_INPUT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_ies_set, - ARRAY_SIZE(mt2701_ies_set), pin, align, value); - else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_smt_set, - ARRAY_SIZE(mt2701_smt_set), pin, align, value); - return -EINVAL; -} - static const struct mtk_spec_pinmux_set mt2701_spec_pinmux[] = { MTK_PINMUX_SPEC(22, 0xb10, 3), MTK_PINMUX_SPEC(23, 0xb10, 4), @@ -508,8 +489,14 @@ static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = { .n_grp_cls = ARRAY_SIZE(mt2701_drv_grp), .pin_drv_grp = mt2701_pin_drv, .n_pin_drv_grps = ARRAY_SIZE(mt2701_pin_drv), - .spec_pull_set = mt2701_spec_pull_set, - .spec_ies_smt_set = mt2701_ies_smt_set, + .spec_ies = mt2701_ies_set, + .n_spec_ies = ARRAY_SIZE(mt2701_ies_set), + .spec_pupd = mt2701_spec_pupd, + .n_spec_pupd = ARRAY_SIZE(mt2701_spec_pupd), + .spec_smt = mt2701_smt_set, + .n_spec_smt = ARRAY_SIZE(mt2701_smt_set), + .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, + .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, .spec_pinmux_set = mt2701_spec_pinmux_set, .spec_dir_set = mt2701_spec_dir_set, .dir_offset = 0x0000, @@ -534,20 +521,15 @@ static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = { }, }; -static int mt2701_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_pctrl_init(pdev, &mt2701_pinctrl_data, NULL); -} - static const struct of_device_id mt2701_pctrl_match[] = { - { .compatible = "mediatek,mt2701-pinctrl", }, - { .compatible = "mediatek,mt7623-pinctrl", }, + { .compatible = "mediatek,mt2701-pinctrl", .data = &mt2701_pinctrl_data }, + { .compatible = "mediatek,mt7623-pinctrl", .data = &mt2701_pinctrl_data }, {} }; MODULE_DEVICE_TABLE(of, mt2701_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { - .probe = mt2701_pinctrl_probe, + .probe = mtk_pctrl_common_probe, .driver = { .name = "mediatek-mt2701-pinctrl", .of_match_table = mt2701_pctrl_match, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c b/drivers/pinctrl/mediatek/pinctrl-mt2712.c index ba35fc6cc138..b921068f9e69 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c @@ -81,16 +81,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = { MTK_PIN_PUPD_SPEC_SR(142, 0xe60, 5, 4, 3) }; -static int mt2712_spec_pull_set(struct regmap *regmap, - unsigned int pin, - unsigned char align, - bool isup, - unsigned int r1r0) -{ - return mtk_pctrl_spec_pull_set_samereg(regmap, mt2712_spec_pupd, - ARRAY_SIZE(mt2712_spec_pupd), pin, align, isup, r1r0); -} - static const struct mtk_pin_ies_smt_set mt2712_smt_set[] = { MTK_PIN_IES_SMT_SPEC(0, 3, 0x900, 2), MTK_PIN_IES_SMT_SPEC(4, 7, 0x900, 0), @@ -285,19 +275,6 @@ static const struct mtk_pin_ies_smt_set mt2712_ies_set[] = { MTK_PIN_IES_SMT_SPEC(207, 209, 0x8b0, 15) }; -static int mt2712_ies_smt_set(struct regmap *regmap, unsigned int pin, - unsigned char align, - int value, enum pin_config_param arg) -{ - if (arg == PIN_CONFIG_INPUT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_ies_set, - ARRAY_SIZE(mt2712_ies_set), pin, align, value); - if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_smt_set, - ARRAY_SIZE(mt2712_smt_set), pin, align, value); - return -EINVAL; -} - static const struct mtk_drv_group_desc mt2712_drv_grp[] = { /* 0E4E8SR 4/8/12/16 */ MTK_DRV_GRP(4, 16, 1, 2, 4), @@ -563,8 +540,14 @@ static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = { .n_grp_cls = ARRAY_SIZE(mt2712_drv_grp), .pin_drv_grp = mt2712_pin_drv, .n_pin_drv_grps = ARRAY_SIZE(mt2712_pin_drv), - .spec_pull_set = mt2712_spec_pull_set, - .spec_ies_smt_set = mt2712_ies_smt_set, + .spec_ies = mt2712_ies_set, + .n_spec_ies = ARRAY_SIZE(mt2712_ies_set), + .spec_pupd = mt2712_spec_pupd, + .n_spec_pupd = ARRAY_SIZE(mt2712_spec_pupd), + .spec_smt = mt2712_smt_set, + .n_spec_smt = ARRAY_SIZE(mt2712_smt_set), + .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, + .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, .dir_offset = 0x0000, .pullen_offset = 0x0100, .pullsel_offset = 0x0200, @@ -587,21 +570,14 @@ static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = { }, }; -static int mt2712_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_pctrl_init(pdev, &mt2712_pinctrl_data, NULL); -} - static const struct of_device_id mt2712_pctrl_match[] = { - { - .compatible = "mediatek,mt2712-pinctrl", - }, + { .compatible = "mediatek,mt2712-pinctrl", .data = &mt2712_pinctrl_data }, { } }; MODULE_DEVICE_TABLE(of, mt2712_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { - .probe = mt2712_pinctrl_probe, + .probe = mtk_pctrl_common_probe, .driver = { .name = "mediatek-mt2712-pinctrl", .of_match_table = mt2712_pctrl_match, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6765.c b/drivers/pinctrl/mediatek/pinctrl-mt6765.c index 2c59d3936256..c57b19fcda03 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6765.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6765.c @@ -1082,21 +1082,16 @@ static const struct mtk_pin_soc mt6765_data = { }; static const struct of_device_id mt6765_pinctrl_of_match[] = { - { .compatible = "mediatek,mt6765-pinctrl", }, + { .compatible = "mediatek,mt6765-pinctrl", .data = &mt6765_data }, { } }; -static int mt6765_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_paris_pinctrl_probe(pdev, &mt6765_data); -} - static struct platform_driver mt6765_pinctrl_driver = { .driver = { .name = "mt6765-pinctrl", .of_match_table = mt6765_pinctrl_of_match, }, - .probe = mt6765_pinctrl_probe, + .probe = mtk_paris_pinctrl_probe, }; static int __init mt6765_pinctrl_init(void) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6779.c b/drivers/pinctrl/mediatek/pinctrl-mt6779.c index bb0851c73304..4ddf8bda6827 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6779.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c @@ -758,21 +758,16 @@ static const struct mtk_pin_soc mt6779_data = { }; static const struct of_device_id mt6779_pinctrl_of_match[] = { - { .compatible = "mediatek,mt6779-pinctrl", }, + { .compatible = "mediatek,mt6779-pinctrl", .data = &mt6779_data }, { } }; -static int mt6779_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_paris_pinctrl_probe(pdev, &mt6779_data); -} - static struct platform_driver mt6779_pinctrl_driver = { .driver = { .name = "mt6779-pinctrl", .of_match_table = mt6779_pinctrl_of_match, }, - .probe = mt6779_pinctrl_probe, + .probe = mtk_paris_pinctrl_probe, }; static int __init mt6779_pinctrl_init(void) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6797.c b/drivers/pinctrl/mediatek/pinctrl-mt6797.c index adebe4333ed9..53f240491259 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6797.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6797.c @@ -58,21 +58,16 @@ static const struct mtk_pin_soc mt6797_data = { }; static const struct of_device_id mt6797_pinctrl_of_match[] = { - { .compatible = "mediatek,mt6797-pinctrl", }, + { .compatible = "mediatek,mt6797-pinctrl", .data = &mt6797_data }, { } }; -static int mt6797_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_paris_pinctrl_probe(pdev, &mt6797_data); -} - static struct platform_driver mt6797_pinctrl_driver = { .driver = { .name = "mt6797-pinctrl", .of_match_table = mt6797_pinctrl_of_match, }, - .probe = mt6797_pinctrl_probe, + .probe = mtk_paris_pinctrl_probe, }; static int __init mt6797_pinctrl_init(void) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c index eaf5c76b14c7..91c530e7b00e 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c @@ -172,13 +172,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt8127_spec_pupd[] = { MTK_PIN_PUPD_SPEC_SR(142, 0xdc0, 2, 0, 1), /* EINT21 */ }; -static int mt8127_spec_pull_set(struct regmap *regmap, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0) -{ - return mtk_pctrl_spec_pull_set_samereg(regmap, mt8127_spec_pupd, - ARRAY_SIZE(mt8127_spec_pupd), pin, align, isup, r1r0); -} - static const struct mtk_pin_ies_smt_set mt8127_ies_set[] = { MTK_PIN_IES_SMT_SPEC(0, 9, 0x900, 0), MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 1), @@ -259,19 +252,6 @@ static const struct mtk_pin_ies_smt_set mt8127_smt_set[] = { MTK_PIN_IES_SMT_SPEC(142, 142, 0x920, 13), }; -static int mt8127_ies_smt_set(struct regmap *regmap, unsigned int pin, - unsigned char align, int value, enum pin_config_param arg) -{ - if (arg == PIN_CONFIG_INPUT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_ies_set, - ARRAY_SIZE(mt8127_ies_set), pin, align, value); - else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_smt_set, - ARRAY_SIZE(mt8127_smt_set), pin, align, value); - return -EINVAL; -} - - static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = { .pins = mtk_pins_mt8127, .npins = ARRAY_SIZE(mtk_pins_mt8127), @@ -279,8 +259,14 @@ static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = { .n_grp_cls = ARRAY_SIZE(mt8127_drv_grp), .pin_drv_grp = mt8127_pin_drv, .n_pin_drv_grps = ARRAY_SIZE(mt8127_pin_drv), - .spec_pull_set = mt8127_spec_pull_set, - .spec_ies_smt_set = mt8127_ies_smt_set, + .spec_ies = mt8127_ies_set, + .n_spec_ies = ARRAY_SIZE(mt8127_ies_set), + .spec_pupd = mt8127_spec_pupd, + .n_spec_pupd = ARRAY_SIZE(mt8127_spec_pupd), + .spec_smt = mt8127_smt_set, + .n_spec_smt = ARRAY_SIZE(mt8127_smt_set), + .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, + .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, .dir_offset = 0x0000, .pullen_offset = 0x0100, .pullsel_offset = 0x0200, @@ -303,18 +289,13 @@ static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = { }, }; -static int mt8127_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_pctrl_init(pdev, &mt8127_pinctrl_data, NULL); -} - static const struct of_device_id mt8127_pctrl_match[] = { - { .compatible = "mediatek,mt8127-pinctrl", }, + { .compatible = "mediatek,mt8127-pinctrl", .data = &mt8127_pinctrl_data }, { } }; static struct platform_driver mtk_pinctrl_driver = { - .probe = mt8127_pinctrl_probe, + .probe = mtk_pctrl_common_probe, .driver = { .name = "mediatek-mt8127-pinctrl", .of_match_table = mt8127_pctrl_match, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c index b8f4080aab45..562846756517 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -230,12 +230,14 @@ static const struct mtk_spec_pull_set spec_pupd[] = { SPEC_PULL(202, PUPD_BASE2+0xc0, 10, R0_BASE1, 12, R1_BASE2+0xc0, 10) }; -static int spec_pull_set(struct regmap *regmap, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0) +static int spec_pull_set(struct regmap *regmap, + const struct mtk_pinctrl_devdata *devdata, + unsigned int pin, bool isup, unsigned int r1r0) { unsigned int i; unsigned int reg_pupd, reg_set_r0, reg_set_r1; unsigned int reg_rst_r0, reg_rst_r1; + unsigned char align = devdata->port_align; bool find = false; for (i = 0; i < ARRAY_SIZE(spec_pupd); i++) { @@ -316,20 +318,13 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = { }, }; -static int mt8135_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_pctrl_init(pdev, &mt8135_pinctrl_data, NULL); -} - static const struct of_device_id mt8135_pctrl_match[] = { - { - .compatible = "mediatek,mt8135-pinctrl", - }, + { .compatible = "mediatek,mt8135-pinctrl", .data = &mt8135_pinctrl_data }, { } }; static struct platform_driver mtk_pinctrl_driver = { - .probe = mt8135_pinctrl_probe, + .probe = mtk_pctrl_common_probe, .driver = { .name = "mediatek-mt8135-pinctrl", .of_match_table = mt8135_pctrl_match, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8167.c b/drivers/pinctrl/mediatek/pinctrl-mt8167.c index ba12ef795e52..825167f5d020 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c @@ -186,13 +186,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt8167_spec_pupd[] = { MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0), }; -static int mt8167_spec_pull_set(struct regmap *regmap, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0) -{ - return mtk_pctrl_spec_pull_set_samereg(regmap, mt8167_spec_pupd, - ARRAY_SIZE(mt8167_spec_pupd), pin, align, isup, r1r0); -} - static const struct mtk_pin_ies_smt_set mt8167_ies_set[] = { MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2), MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3), @@ -292,18 +285,6 @@ static const struct mtk_pin_ies_smt_set mt8167_smt_set[] = { MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9), }; -static int mt8167_ies_smt_set(struct regmap *regmap, unsigned int pin, - unsigned char align, int value, enum pin_config_param arg) -{ - if (arg == PIN_CONFIG_INPUT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8167_ies_set, - ARRAY_SIZE(mt8167_ies_set), pin, align, value); - else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8167_smt_set, - ARRAY_SIZE(mt8167_smt_set), pin, align, value); - return -EINVAL; -} - static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = { .pins = mtk_pins_mt8167, .npins = ARRAY_SIZE(mtk_pins_mt8167), @@ -311,8 +292,14 @@ static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = { .n_grp_cls = ARRAY_SIZE(mt8167_drv_grp), .pin_drv_grp = mt8167_pin_drv, .n_pin_drv_grps = ARRAY_SIZE(mt8167_pin_drv), - .spec_pull_set = mt8167_spec_pull_set, - .spec_ies_smt_set = mt8167_ies_smt_set, + .spec_ies = mt8167_ies_set, + .n_spec_ies = ARRAY_SIZE(mt8167_ies_set), + .spec_pupd = mt8167_spec_pupd, + .n_spec_pupd = ARRAY_SIZE(mt8167_spec_pupd), + .spec_smt = mt8167_smt_set, + .n_spec_smt = ARRAY_SIZE(mt8167_smt_set), + .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, + .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, .dir_offset = 0x0000, .pullen_offset = 0x0500, .pullsel_offset = 0x0600, @@ -335,22 +322,15 @@ static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = { }, }; -static int mt8167_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_pctrl_init(pdev, &mt8167_pinctrl_data, NULL); -} - static const struct of_device_id mt8167_pctrl_match[] = { - { - .compatible = "mediatek,mt8167-pinctrl", - }, + { .compatible = "mediatek,mt8167-pinctrl", .data = &mt8167_pinctrl_data }, {} }; MODULE_DEVICE_TABLE(of, mt8167_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { - .probe = mt8167_pinctrl_probe, + .probe = mtk_pctrl_common_probe, .driver = { .name = "mediatek-mt8167-pinctrl", .of_match_table = mt8167_pctrl_match, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c index fc99df8a11c6..1d7d11a32e7d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -61,13 +61,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = { MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0) /* ms3 cmd */ }; -static int mt8173_spec_pull_set(struct regmap *regmap, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0) -{ - return mtk_pctrl_spec_pull_set_samereg(regmap, mt8173_spec_pupd, - ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0); -} - static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = { MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1), MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2), @@ -174,18 +167,6 @@ static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = { MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8) }; -static int mt8173_ies_smt_set(struct regmap *regmap, unsigned int pin, - unsigned char align, int value, enum pin_config_param arg) -{ - if (arg == PIN_CONFIG_INPUT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_ies_set, - ARRAY_SIZE(mt8173_ies_set), pin, align, value); - else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_smt_set, - ARRAY_SIZE(mt8173_smt_set), pin, align, value); - return -EINVAL; -} - static const struct mtk_drv_group_desc mt8173_drv_grp[] = { /* 0E4E8SR 4/8/12/16 */ MTK_DRV_GRP(4, 16, 1, 2, 4), @@ -319,8 +300,14 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = { .n_grp_cls = ARRAY_SIZE(mt8173_drv_grp), .pin_drv_grp = mt8173_pin_drv, .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv), - .spec_pull_set = mt8173_spec_pull_set, - .spec_ies_smt_set = mt8173_ies_smt_set, + .spec_ies = mt8173_ies_set, + .n_spec_ies = ARRAY_SIZE(mt8173_ies_set), + .spec_pupd = mt8173_spec_pupd, + .n_spec_pupd = ARRAY_SIZE(mt8173_spec_pupd), + .spec_smt = mt8173_smt_set, + .n_spec_smt = ARRAY_SIZE(mt8173_smt_set), + .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, + .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, .dir_offset = 0x0000, .pullen_offset = 0x0100, .pullsel_offset = 0x0200, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8183.c b/drivers/pinctrl/mediatek/pinctrl-mt8183.c index 60318339b618..fecb1e64fff4 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8183.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c @@ -567,22 +567,17 @@ static const struct mtk_pin_soc mt8183_data = { }; static const struct of_device_id mt8183_pinctrl_of_match[] = { - { .compatible = "mediatek,mt8183-pinctrl", }, + { .compatible = "mediatek,mt8183-pinctrl", .data = &mt8183_data }, { } }; -static int mt8183_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_paris_pinctrl_probe(pdev, &mt8183_data); -} - static struct platform_driver mt8183_pinctrl_driver = { .driver = { .name = "mt8183-pinctrl", .of_match_table = mt8183_pinctrl_of_match, .pm = &mtk_paris_pinctrl_pm_ops, }, - .probe = mt8183_pinctrl_probe, + .probe = mtk_paris_pinctrl_probe, }; static int __init mt8183_pinctrl_init(void) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8186.c b/drivers/pinctrl/mediatek/pinctrl-mt8186.c new file mode 100644 index 000000000000..a4dd5197abc1 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8186.c @@ -0,0 +1,1267 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 MediaTek Inc. + * + * Author: Guodong Liu <guodong.liu@mediatek.com> + * + */ + +#include "pinctrl-mtk-mt8186.h" +#include "pinctrl-paris.h" + +/* MT8186 have multiple bases to program pin configuration listed as the below: + * iocfg[0]:0x10005000, iocfg[1]:0x10002000, iocfg[2]:0x10002200, + * iocfg[3]:0x10002400, iocfg[4]:0x10002600, iocfg[5]:0x10002800, + * iocfg[6]:0x10002C00. + * _i_based could be used to indicate what base the pin should be mapped into. + */ + +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, 32, 0) + +#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, 32, 1) + +static const struct mtk_pin_field_calc mt8186_pin_mode_range[] = { + PIN_FIELD(0, 184, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt8186_pin_dir_range[] = { + PIN_FIELD(0, 184, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_di_range[] = { + PIN_FIELD(0, 184, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_do_range[] = { + PIN_FIELD(0, 184, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, 6, 0x0030, 0x10, 13, 1), + PIN_FIELD_BASE(1, 1, 6, 0x0030, 0x10, 14, 1), + PIN_FIELD_BASE(2, 2, 6, 0x0030, 0x10, 17, 1), + PIN_FIELD_BASE(3, 3, 6, 0x0030, 0x10, 18, 1), + PIN_FIELD_BASE(4, 4, 6, 0x0030, 0x10, 19, 1), + PIN_FIELD_BASE(5, 5, 6, 0x0030, 0x10, 20, 1), + PIN_FIELD_BASE(6, 6, 4, 0x0020, 0x10, 19, 1), + PIN_FIELD_BASE(7, 7, 4, 0x0020, 0x10, 20, 1), + PIN_FIELD_BASE(8, 8, 4, 0x0020, 0x10, 21, 1), + PIN_FIELD_BASE(9, 9, 4, 0x0020, 0x10, 22, 1), + PIN_FIELD_BASE(10, 10, 4, 0x0020, 0x10, 16, 1), + PIN_FIELD_BASE(11, 11, 4, 0x0020, 0x10, 17, 1), + PIN_FIELD_BASE(12, 12, 4, 0x0020, 0x10, 18, 1), + PIN_FIELD_BASE(13, 13, 3, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 3, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0030, 0x10, 15, 1), + PIN_FIELD_BASE(16, 16, 6, 0x0030, 0x10, 16, 1), + PIN_FIELD_BASE(17, 17, 5, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(18, 18, 5, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(19, 19, 5, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(20, 20, 5, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(21, 21, 5, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(22, 22, 5, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(23, 23, 5, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(24, 24, 5, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(25, 25, 5, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(26, 26, 5, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(27, 27, 5, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(28, 28, 5, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(29, 29, 6, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(30, 30, 6, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(31, 31, 6, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(32, 32, 2, 0x0040, 0x10, 25, 1), + PIN_FIELD_BASE(33, 33, 2, 0x0040, 0x10, 27, 1), + PIN_FIELD_BASE(34, 34, 2, 0x0040, 0x10, 26, 1), + PIN_FIELD_BASE(35, 35, 2, 0x0040, 0x10, 28, 1), + PIN_FIELD_BASE(36, 36, 2, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(37, 37, 2, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(38, 38, 2, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(39, 39, 2, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(40, 40, 2, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(41, 41, 2, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(42, 42, 2, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(43, 43, 2, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(44, 44, 5, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(45, 45, 5, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(46, 46, 5, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(47, 47, 5, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(48, 48, 2, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(49, 49, 2, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(50, 50, 2, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(51, 51, 2, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(52, 52, 3, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(53, 53, 3, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(54, 54, 3, 0x0040, 0x10, 21, 1), + PIN_FIELD_BASE(55, 55, 3, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(56, 56, 5, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(57, 57, 5, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(58, 58, 5, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(59, 59, 5, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(60, 60, 3, 0x0040, 0x10, 27, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0040, 0x10, 22, 1), + PIN_FIELD_BASE(62, 62, 3, 0x0040, 0x10, 28, 1), + PIN_FIELD_BASE(63, 63, 3, 0x0040, 0x10, 23, 1), + PIN_FIELD_BASE(64, 64, 3, 0x0040, 0x10, 24, 1), + PIN_FIELD_BASE(65, 65, 3, 0x0040, 0x10, 25, 1), + PIN_FIELD_BASE(66, 66, 3, 0x0040, 0x10, 26, 1), + PIN_FIELD_BASE(67, 67, 1, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(68, 68, 1, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(69, 69, 1, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(70, 70, 1, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(71, 71, 1, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(72, 72, 1, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(73, 73, 1, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(74, 74, 1, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(75, 75, 1, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(76, 76, 1, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(77, 77, 1, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(78, 78, 1, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(79, 79, 5, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(80, 80, 5, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(81, 81, 5, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(82, 82, 5, 0x0050, 0x10, 27, 1), + PIN_FIELD_BASE(83, 83, 6, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(85, 85, 3, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(86, 86, 3, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(87, 87, 3, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(88, 88, 3, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(89, 89, 3, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(90, 90, 3, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(91, 91, 3, 0x0040, 0x10, 29, 1), + PIN_FIELD_BASE(92, 92, 3, 0x0040, 0x10, 31, 1), + PIN_FIELD_BASE(93, 93, 3, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(94, 94, 3, 0x0040, 0x10, 30, 1), + PIN_FIELD_BASE(95, 95, 3, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(96, 96, 2, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(97, 97, 2, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(98, 98, 2, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(99, 99, 4, 0x0020, 0x10, 14, 1), + PIN_FIELD_BASE(100, 100, 4, 0x0020, 0x10, 15, 1), + PIN_FIELD_BASE(101, 101, 4, 0x0020, 0x10, 13, 1), + PIN_FIELD_BASE(102, 102, 4, 0x0020, 0x10, 12, 1), + PIN_FIELD_BASE(103, 103, 4, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, 4, 0x0020, 0x10, 1, 1), + PIN_FIELD_BASE(105, 105, 4, 0x0020, 0x10, 4, 1), + PIN_FIELD_BASE(106, 106, 4, 0x0020, 0x10, 5, 1), + PIN_FIELD_BASE(107, 107, 4, 0x0020, 0x10, 6, 1), + PIN_FIELD_BASE(108, 108, 4, 0x0020, 0x10, 7, 1), + PIN_FIELD_BASE(109, 109, 4, 0x0020, 0x10, 8, 1), + PIN_FIELD_BASE(110, 110, 4, 0x0020, 0x10, 9, 1), + PIN_FIELD_BASE(111, 111, 4, 0x0020, 0x10, 10, 1), + PIN_FIELD_BASE(112, 112, 4, 0x0020, 0x10, 11, 1), + PIN_FIELD_BASE(113, 113, 4, 0x0020, 0x10, 2, 1), + PIN_FIELD_BASE(114, 114, 4, 0x0020, 0x10, 3, 1), + PIN_FIELD_BASE(115, 115, 3, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(116, 116, 3, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(117, 117, 3, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(118, 118, 3, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(119, 119, 5, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(120, 120, 5, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(121, 121, 5, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(122, 122, 5, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(123, 123, 5, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(124, 124, 5, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(125, 125, 5, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(126, 126, 5, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, 3, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(128, 128, 3, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(129, 129, 5, 0x0050, 0x10, 28, 1), + PIN_FIELD_BASE(130, 130, 5, 0x0050, 0x10, 30, 1), + PIN_FIELD_BASE(131, 131, 5, 0x0050, 0x10, 29, 1), + PIN_FIELD_BASE(132, 132, 5, 0x0050, 0x10, 31, 1), + PIN_FIELD_BASE(133, 133, 1, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(134, 134, 1, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(135, 135, 6, 0x0030, 0x10, 21, 1), + PIN_FIELD_BASE(136, 136, 6, 0x0030, 0x10, 24, 1), + PIN_FIELD_BASE(137, 137, 1, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(138, 138, 1, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(139, 139, 2, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(140, 140, 2, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(141, 141, 3, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(142, 142, 3, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(143, 143, 6, 0x0030, 0x10, 22, 1), + PIN_FIELD_BASE(144, 144, 6, 0x0030, 0x10, 25, 1), + PIN_FIELD_BASE(145, 145, 6, 0x0030, 0x10, 23, 1), + PIN_FIELD_BASE(146, 146, 6, 0x0030, 0x10, 26, 1), + PIN_FIELD_BASE(147, 147, 4, 0x0020, 0x10, 23, 1), + PIN_FIELD_BASE(148, 148, 4, 0x0020, 0x10, 24, 1), + PIN_FIELD_BASE(149, 149, 4, 0x0020, 0x10, 25, 1), + PIN_FIELD_BASE(150, 150, 4, 0x0020, 0x10, 26, 1), + PIN_FIELD_BASE(151, 151, 4, 0x0020, 0x10, 27, 1), + PIN_FIELD_BASE(152, 152, 4, 0x0020, 0x10, 28, 1), + PIN_FIELD_BASE(153, 153, 4, 0x0020, 0x10, 29, 1), + PIN_FIELD_BASE(154, 154, 4, 0x0020, 0x10, 30, 1), + PIN_FIELD_BASE(155, 155, 4, 0x0020, 0x10, 31, 1), + PIN_FIELD_BASE(156, 156, 4, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(157, 157, 2, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(158, 158, 2, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(159, 159, 2, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(160, 160, 2, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(161, 161, 2, 0x0040, 0x10, 23, 1), + PIN_FIELD_BASE(162, 162, 2, 0x0040, 0x10, 24, 1), + PIN_FIELD_BASE(163, 163, 1, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(164, 164, 1, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(165, 165, 1, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(166, 166, 1, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(167, 167, 1, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(168, 168, 1, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(169, 169, 1, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(170, 170, 1, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(171, 171, 1, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(172, 172, 1, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(173, 173, 1, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(174, 174, 6, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(175, 175, 6, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(176, 176, 6, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(177, 177, 6, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(178, 178, 6, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 6, 0x0030, 0x10, 9, 1), + PIN_FIELD_BASE(180, 180, 6, 0x0030, 0x10, 10, 1), + PIN_FIELD_BASE(181, 181, 6, 0x0030, 0x10, 11, 1), + PIN_FIELD_BASE(182, 182, 6, 0x0030, 0x10, 12, 1), + PIN_FIELD_BASE(183, 183, 2, 0x0040, 0x10, 21, 1), + PIN_FIELD_BASE(184, 184, 2, 0x0040, 0x10, 22, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, 6, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 6, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(2, 2, 6, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(3, 3, 6, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(4, 4, 6, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, 6, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(6, 6, 4, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, 4, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(8, 8, 4, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(9, 9, 4, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(10, 10, 4, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, 4, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(12, 12, 4, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(13, 13, 3, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(14, 14, 3, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 6, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(17, 17, 5, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(18, 18, 5, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(19, 19, 5, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, 5, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(21, 21, 5, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(22, 22, 5, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(23, 23, 5, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(24, 24, 5, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(25, 25, 5, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(26, 26, 5, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(27, 27, 5, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, 5, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, 6, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(30, 30, 6, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(31, 31, 6, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(32, 32, 2, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(33, 33, 2, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(34, 34, 2, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(35, 35, 2, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(36, 36, 2, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, 2, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(38, 38, 2, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(39, 39, 2, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(40, 40, 2, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(41, 41, 2, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(42, 42, 2, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(43, 43, 2, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, 5, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(45, 45, 5, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(46, 46, 5, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(47, 47, 5, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(48, 48, 2, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(49, 49, 2, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(50, 50, 2, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(51, 51, 2, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(52, 52, 3, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(53, 53, 3, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(54, 54, 3, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(55, 55, 3, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(56, 56, 5, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(57, 57, 5, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(58, 58, 5, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(59, 59, 5, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(60, 60, 3, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(61, 61, 3, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(62, 62, 3, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(63, 63, 3, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(64, 64, 3, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(65, 65, 3, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(66, 66, 3, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(67, 67, 1, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(68, 68, 1, 0x00f0, 0x10, 0, 1), + PIN_FIELD_BASE(69, 69, 1, 0x00f0, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 1, 0x00f0, 0x10, 11, 1), + PIN_FIELD_BASE(71, 71, 1, 0x00f0, 0x10, 2, 1), + PIN_FIELD_BASE(72, 72, 1, 0x00f0, 0x10, 3, 1), + PIN_FIELD_BASE(73, 73, 1, 0x00f0, 0x10, 4, 1), + PIN_FIELD_BASE(74, 74, 1, 0x00f0, 0x10, 5, 1), + PIN_FIELD_BASE(75, 75, 1, 0x00f0, 0x10, 6, 1), + PIN_FIELD_BASE(76, 76, 1, 0x00f0, 0x10, 7, 1), + PIN_FIELD_BASE(77, 77, 1, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(78, 78, 1, 0x00f0, 0x10, 9, 1), + PIN_FIELD_BASE(79, 79, 5, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(80, 80, 5, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(81, 81, 5, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(82, 82, 5, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(83, 83, 6, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(84, 84, 3, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(85, 85, 3, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(86, 86, 3, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(87, 87, 3, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, 3, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, 3, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(90, 90, 3, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(91, 91, 3, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(92, 92, 3, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(93, 93, 3, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(94, 94, 3, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(95, 95, 3, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(96, 96, 2, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(97, 97, 2, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(98, 98, 2, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(99, 99, 4, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(100, 100, 4, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(101, 101, 4, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(102, 102, 4, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(103, 103, 4, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(104, 104, 4, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(105, 105, 4, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(106, 106, 4, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(107, 107, 4, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(108, 108, 4, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(109, 109, 4, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(110, 110, 4, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(111, 111, 4, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(112, 112, 4, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(113, 113, 4, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(114, 114, 4, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(115, 115, 3, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(116, 116, 3, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(117, 117, 3, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(118, 118, 3, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(119, 119, 5, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(120, 120, 5, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(121, 121, 5, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(122, 122, 5, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(123, 123, 5, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(124, 124, 5, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(125, 125, 5, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(126, 126, 5, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, 3, 0x00e0, 0x10, 12, 1), + PIN_FIELD_BASE(128, 128, 3, 0x00e0, 0x10, 14, 1), + PIN_FIELD_BASE(129, 129, 5, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(130, 130, 5, 0x00e0, 0x10, 13, 1), + PIN_FIELD_BASE(131, 131, 5, 0x00e0, 0x10, 12, 1), + PIN_FIELD_BASE(132, 132, 5, 0x00e0, 0x10, 14, 1), + PIN_FIELD_BASE(133, 133, 1, 0x00f0, 0x10, 15, 1), + PIN_FIELD_BASE(134, 134, 1, 0x00f0, 0x10, 17, 1), + PIN_FIELD_BASE(135, 135, 6, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(136, 136, 6, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(137, 137, 1, 0x00f0, 0x10, 16, 1), + PIN_FIELD_BASE(138, 138, 1, 0x00f0, 0x10, 18, 1), + PIN_FIELD_BASE(139, 139, 2, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(140, 140, 2, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(141, 141, 3, 0x00e0, 0x10, 13, 1), + PIN_FIELD_BASE(142, 142, 3, 0x00e0, 0x10, 15, 1), + PIN_FIELD_BASE(143, 143, 6, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(144, 144, 6, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(145, 145, 6, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(146, 146, 6, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(147, 147, 4, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(148, 148, 4, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(149, 149, 4, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(150, 150, 4, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(151, 151, 4, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(152, 152, 4, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(153, 153, 4, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(154, 154, 4, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(155, 155, 4, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(156, 156, 4, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(157, 157, 2, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(158, 158, 2, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(159, 159, 2, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(160, 160, 2, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(161, 161, 2, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(162, 162, 2, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(163, 163, 1, 0x00f0, 0x10, 14, 1), + PIN_FIELD_BASE(164, 164, 1, 0x00f0, 0x10, 12, 1), + PIN_FIELD_BASE(165, 165, 1, 0x00f0, 0x10, 12, 1), + PIN_FIELD_BASE(166, 166, 1, 0x00f0, 0x10, 13, 1), + PIN_FIELD_BASE(167, 167, 1, 0x00f0, 0x10, 13, 1), + PIN_FIELD_BASE(168, 168, 1, 0x00f0, 0x10, 12, 1), + PIN_FIELD_BASE(169, 169, 1, 0x00f0, 0x10, 14, 1), + PIN_FIELD_BASE(170, 170, 1, 0x00f0, 0x10, 13, 1), + PIN_FIELD_BASE(171, 171, 1, 0x00f0, 0x10, 13, 1), + PIN_FIELD_BASE(172, 172, 1, 0x00f0, 0x10, 14, 1), + PIN_FIELD_BASE(173, 173, 1, 0x00f0, 0x10, 12, 1), + PIN_FIELD_BASE(174, 174, 6, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(175, 175, 6, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(176, 176, 6, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(177, 177, 6, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(178, 178, 6, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(179, 179, 6, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(180, 180, 6, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(181, 181, 6, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(182, 182, 6, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(183, 183, 2, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(184, 184, 2, 0x0090, 0x10, 10, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_pu_range[] = { + PIN_FIELD_BASE(0, 0, 6, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(1, 1, 6, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(2, 2, 6, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(3, 3, 6, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(4, 4, 6, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(5, 5, 6, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(6, 6, 4, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(7, 7, 4, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(8, 8, 4, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(9, 9, 4, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(10, 10, 4, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(11, 11, 4, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(12, 12, 4, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(13, 13, 3, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 3, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(16, 16, 6, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(17, 17, 5, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(18, 18, 5, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(19, 19, 5, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(20, 20, 5, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(21, 21, 5, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(22, 22, 5, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(23, 23, 5, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(24, 24, 5, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(25, 25, 5, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(26, 26, 5, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(27, 27, 5, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(28, 28, 5, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(29, 29, 6, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(30, 30, 6, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(31, 31, 6, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(32, 32, 2, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(33, 33, 2, 0x0060, 0x10, 27, 1), + PIN_FIELD_BASE(34, 34, 2, 0x0060, 0x10, 26, 1), + PIN_FIELD_BASE(35, 35, 2, 0x0060, 0x10, 28, 1), + PIN_FIELD_BASE(36, 36, 2, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(37, 37, 2, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(38, 38, 2, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(39, 39, 2, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(40, 40, 2, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(41, 41, 2, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(42, 42, 2, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(43, 43, 2, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(44, 44, 5, 0x0090, 0x10, 28, 1), + PIN_FIELD_BASE(45, 45, 5, 0x0090, 0x10, 29, 1), + PIN_FIELD_BASE(46, 46, 5, 0x0090, 0x10, 31, 1), + PIN_FIELD_BASE(47, 47, 5, 0x0090, 0x10, 30, 1), + PIN_FIELD_BASE(48, 48, 2, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(49, 49, 2, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(50, 50, 2, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(51, 51, 2, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(52, 52, 3, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(53, 53, 3, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(54, 54, 3, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(55, 55, 3, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(56, 56, 5, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(57, 57, 5, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(58, 58, 5, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(59, 59, 5, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(60, 60, 3, 0x0080, 0x10, 21, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(62, 62, 3, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(63, 63, 3, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(64, 64, 3, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(65, 65, 3, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(66, 66, 3, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(83, 83, 6, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(90, 90, 3, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(91, 91, 3, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(92, 92, 3, 0x0080, 0x10, 25, 1), + PIN_FIELD_BASE(93, 93, 3, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(94, 94, 3, 0x0080, 0x10, 24, 1), + PIN_FIELD_BASE(95, 95, 3, 0x0080, 0x10, 26, 1), + PIN_FIELD_BASE(96, 96, 2, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(97, 97, 2, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(98, 98, 2, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(99, 99, 4, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(100, 100, 4, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(101, 101, 4, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(102, 102, 4, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(103, 103, 4, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, 4, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(105, 105, 4, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(106, 106, 4, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(107, 107, 4, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(108, 108, 4, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(109, 109, 4, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(110, 110, 4, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(111, 111, 4, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(112, 112, 4, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(113, 113, 4, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(114, 114, 4, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(115, 115, 3, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(116, 116, 3, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(117, 117, 3, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(118, 118, 3, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(119, 119, 5, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(120, 120, 5, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(121, 121, 5, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(122, 122, 5, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(123, 123, 5, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(124, 124, 5, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(125, 125, 5, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(126, 126, 5, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, 3, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(128, 128, 3, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(129, 129, 5, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(130, 130, 5, 0x0090, 0x10, 26, 1), + PIN_FIELD_BASE(131, 131, 5, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(132, 132, 5, 0x0090, 0x10, 27, 1), + PIN_FIELD_BASE(133, 133, 1, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(134, 134, 1, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(135, 135, 6, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(136, 136, 6, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(137, 137, 1, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(138, 138, 1, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(139, 139, 2, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(140, 140, 2, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(141, 141, 3, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(142, 142, 3, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(143, 143, 6, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(144, 144, 6, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(145, 145, 6, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(146, 146, 6, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(147, 147, 4, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(148, 148, 4, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(149, 149, 4, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(150, 150, 4, 0x0060, 0x10, 26, 1), + PIN_FIELD_BASE(151, 151, 4, 0x0060, 0x10, 27, 1), + PIN_FIELD_BASE(152, 152, 4, 0x0060, 0x10, 28, 1), + PIN_FIELD_BASE(153, 153, 4, 0x0060, 0x10, 29, 1), + PIN_FIELD_BASE(154, 154, 4, 0x0060, 0x10, 30, 1), + PIN_FIELD_BASE(155, 155, 4, 0x0060, 0x10, 31, 1), + PIN_FIELD_BASE(156, 156, 4, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(157, 157, 2, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(158, 158, 2, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(159, 159, 2, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(160, 160, 2, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(161, 161, 2, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(162, 162, 2, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(163, 163, 1, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(164, 164, 1, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(165, 165, 1, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(166, 166, 1, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(167, 167, 1, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(168, 168, 1, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(169, 169, 1, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(170, 170, 1, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(171, 171, 1, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(172, 172, 1, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(173, 173, 1, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(174, 174, 6, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(175, 175, 6, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(176, 176, 6, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(177, 177, 6, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(178, 178, 6, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 6, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(180, 180, 6, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(181, 181, 6, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(182, 182, 6, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(183, 183, 2, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(184, 184, 2, 0x0060, 0x10, 22, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_pd_range[] = { + PIN_FIELD_BASE(0, 0, 6, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(1, 1, 6, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(2, 2, 6, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(3, 3, 6, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(4, 4, 6, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(5, 5, 6, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(6, 6, 4, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(7, 7, 4, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(8, 8, 4, 0x0040, 0x10, 21, 1), + PIN_FIELD_BASE(9, 9, 4, 0x0040, 0x10, 22, 1), + PIN_FIELD_BASE(10, 10, 4, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(11, 11, 4, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(12, 12, 4, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(13, 13, 3, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 3, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(16, 16, 6, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(17, 17, 5, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(18, 18, 5, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(19, 19, 5, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(20, 20, 5, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(21, 21, 5, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(22, 22, 5, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(23, 23, 5, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(24, 24, 5, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(25, 25, 5, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(26, 26, 5, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(27, 27, 5, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(28, 28, 5, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(29, 29, 6, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(30, 30, 6, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(31, 31, 6, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(32, 32, 2, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(33, 33, 2, 0x0050, 0x10, 27, 1), + PIN_FIELD_BASE(34, 34, 2, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(35, 35, 2, 0x0050, 0x10, 28, 1), + PIN_FIELD_BASE(36, 36, 2, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(37, 37, 2, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(38, 38, 2, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(39, 39, 2, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(40, 40, 2, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(41, 41, 2, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(42, 42, 2, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(43, 43, 2, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(44, 44, 5, 0x0070, 0x10, 28, 1), + PIN_FIELD_BASE(45, 45, 5, 0x0070, 0x10, 29, 1), + PIN_FIELD_BASE(46, 46, 5, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(47, 47, 5, 0x0070, 0x10, 30, 1), + PIN_FIELD_BASE(48, 48, 2, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(49, 49, 2, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(50, 50, 2, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(51, 51, 2, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(52, 52, 3, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(53, 53, 3, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(54, 54, 3, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(55, 55, 3, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(56, 56, 5, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(57, 57, 5, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(58, 58, 5, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(59, 59, 5, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(60, 60, 3, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(62, 62, 3, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(63, 63, 3, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(64, 64, 3, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(65, 65, 3, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(66, 66, 3, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(83, 83, 6, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(90, 90, 3, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(91, 91, 3, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(92, 92, 3, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(93, 93, 3, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(94, 94, 3, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(95, 95, 3, 0x0060, 0x10, 26, 1), + PIN_FIELD_BASE(96, 96, 2, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(97, 97, 2, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(98, 98, 2, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(99, 99, 4, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(100, 100, 4, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(101, 101, 4, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(102, 102, 4, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(103, 103, 4, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, 4, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(105, 105, 4, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(106, 106, 4, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(107, 107, 4, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(108, 108, 4, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(109, 109, 4, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(110, 110, 4, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(111, 111, 4, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(112, 112, 4, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(113, 113, 4, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(114, 114, 4, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(115, 115, 3, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(116, 116, 3, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(117, 117, 3, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(118, 118, 3, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(119, 119, 5, 0x0070, 0x10, 22, 1), + PIN_FIELD_BASE(120, 120, 5, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(121, 121, 5, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(122, 122, 5, 0x0070, 0x10, 21, 1), + PIN_FIELD_BASE(123, 123, 5, 0x0070, 0x10, 23, 1), + PIN_FIELD_BASE(124, 124, 5, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(125, 125, 5, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(126, 126, 5, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, 3, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(128, 128, 3, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(129, 129, 5, 0x0070, 0x10, 24, 1), + PIN_FIELD_BASE(130, 130, 5, 0x0070, 0x10, 26, 1), + PIN_FIELD_BASE(131, 131, 5, 0x0070, 0x10, 25, 1), + PIN_FIELD_BASE(132, 132, 5, 0x0070, 0x10, 27, 1), + PIN_FIELD_BASE(133, 133, 1, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(134, 134, 1, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(135, 135, 6, 0x0040, 0x10, 21, 1), + PIN_FIELD_BASE(136, 136, 6, 0x0040, 0x10, 24, 1), + PIN_FIELD_BASE(137, 137, 1, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(138, 138, 1, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(139, 139, 2, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(140, 140, 2, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(141, 141, 3, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(142, 142, 3, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(143, 143, 6, 0x0040, 0x10, 22, 1), + PIN_FIELD_BASE(144, 144, 6, 0x0040, 0x10, 25, 1), + PIN_FIELD_BASE(145, 145, 6, 0x0040, 0x10, 23, 1), + PIN_FIELD_BASE(146, 146, 6, 0x0040, 0x10, 26, 1), + PIN_FIELD_BASE(147, 147, 4, 0x0040, 0x10, 23, 1), + PIN_FIELD_BASE(148, 148, 4, 0x0040, 0x10, 24, 1), + PIN_FIELD_BASE(149, 149, 4, 0x0040, 0x10, 25, 1), + PIN_FIELD_BASE(150, 150, 4, 0x0040, 0x10, 26, 1), + PIN_FIELD_BASE(151, 151, 4, 0x0040, 0x10, 27, 1), + PIN_FIELD_BASE(152, 152, 4, 0x0040, 0x10, 28, 1), + PIN_FIELD_BASE(153, 153, 4, 0x0040, 0x10, 29, 1), + PIN_FIELD_BASE(154, 154, 4, 0x0040, 0x10, 30, 1), + PIN_FIELD_BASE(155, 155, 4, 0x0040, 0x10, 31, 1), + PIN_FIELD_BASE(156, 156, 4, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(157, 157, 2, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(158, 158, 2, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(159, 159, 2, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(160, 160, 2, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(161, 161, 2, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(162, 162, 2, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(163, 163, 1, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(164, 164, 1, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(165, 165, 1, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(166, 166, 1, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(167, 167, 1, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(168, 168, 1, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(169, 169, 1, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(170, 170, 1, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(171, 171, 1, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(172, 172, 1, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(173, 173, 1, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(174, 174, 6, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(175, 175, 6, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(176, 176, 6, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(177, 177, 6, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(178, 178, 6, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 6, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(180, 180, 6, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(181, 181, 6, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(182, 182, 6, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(183, 183, 2, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(184, 184, 2, 0x0050, 0x10, 22, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_pupd_range[] = { + PIN_FIELD_BASE(67, 67, 1, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(68, 68, 1, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(69, 69, 1, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 1, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(71, 71, 1, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(72, 72, 1, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(73, 73, 1, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(74, 74, 1, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(75, 75, 1, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(76, 76, 1, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(77, 77, 1, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(78, 78, 1, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(79, 79, 5, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(80, 80, 5, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(81, 81, 5, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(82, 82, 5, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(85, 85, 3, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(86, 86, 3, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(87, 87, 3, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, 3, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, 3, 0x0070, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_r0_range[] = { + PIN_FIELD_BASE(67, 67, 1, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(68, 68, 1, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(69, 69, 1, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 1, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(71, 71, 1, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(72, 72, 1, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(73, 73, 1, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(74, 74, 1, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(75, 75, 1, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(76, 76, 1, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(77, 77, 1, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(78, 78, 1, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(79, 79, 5, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(80, 80, 5, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(81, 81, 5, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(82, 82, 5, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(85, 85, 3, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(86, 86, 3, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(87, 87, 3, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, 3, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, 3, 0x0090, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_r1_range[] = { + PIN_FIELD_BASE(67, 67, 1, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(68, 68, 1, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(69, 69, 1, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 1, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(71, 71, 1, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(72, 72, 1, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(73, 73, 1, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(74, 74, 1, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(75, 75, 1, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(76, 76, 1, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(77, 77, 1, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(78, 78, 1, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(79, 79, 5, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(80, 80, 5, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(81, 81, 5, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(82, 82, 5, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(84, 84, 3, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(85, 85, 3, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(86, 86, 3, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(87, 87, 3, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, 3, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, 3, 0x00a0, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, 6, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(1, 1, 6, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(2, 2, 6, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(3, 3, 6, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(4, 4, 6, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(5, 5, 6, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(6, 6, 4, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(7, 7, 4, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(8, 8, 4, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(9, 9, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(10, 10, 4, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(11, 11, 4, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(12, 12, 4, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(13, 13, 3, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(14, 14, 3, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(15, 15, 6, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(16, 16, 6, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(17, 17, 5, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(18, 18, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(19, 19, 5, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(20, 20, 5, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(21, 21, 5, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(22, 22, 5, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(23, 23, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(24, 24, 5, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(25, 25, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(26, 26, 5, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(27, 27, 5, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(28, 28, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(29, 29, 6, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(30, 30, 6, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(31, 31, 6, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(32, 32, 2, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(33, 33, 2, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(34, 34, 2, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(35, 35, 2, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(36, 36, 2, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(37, 37, 2, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(38, 38, 2, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(39, 39, 2, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(40, 40, 2, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(41, 41, 2, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(42, 42, 2, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(43, 43, 2, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(44, 44, 5, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(45, 45, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(46, 46, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(47, 47, 5, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(48, 48, 2, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(49, 49, 2, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(50, 50, 2, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(51, 51, 2, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(52, 52, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(53, 53, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(54, 54, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(55, 55, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(56, 56, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(57, 57, 5, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(58, 58, 5, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(59, 59, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(60, 60, 3, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(61, 61, 3, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(62, 62, 3, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(63, 63, 3, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(64, 64, 3, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(65, 65, 3, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(66, 66, 3, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(67, 67, 1, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(68, 68, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(69, 69, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(70, 70, 1, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(71, 71, 1, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(72, 72, 1, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(73, 73, 1, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(74, 74, 1, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(75, 75, 1, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(76, 76, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(77, 77, 1, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(78, 78, 1, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(79, 79, 5, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(80, 80, 5, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(81, 81, 5, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(82, 82, 5, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(83, 83, 6, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(84, 84, 3, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(85, 85, 3, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(86, 86, 3, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(87, 87, 3, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(88, 88, 3, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(89, 89, 3, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(90, 90, 3, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(91, 91, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(92, 92, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(93, 93, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(94, 94, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(95, 95, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(96, 96, 2, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(97, 97, 2, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(98, 98, 2, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(99, 99, 4, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(100, 100, 4, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(101, 101, 4, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(102, 102, 4, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(103, 103, 4, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(104, 104, 4, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(105, 105, 4, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(106, 106, 4, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(107, 107, 4, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(108, 108, 4, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(109, 109, 4, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(110, 110, 4, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(111, 111, 4, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(112, 112, 4, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(113, 113, 4, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(114, 114, 4, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(115, 115, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(116, 116, 3, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(117, 117, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(118, 118, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(119, 119, 5, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(120, 120, 5, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(121, 121, 5, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(122, 122, 5, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(123, 123, 5, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(124, 124, 5, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(125, 125, 5, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(126, 126, 5, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(127, 127, 3, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(128, 128, 3, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(129, 129, 5, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(130, 130, 5, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(131, 131, 5, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(132, 132, 5, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(133, 133, 1, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(134, 134, 1, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(135, 135, 6, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(136, 136, 6, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(137, 137, 1, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(138, 138, 1, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(139, 139, 2, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(140, 140, 2, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(141, 141, 3, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(142, 142, 3, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(143, 143, 6, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(144, 144, 6, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(145, 145, 6, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(146, 146, 6, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(147, 147, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(148, 148, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(149, 149, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(150, 150, 4, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(151, 151, 4, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(152, 152, 4, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(153, 153, 4, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(154, 154, 4, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(155, 155, 4, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(156, 156, 4, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(157, 157, 2, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(158, 158, 2, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(159, 159, 2, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(160, 160, 2, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(161, 161, 2, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(162, 162, 2, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(163, 163, 1, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(165, 165, 1, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(166, 166, 1, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(167, 167, 1, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(168, 168, 1, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(169, 169, 1, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(170, 170, 1, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(171, 171, 1, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(172, 172, 1, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(173, 173, 1, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(174, 174, 6, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(175, 175, 6, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(176, 176, 6, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(177, 177, 6, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(178, 178, 6, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(179, 179, 6, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(180, 180, 6, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(181, 181, 6, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(182, 182, 6, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(183, 183, 2, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(184, 184, 2, 0x0010, 0x10, 0, 3), +}; + +static const struct mtk_pin_field_calc mt8186_pin_drv_adv_range[] = { + PIN_FIELD_BASE(127, 127, 3, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(128, 128, 3, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(129, 129, 5, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(130, 130, 5, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(131, 131, 5, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(132, 132, 5, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(133, 133, 1, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(134, 134, 1, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(135, 135, 6, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(136, 136, 6, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(137, 137, 1, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(138, 138, 1, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(139, 139, 2, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(140, 140, 2, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(141, 141, 3, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(142, 142, 3, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(143, 143, 6, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(144, 144, 6, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(145, 145, 6, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(146, 146, 6, 0x0020, 0x10, 15, 3), +}; + +static const struct mtk_pin_field_calc mt8186_pin_rsel_range[] = { + PIN_FIELD_BASE(127, 127, 3, 0x00d0, 0x10, 0, 2), + PIN_FIELD_BASE(128, 128, 3, 0x00d0, 0x10, 4, 2), + PIN_FIELD_BASE(129, 129, 5, 0x00d0, 0x10, 0, 2), + PIN_FIELD_BASE(130, 130, 5, 0x00d0, 0x10, 4, 2), + PIN_FIELD_BASE(131, 131, 5, 0x00d0, 0x10, 2, 2), + PIN_FIELD_BASE(132, 132, 5, 0x00d0, 0x10, 6, 2), + PIN_FIELD_BASE(133, 133, 1, 0x00e0, 0x10, 0, 2), + PIN_FIELD_BASE(134, 134, 1, 0x00e0, 0x10, 4, 2), + PIN_FIELD_BASE(135, 135, 6, 0x0070, 0x10, 0, 2), + PIN_FIELD_BASE(136, 136, 6, 0x0070, 0x10, 6, 2), + PIN_FIELD_BASE(137, 137, 1, 0x00e0, 0x10, 2, 2), + PIN_FIELD_BASE(138, 138, 1, 0x00e0, 0x10, 6, 2), + PIN_FIELD_BASE(139, 139, 2, 0x0080, 0x10, 0, 2), + PIN_FIELD_BASE(140, 140, 2, 0x0080, 0x10, 2, 2), + PIN_FIELD_BASE(141, 141, 3, 0x00d0, 0x10, 2, 2), + PIN_FIELD_BASE(142, 142, 3, 0x00d0, 0x10, 6, 2), + PIN_FIELD_BASE(143, 143, 6, 0x0070, 0x10, 2, 2), + PIN_FIELD_BASE(144, 144, 6, 0x0070, 0x10, 8, 2), + PIN_FIELD_BASE(145, 145, 6, 0x0070, 0x10, 4, 2), + PIN_FIELD_BASE(146, 146, 6, 0x0070, 0x10, 10, 2), +}; + +static const struct mtk_pin_rsel mt8186_pin_rsel_val_range[] = { + PIN_RSEL(127, 128, 0x0, 75000, 75000), + PIN_RSEL(127, 128, 0x1, 10000, 75000), + PIN_RSEL(127, 128, 0x2, 5000, 5000), + PIN_RSEL(127, 128, 0x3, 1000, 5000), + PIN_RSEL(129, 130, 0x0, 75000, 75000), + PIN_RSEL(129, 130, 0x1, 10000, 75000), + PIN_RSEL(129, 130, 0x2, 5000, 5000), + PIN_RSEL(129, 130, 0x3, 1000, 5000), + PIN_RSEL(131, 132, 0x0, 75000, 75000), + PIN_RSEL(131, 132, 0x1, 10000, 75000), + PIN_RSEL(131, 132, 0x2, 5000, 5000), + PIN_RSEL(131, 132, 0x3, 1000, 5000), + PIN_RSEL(133, 134, 0x0, 75000, 75000), + PIN_RSEL(133, 134, 0x1, 10000, 75000), + PIN_RSEL(133, 134, 0x2, 5000, 5000), + PIN_RSEL(133, 134, 0x3, 1000, 5000), + PIN_RSEL(135, 136, 0x0, 75000, 75000), + PIN_RSEL(135, 136, 0x1, 10000, 75000), + PIN_RSEL(135, 136, 0x2, 5000, 5000), + PIN_RSEL(135, 136, 0x3, 1000, 5000), + PIN_RSEL(137, 138, 0x0, 75000, 75000), + PIN_RSEL(137, 138, 0x1, 10000, 75000), + PIN_RSEL(137, 138, 0x2, 5000, 5000), + PIN_RSEL(137, 138, 0x3, 1000, 5000), + PIN_RSEL(139, 140, 0x0, 75000, 75000), + PIN_RSEL(139, 140, 0x1, 10000, 75000), + PIN_RSEL(139, 140, 0x2, 5000, 5000), + PIN_RSEL(139, 140, 0x3, 1000, 5000), + PIN_RSEL(141, 142, 0x0, 75000, 75000), + PIN_RSEL(141, 142, 0x1, 10000, 75000), + PIN_RSEL(141, 142, 0x2, 5000, 5000), + PIN_RSEL(141, 142, 0x3, 1000, 5000), + PIN_RSEL(143, 144, 0x0, 75000, 75000), + PIN_RSEL(143, 144, 0x1, 10000, 75000), + PIN_RSEL(143, 144, 0x2, 5000, 5000), + PIN_RSEL(143, 144, 0x3, 1000, 5000), + PIN_RSEL(145, 146, 0x0, 75000, 75000), + PIN_RSEL(145, 146, 0x1, 10000, 75000), + PIN_RSEL(145, 146, 0x2, 5000, 5000), + PIN_RSEL(145, 146, 0x3, 1000, 5000), +}; + +static const unsigned int mt8186_pull_type[] = { + MTK_PULL_PU_PD_TYPE,/*0*/ MTK_PULL_PU_PD_TYPE,/*1*/ + MTK_PULL_PU_PD_TYPE,/*2*/ MTK_PULL_PU_PD_TYPE,/*3*/ + MTK_PULL_PU_PD_TYPE,/*4*/ MTK_PULL_PU_PD_TYPE,/*5*/ + MTK_PULL_PU_PD_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE,/*7*/ + MTK_PULL_PU_PD_TYPE,/*8*/ MTK_PULL_PU_PD_TYPE,/*9*/ + MTK_PULL_PU_PD_TYPE,/*10*/ MTK_PULL_PU_PD_TYPE,/*11*/ + MTK_PULL_PU_PD_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE,/*13*/ + MTK_PULL_PU_PD_TYPE,/*14*/ MTK_PULL_PU_PD_TYPE,/*15*/ + MTK_PULL_PU_PD_TYPE,/*16*/ MTK_PULL_PU_PD_TYPE,/*17*/ + MTK_PULL_PU_PD_TYPE,/*18*/ MTK_PULL_PU_PD_TYPE,/*19*/ + MTK_PULL_PU_PD_TYPE,/*20*/ MTK_PULL_PU_PD_TYPE,/*21*/ + MTK_PULL_PU_PD_TYPE,/*22*/ MTK_PULL_PU_PD_TYPE,/*23*/ + MTK_PULL_PU_PD_TYPE,/*24*/ MTK_PULL_PU_PD_TYPE,/*25*/ + MTK_PULL_PU_PD_TYPE,/*26*/ MTK_PULL_PU_PD_TYPE,/*27*/ + MTK_PULL_PU_PD_TYPE,/*28*/ MTK_PULL_PU_PD_TYPE,/*29*/ + MTK_PULL_PU_PD_TYPE,/*30*/ MTK_PULL_PU_PD_TYPE,/*31*/ + MTK_PULL_PU_PD_TYPE,/*32*/ MTK_PULL_PU_PD_TYPE,/*33*/ + MTK_PULL_PU_PD_TYPE,/*34*/ MTK_PULL_PU_PD_TYPE,/*35*/ + MTK_PULL_PU_PD_TYPE,/*36*/ MTK_PULL_PU_PD_TYPE,/*37*/ + MTK_PULL_PU_PD_TYPE,/*38*/ MTK_PULL_PU_PD_TYPE,/*39*/ + MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/ + MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/ + MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/ + MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/ + MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/ + MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/ + MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/ + MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/ + MTK_PULL_PU_PD_TYPE,/*56*/ MTK_PULL_PU_PD_TYPE,/*57*/ + MTK_PULL_PU_PD_TYPE,/*58*/ MTK_PULL_PU_PD_TYPE,/*59*/ + MTK_PULL_PU_PD_TYPE,/*60*/ MTK_PULL_PU_PD_TYPE,/*61*/ + MTK_PULL_PU_PD_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE,/*63*/ + MTK_PULL_PU_PD_TYPE,/*64*/ MTK_PULL_PU_PD_TYPE,/*65*/ + MTK_PULL_PU_PD_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ + MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/ + MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PUPD_R1R0_TYPE,/*71*/ + MTK_PULL_PUPD_R1R0_TYPE,/*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/ + MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PUPD_R1R0_TYPE,/*75*/ + MTK_PULL_PUPD_R1R0_TYPE,/*76*/ MTK_PULL_PUPD_R1R0_TYPE,/*77*/ + MTK_PULL_PUPD_R1R0_TYPE,/*78*/ MTK_PULL_PUPD_R1R0_TYPE,/*79*/ + MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/ + MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ + MTK_PULL_PUPD_R1R0_TYPE,/*84*/ MTK_PULL_PUPD_R1R0_TYPE,/*85*/ + MTK_PULL_PUPD_R1R0_TYPE,/*86*/ MTK_PULL_PUPD_R1R0_TYPE,/*87*/ + MTK_PULL_PUPD_R1R0_TYPE,/*88*/ MTK_PULL_PUPD_R1R0_TYPE,/*89*/ + MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ + MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ + MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ + MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ + MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ + MTK_PULL_PU_PD_TYPE,/*100*/ MTK_PULL_PU_PD_TYPE,/*101*/ + MTK_PULL_PU_PD_TYPE,/*102*/ MTK_PULL_PU_PD_TYPE,/*103*/ + MTK_PULL_PU_PD_TYPE,/*104*/ MTK_PULL_PU_PD_TYPE,/*105*/ + MTK_PULL_PU_PD_TYPE,/*106*/ MTK_PULL_PU_PD_TYPE,/*107*/ + MTK_PULL_PU_PD_TYPE,/*108*/ MTK_PULL_PU_PD_TYPE,/*109*/ + MTK_PULL_PU_PD_TYPE,/*110*/ MTK_PULL_PU_PD_TYPE,/*111*/ + MTK_PULL_PU_PD_TYPE,/*112*/ MTK_PULL_PU_PD_TYPE,/*113*/ + MTK_PULL_PU_PD_TYPE,/*114*/ MTK_PULL_PU_PD_TYPE,/*115*/ + MTK_PULL_PU_PD_TYPE,/*116*/ MTK_PULL_PU_PD_TYPE,/*117*/ + MTK_PULL_PU_PD_TYPE,/*118*/ MTK_PULL_PU_PD_TYPE,/*119*/ + MTK_PULL_PU_PD_TYPE,/*120*/ MTK_PULL_PU_PD_TYPE,/*121*/ + MTK_PULL_PU_PD_TYPE,/*122*/ MTK_PULL_PU_PD_TYPE,/*123*/ + MTK_PULL_PU_PD_TYPE,/*124*/ MTK_PULL_PU_PD_TYPE,/*125*/ + MTK_PULL_PU_PD_TYPE,/*126*/ MTK_PULL_PU_PD_RSEL_TYPE,/*127*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*128*/ MTK_PULL_PU_PD_RSEL_TYPE,/*129*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*130*/ MTK_PULL_PU_PD_RSEL_TYPE,/*131*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*132*/ MTK_PULL_PU_PD_RSEL_TYPE,/*133*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*134*/ MTK_PULL_PU_PD_RSEL_TYPE,/*135*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*136*/ MTK_PULL_PU_PD_RSEL_TYPE,/*137*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*138*/ MTK_PULL_PU_PD_RSEL_TYPE,/*139*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*140*/ MTK_PULL_PU_PD_RSEL_TYPE,/*141*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*142*/ MTK_PULL_PU_PD_RSEL_TYPE,/*143*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*144*/ MTK_PULL_PU_PD_RSEL_TYPE,/*145*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*146*/ MTK_PULL_PU_PD_TYPE,/*147*/ + MTK_PULL_PU_PD_TYPE,/*148*/ MTK_PULL_PU_PD_TYPE,/*149*/ + MTK_PULL_PU_PD_TYPE,/*150*/ MTK_PULL_PU_PD_TYPE,/*151*/ + MTK_PULL_PU_PD_TYPE,/*152*/ MTK_PULL_PU_PD_TYPE,/*153*/ + MTK_PULL_PU_PD_TYPE,/*154*/ MTK_PULL_PU_PD_TYPE,/*155*/ + MTK_PULL_PU_PD_TYPE,/*156*/ MTK_PULL_PU_PD_TYPE,/*157*/ + MTK_PULL_PU_PD_TYPE,/*158*/ MTK_PULL_PU_PD_TYPE,/*159*/ + MTK_PULL_PU_PD_TYPE,/*160*/ MTK_PULL_PU_PD_TYPE,/*161*/ + MTK_PULL_PU_PD_TYPE,/*162*/ MTK_PULL_PU_PD_TYPE,/*163*/ + MTK_PULL_PU_PD_TYPE,/*164*/ MTK_PULL_PU_PD_TYPE,/*165*/ + MTK_PULL_PU_PD_TYPE,/*166*/ MTK_PULL_PU_PD_TYPE,/*167*/ + MTK_PULL_PU_PD_TYPE,/*168*/ MTK_PULL_PU_PD_TYPE,/*169*/ + MTK_PULL_PU_PD_TYPE,/*170*/ MTK_PULL_PU_PD_TYPE,/*171*/ + MTK_PULL_PU_PD_TYPE,/*172*/ MTK_PULL_PU_PD_TYPE,/*173*/ + MTK_PULL_PU_PD_TYPE,/*174*/ MTK_PULL_PU_PD_TYPE,/*175*/ + MTK_PULL_PU_PD_TYPE,/*176*/ MTK_PULL_PU_PD_TYPE,/*177*/ + MTK_PULL_PU_PD_TYPE,/*178*/ MTK_PULL_PU_PD_TYPE,/*179*/ + MTK_PULL_PU_PD_TYPE,/*180*/ MTK_PULL_PU_PD_TYPE,/*181*/ + MTK_PULL_PU_PD_TYPE,/*182*/ MTK_PULL_PU_PD_TYPE,/*183*/ + MTK_PULL_PU_PD_TYPE,/*184*/ +}; + +static const struct mtk_pin_reg_calc mt8186_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8186_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8186_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8186_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8186_pin_do_range), + [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt8186_pin_dir_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8186_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8186_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8186_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8186_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8186_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8186_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8186_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8186_pin_r1_range), + [PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8186_pin_drv_adv_range), + [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8186_pin_rsel_range), + +}; + +static const char * const mt8186_pinctrl_register_base_names[] = { + "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", "iocfg_bl", + "iocfg_rb", "iocfg_rt", +}; + +static const struct mtk_eint_hw mt8186_eint_hw = { + .port_mask = 0xf, + .ports = 7, + .ap_num = 217, + .db_cnt = 32, +}; + +static const struct mtk_pin_soc mt8186_data = { + .reg_cal = mt8186_reg_cals, + .pins = mtk_pins_mt8186, + .npins = ARRAY_SIZE(mtk_pins_mt8186), + .ngrps = ARRAY_SIZE(mtk_pins_mt8186), + .nfuncs = 8, + .gpio_m = 0, + .eint_hw = &mt8186_eint_hw, + .base_names = mt8186_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt8186_pinctrl_register_base_names), + .pull_type = mt8186_pull_type, + .pin_rsel = mt8186_pin_rsel_val_range, + .npin_rsel = ARRAY_SIZE(mt8186_pin_rsel_val_range), + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_drive_get = mtk_pinconf_adv_drive_get_raw, + .adv_drive_set = mtk_pinconf_adv_drive_set_raw, +}; + +static const struct of_device_id mt8186_pinctrl_of_match[] = { + { .compatible = "mediatek,mt8186-pinctrl", .data = &mt8186_data }, + { } +}; + +static struct platform_driver mt8186_pinctrl_driver = { + .driver = { + .name = "mt8186-pinctrl", + .of_match_table = mt8186_pinctrl_of_match, + .pm = &mtk_paris_pinctrl_pm_ops, + }, + .probe = mtk_paris_pinctrl_probe, +}; + +static int __init mt8186_pinctrl_init(void) +{ + return platform_driver_register(&mt8186_pinctrl_driver); +} + +arch_initcall(mt8186_pinctrl_init); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8192.c b/drivers/pinctrl/mediatek/pinctrl-mt8192.c index 0c16b2c756bf..acccde9262ba 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c @@ -1381,22 +1381,17 @@ static const struct mtk_pin_soc mt8192_data = { }; static const struct of_device_id mt8192_pinctrl_of_match[] = { - { .compatible = "mediatek,mt8192-pinctrl", }, + { .compatible = "mediatek,mt8192-pinctrl", .data = &mt8192_data }, { } }; -static int mt8192_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_paris_pinctrl_probe(pdev, &mt8192_data); -} - static struct platform_driver mt8192_pinctrl_driver = { .driver = { .name = "mt8192-pinctrl", .of_match_table = mt8192_pinctrl_of_match, .pm = &mtk_paris_pinctrl_pm_ops, }, - .probe = mt8192_pinctrl_probe, + .probe = mtk_paris_pinctrl_probe, }; static int __init mt8192_pinctrl_init(void) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8195.c b/drivers/pinctrl/mediatek/pinctrl-mt8195.c index 275b7ba4386d..563693d3d4c2 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c @@ -959,22 +959,17 @@ static const struct mtk_pin_soc mt8195_data = { }; static const struct of_device_id mt8195_pinctrl_of_match[] = { - { .compatible = "mediatek,mt8195-pinctrl", }, + { .compatible = "mediatek,mt8195-pinctrl", .data = &mt8195_data }, { } }; -static int mt8195_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_paris_pinctrl_probe(pdev, &mt8195_data); -} - static struct platform_driver mt8195_pinctrl_driver = { .driver = { .name = "mt8195-pinctrl", .of_match_table = mt8195_pinctrl_of_match, .pm = &mtk_paris_pinctrl_pm_ops, }, - .probe = mt8195_pinctrl_probe, + .probe = mtk_paris_pinctrl_probe, }; static int __init mt8195_pinctrl_init(void) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c index 79b1fee5a1eb..727c65221aef 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -416,25 +416,6 @@ static const struct mtk_pin_ies_smt_set mt8365_smt_set[] = { MTK_PIN_IES_SMT_SPEC(144, 144, 0x480, 22), }; -static int mt8365_spec_pull_set(struct regmap *regmap, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0) -{ - return mtk_pctrl_spec_pull_set_samereg(regmap, mt8365_spec_pupd, - ARRAY_SIZE(mt8365_spec_pupd), pin, align, isup, r1r0); -} - -static int mt8365_ies_smt_set(struct regmap *regmap, unsigned int pin, - unsigned char align, int value, enum pin_config_param arg) -{ - if (arg == PIN_CONFIG_INPUT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8365_ies_set, - ARRAY_SIZE(mt8365_ies_set), pin, align, value); - else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8365_smt_set, - ARRAY_SIZE(mt8365_smt_set), pin, align, value); - return -EINVAL; -} - static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { .pins = mtk_pins_mt8365, .npins = ARRAY_SIZE(mtk_pins_mt8365), @@ -442,8 +423,14 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { .n_grp_cls = ARRAY_SIZE(mt8365_drv_grp), .pin_drv_grp = mt8365_pin_drv, .n_pin_drv_grps = ARRAY_SIZE(mt8365_pin_drv), - .spec_pull_set = mt8365_spec_pull_set, - .spec_ies_smt_set = mt8365_ies_smt_set, + .spec_ies = mt8365_ies_set, + .n_spec_ies = ARRAY_SIZE(mt8365_ies_set), + .spec_smt = mt8365_smt_set, + .n_spec_smt = ARRAY_SIZE(mt8365_smt_set), + .spec_pupd = mt8365_spec_pupd, + .n_spec_pupd = ARRAY_SIZE(mt8365_spec_pupd), + .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, + .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, .dir_offset = 0x0140, .dout_offset = 0x00A0, .din_offset = 0x0000, @@ -469,20 +456,13 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { }, }; -static int mtk_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_pctrl_init(pdev, &mt8365_pinctrl_data, NULL); -} - static const struct of_device_id mt8365_pctrl_match[] = { - { - .compatible = "mediatek,mt8365-pinctrl", - }, + { .compatible = "mediatek,mt8365-pinctrl", .data = &mt8365_pinctrl_data }, {} }; static struct platform_driver mtk_pinctrl_driver = { - .probe = mtk_pinctrl_probe, + .probe = mtk_pctrl_common_probe, .driver = { .name = "mediatek-mt8365-pinctrl", .of_match_table = mt8365_pctrl_match, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c index 219fb4bc341f..939a1932b8dc 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c @@ -186,13 +186,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt8516_spec_pupd[] = { MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0), }; -static int mt8516_spec_pull_set(struct regmap *regmap, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0) -{ - return mtk_pctrl_spec_pull_set_samereg(regmap, mt8516_spec_pupd, - ARRAY_SIZE(mt8516_spec_pupd), pin, align, isup, r1r0); -} - static const struct mtk_pin_ies_smt_set mt8516_ies_set[] = { MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2), MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3), @@ -292,18 +285,6 @@ static const struct mtk_pin_ies_smt_set mt8516_smt_set[] = { MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9), }; -static int mt8516_ies_smt_set(struct regmap *regmap, unsigned int pin, - unsigned char align, int value, enum pin_config_param arg) -{ - if (arg == PIN_CONFIG_INPUT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_ies_set, - ARRAY_SIZE(mt8516_ies_set), pin, align, value); - else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_smt_set, - ARRAY_SIZE(mt8516_smt_set), pin, align, value); - return -EINVAL; -} - static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = { .pins = mtk_pins_mt8516, .npins = ARRAY_SIZE(mtk_pins_mt8516), @@ -311,8 +292,14 @@ static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = { .n_grp_cls = ARRAY_SIZE(mt8516_drv_grp), .pin_drv_grp = mt8516_pin_drv, .n_pin_drv_grps = ARRAY_SIZE(mt8516_pin_drv), - .spec_pull_set = mt8516_spec_pull_set, - .spec_ies_smt_set = mt8516_ies_smt_set, + .spec_ies = mt8516_ies_set, + .n_spec_ies = ARRAY_SIZE(mt8516_ies_set), + .spec_pupd = mt8516_spec_pupd, + .n_spec_pupd = ARRAY_SIZE(mt8516_spec_pupd), + .spec_smt = mt8516_smt_set, + .n_spec_smt = ARRAY_SIZE(mt8516_smt_set), + .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, + .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, .dir_offset = 0x0000, .pullen_offset = 0x0500, .pullsel_offset = 0x0600, @@ -335,22 +322,15 @@ static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = { }, }; -static int mt8516_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_pctrl_init(pdev, &mt8516_pinctrl_data, NULL); -} - static const struct of_device_id mt8516_pctrl_match[] = { - { - .compatible = "mediatek,mt8516-pinctrl", - }, + { .compatible = "mediatek,mt8516-pinctrl", .data = &mt8516_pinctrl_data }, {} }; MODULE_DEVICE_TABLE(of, mt8516_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { - .probe = mt8516_pinctrl_probe, + .probe = mtk_pctrl_common_probe, .driver = { .name = "mediatek-mt8516-pinctrl", .of_match_table = mt8516_pctrl_match, diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 5f7c421ab6e7..f25b3e09386b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -131,7 +131,7 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, */ if (pctl->devdata->spec_ies_smt_set) { return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), - pin, pctl->devdata->port_align, value, arg); + pctl->devdata, pin, value, arg); } if (arg == PIN_CONFIG_INPUT_ENABLE) @@ -151,10 +151,27 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, } int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, - const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, - unsigned int pin, unsigned char align, int value) + const struct mtk_pinctrl_devdata *devdata, + unsigned int pin, int value, enum pin_config_param arg) { - unsigned int i, reg_addr, bit; + const struct mtk_pin_ies_smt_set *ies_smt_infos = NULL; + unsigned int i, info_num, reg_addr, bit; + + switch (arg) { + case PIN_CONFIG_INPUT_ENABLE: + ies_smt_infos = devdata->spec_ies; + info_num = devdata->n_spec_ies; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + ies_smt_infos = devdata->spec_smt; + info_num = devdata->n_spec_smt; + break; + default: + break; + } + + if (!ies_smt_infos) + return -EINVAL; for (i = 0; i < info_num; i++) { if (pin >= ies_smt_infos[i].start && @@ -167,9 +184,9 @@ int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, return -EINVAL; if (value) - reg_addr = ies_smt_infos[i].offset + align; + reg_addr = ies_smt_infos[i].offset + devdata->port_align; else - reg_addr = ies_smt_infos[i].offset + (align << 1); + reg_addr = ies_smt_infos[i].offset + (devdata->port_align << 1); bit = BIT(ies_smt_infos[i].bit); regmap_write(regmap, reg_addr, bit); @@ -222,9 +239,8 @@ static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl, } int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, - const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, - unsigned int info_num, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0) + const struct mtk_pinctrl_devdata *devdata, + unsigned int pin, bool isup, unsigned int r1r0) { unsigned int i; unsigned int reg_pupd, reg_set, reg_rst; @@ -232,8 +248,11 @@ int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin; bool find = false; - for (i = 0; i < info_num; i++) { - if (pin == pupd_infos[i].pin) { + if (!devdata->spec_pupd) + return -EINVAL; + + for (i = 0; i < devdata->n_spec_pupd; i++) { + if (pin == devdata->spec_pupd[i].pin) { find = true; break; } @@ -242,9 +261,9 @@ int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, if (!find) return -EINVAL; - spec_pupd_pin = pupd_infos + i; - reg_set = spec_pupd_pin->offset + align; - reg_rst = spec_pupd_pin->offset + (align << 1); + spec_pupd_pin = devdata->spec_pupd + i; + reg_set = spec_pupd_pin->offset + devdata->port_align; + reg_rst = spec_pupd_pin->offset + (devdata->port_align << 1); if (isup) reg_pupd = reg_rst; @@ -298,7 +317,8 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, */ r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00; ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin), - pin, pctl->devdata->port_align, isup, r1r0); + pctl->devdata, pin, isup, + r1r0); if (!ret) return 0; } @@ -1013,10 +1033,12 @@ static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev) return mtk_eint_do_init(pctl->eint); } +/* This is used as a common probe function */ int mtk_pctrl_init(struct platform_device *pdev, const struct mtk_pinctrl_devdata *data, struct regmap *regmap) { + struct device *dev = &pdev->dev; struct pinctrl_pin_desc *pins; struct mtk_pinctrl *pctl; struct device_node *np = pdev->dev.of_node, *node; @@ -1030,37 +1052,35 @@ int mtk_pctrl_init(struct platform_device *pdev, platform_set_drvdata(pdev, pctl); prop = of_find_property(np, "pins-are-numbered", NULL); - if (!prop) { - dev_err(&pdev->dev, "only support pins-are-numbered format\n"); - return -EINVAL; - } + if (!prop) + return dev_err_probe(dev, -EINVAL, + "only support pins-are-numbered format\n"); node = of_parse_phandle(np, "mediatek,pctl-regmap", 0); if (node) { pctl->regmap1 = syscon_node_to_regmap(node); + of_node_put(node); if (IS_ERR(pctl->regmap1)) return PTR_ERR(pctl->regmap1); } else if (regmap) { pctl->regmap1 = regmap; } else { - dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n"); - return -EINVAL; + return dev_err_probe(dev, -EINVAL, "Cannot find pinctrl regmap.\n"); } /* Only 8135 has two base addr, other SoCs have only one. */ node = of_parse_phandle(np, "mediatek,pctl-regmap", 1); if (node) { pctl->regmap2 = syscon_node_to_regmap(node); + of_node_put(node); if (IS_ERR(pctl->regmap2)) return PTR_ERR(pctl->regmap2); } pctl->devdata = data; ret = mtk_pctrl_build_state(pdev); - if (ret) { - dev_err(&pdev->dev, "build state failed: %d\n", ret); - return -EINVAL; - } + if (ret) + return dev_err_probe(dev, ret, "build state failed\n"); pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins), GFP_KERNEL); @@ -1081,10 +1101,9 @@ int mtk_pctrl_init(struct platform_device *pdev, pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, pctl); - if (IS_ERR(pctl->pctl_dev)) { - dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); - return PTR_ERR(pctl->pctl_dev); - } + if (IS_ERR(pctl->pctl_dev)) + return dev_err_probe(dev, PTR_ERR(pctl->pctl_dev), + "Couldn't register pinctrl driver\n"); pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); if (!pctl->chip) @@ -1118,3 +1137,14 @@ chip_error: gpiochip_remove(pctl->chip); return ret; } + +int mtk_pctrl_common_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct mtk_pinctrl_devdata *data = device_get_match_data(dev); + + if (!data) + return -ENODEV; + + return mtk_pctrl_init(pdev, data, NULL); +} diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 98f27cdc609a..6fe8564334c9 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -193,6 +193,12 @@ struct mtk_eint_offsets { * * @grp_desc: The driving group info. * @pin_drv_grp: The driving group for all pins. + * @spec_ies: Special pin setting for input enable + * @n_spec_ies: Number of entries in spec_ies + * @spec_pupd: Special pull up/down setting + * @n_spec_pupd: Number of entries in spec_pupd + * @spec_smt: Special pin setting for schmitt + * @n_spec_smt: Number of entries in spec_smt * @spec_pull_set: Each SoC may have special pins for pull up/down setting, * these pins' pull setting are very different, they have separate pull * up/down bit, R0 and R1 resistor bit, so they need special pull setting. @@ -231,10 +237,18 @@ struct mtk_pinctrl_devdata { unsigned int n_grp_cls; const struct mtk_pin_drv_grp *pin_drv_grp; unsigned int n_pin_drv_grps; - int (*spec_pull_set)(struct regmap *reg, unsigned int pin, - unsigned char align, bool isup, unsigned int arg); - int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin, - unsigned char align, int value, enum pin_config_param arg); + const struct mtk_pin_ies_smt_set *spec_ies; + unsigned int n_spec_ies; + const struct mtk_pin_spec_pupd_set_samereg *spec_pupd; + unsigned int n_spec_pupd; + const struct mtk_pin_ies_smt_set *spec_smt; + unsigned int n_spec_smt; + int (*spec_pull_set)(struct regmap *regmap, + const struct mtk_pinctrl_devdata *devdata, + unsigned int pin, bool isup, unsigned int r1r0); + int (*spec_ies_smt_set)(struct regmap *reg, + const struct mtk_pinctrl_devdata *devdata, + unsigned int pin, int value, enum pin_config_param arg); void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin, unsigned int mode); void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin); @@ -277,14 +291,15 @@ int mtk_pctrl_init(struct platform_device *pdev, const struct mtk_pinctrl_devdata *data, struct regmap *regmap); +int mtk_pctrl_common_probe(struct platform_device *pdev); + int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, - const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, - unsigned int info_num, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0); + const struct mtk_pinctrl_devdata *devdata, + unsigned int pin, bool isup, unsigned int r1r0); int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, - const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, - unsigned int pin, unsigned char align, int value); + const struct mtk_pinctrl_devdata *devdata, + unsigned int pin, int value, enum pin_config_param arg); extern const struct dev_pm_ops mtk_eint_pm_ops; diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h new file mode 100644 index 000000000000..464651f7b44b --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h @@ -0,0 +1,2186 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 MediaTek Inc. + * + * Author: Guodong Liu <guodong.liu@mediatek.com> + * + */ + +#ifndef __PINCTRL_MTK_MT8186_H +#define __PINCTRL_MTK_MT8186_H + +#include "pinctrl-paris.h" + +static const struct mtk_pin_desc mtk_pins_mt8186[] = { + MTK_PIN( + 0, "GPIO0", + MTK_EINT_FUNCTION(0, 0), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "I2S0_MCK"), + MTK_FUNCTION(2, "SPI0_CLK_B"), + MTK_FUNCTION(3, "I2S2_MCK"), + MTK_FUNCTION(4, "CMFLASH0"), + MTK_FUNCTION(5, "SCP_SPI0_CK"), + MTK_FUNCTION(6, "TP_GPIO0_AO"), + MTK_FUNCTION(7, "dbg_mon_a0") + ), + + MTK_PIN( + 1, "GPIO1", + MTK_EINT_FUNCTION(0, 1), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "I2S0_BCK"), + MTK_FUNCTION(2, "SPI0_CSB_B"), + MTK_FUNCTION(3, "I2S2_BCK"), + MTK_FUNCTION(4, "CMFLASH1"), + MTK_FUNCTION(5, "SCP_SPI0_CS"), + MTK_FUNCTION(6, "TP_GPIO1_AO") + ), + + MTK_PIN( + 2, "GPIO2", + MTK_EINT_FUNCTION(0, 2), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "I2S0_LRCK"), + MTK_FUNCTION(2, "SPI0_MO_B"), + MTK_FUNCTION(3, "I2S2_LRCK"), + MTK_FUNCTION(4, "CMFLASH2"), + MTK_FUNCTION(5, "SCP_SPI0_MO"), + MTK_FUNCTION(6, "TP_GPIO2_AO") + ), + + MTK_PIN( + 3, "GPIO3", + MTK_EINT_FUNCTION(0, 3), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "I2S0_DI"), + MTK_FUNCTION(2, "SPI0_MI_B"), + MTK_FUNCTION(3, "I2S2_DI"), + MTK_FUNCTION(4, "SRCLKENAI1"), + MTK_FUNCTION(5, "SCP_SPI0_MI"), + MTK_FUNCTION(6, "TP_GPIO3_AO") + ), + + MTK_PIN( + 4, "GPIO4", + MTK_EINT_FUNCTION(0, 4), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "I2S3_DO"), + MTK_FUNCTION(3, "I2S1_DO"), + MTK_FUNCTION(6, "TP_GPIO4_AO") + ), + + MTK_PIN( + 5, "GPIO5", + MTK_EINT_FUNCTION(0, 5), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "EXT_FRAME_SYNC"), + MTK_FUNCTION(6, "TP_GPIO5_AO") + ), + + MTK_PIN( + 6, "GPIO6", + MTK_EINT_FUNCTION(0, 6), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "I2S3_MCK"), + MTK_FUNCTION(2, "SPI1_CLK_B"), + MTK_FUNCTION(3, "I2S1_MCK"), + MTK_FUNCTION(4, "DPI_DATA22"), + MTK_FUNCTION(6, "TP_GPIO6_AO") + ), + + MTK_PIN( + 7, "GPIO7", + MTK_EINT_FUNCTION(0, 7), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "I2S3_BCK"), + MTK_FUNCTION(2, "SPI1_CSB_B"), + MTK_FUNCTION(3, "I2S1_BCK"), + MTK_FUNCTION(4, "DPI_DATA23"), + MTK_FUNCTION(6, "TP_GPIO7_AO") + ), + + MTK_PIN( + 8, "GPIO8", + MTK_EINT_FUNCTION(0, 8), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "I2S3_LRCK"), + MTK_FUNCTION(2, "SPI1_MO_B"), + MTK_FUNCTION(3, "I2S1_LRCK"), + MTK_FUNCTION(4, "CONN_UART0_RXD"), + MTK_FUNCTION(5, "SSPM_URXD_AO"), + MTK_FUNCTION(6, "ADSP_UART_RX"), + MTK_FUNCTION(7, "CONN_MCU_DBGACK_N") + ), + + MTK_PIN( + 9, "GPIO9", + MTK_EINT_FUNCTION(0, 9), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "I2S3_DO"), + MTK_FUNCTION(2, "SPI1_MI_B"), + MTK_FUNCTION(3, "I2S1_DO"), + MTK_FUNCTION(4, "CONN_UART0_TXD"), + MTK_FUNCTION(5, "SSPM_UTXD_AO"), + MTK_FUNCTION(6, "ADSP_UART_TX"), + MTK_FUNCTION(7, "CONN_MCU_DBGI_N") + ), + + MTK_PIN( + 10, "GPIO10", + MTK_EINT_FUNCTION(0, 10), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "I2S0_MCK"), + MTK_FUNCTION(2, "SPI4_CLK_A"), + MTK_FUNCTION(3, "I2S2_MCK"), + MTK_FUNCTION(4, "SPM_JTAG_TDI"), + MTK_FUNCTION(5, "SCP_JTAG_TDI"), + MTK_FUNCTION(6, "ADSP_JTAG_TDI"), + MTK_FUNCTION(7, "CONN_MCU_TDI") + ), + + MTK_PIN( + 11, "GPIO11", + MTK_EINT_FUNCTION(0, 11), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "I2S0_BCK"), + MTK_FUNCTION(2, "SPI4_CSB_A"), + MTK_FUNCTION(3, "I2S2_BCK"), + MTK_FUNCTION(4, "SPM_JTAG_TRSTN"), + MTK_FUNCTION(5, "SCP_JTAG_TRSTN"), + MTK_FUNCTION(6, "ADSP_JTAG_TRSTN"), + MTK_FUNCTION(7, "CONN_MCU_TRST_B") + ), + + MTK_PIN( + 12, "GPIO12", + MTK_EINT_FUNCTION(0, 12), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "I2S0_LRCK"), + MTK_FUNCTION(2, "SPI4_MO_A"), + MTK_FUNCTION(3, "I2S2_LRCK"), + MTK_FUNCTION(4, "SPM_JTAG_TCK"), + MTK_FUNCTION(5, "SCP_JTAG_TCK"), + MTK_FUNCTION(6, "ADSP_JTAG_TCK"), + MTK_FUNCTION(7, "CONN_MCU_TCK") + ), + + MTK_PIN( + 13, "GPIO13", + MTK_EINT_FUNCTION(0, 13), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "I2S0_DI"), + MTK_FUNCTION(2, "SPI4_MI_A"), + MTK_FUNCTION(3, "I2S2_DI"), + MTK_FUNCTION(4, "SPM_JTAG_TDO"), + MTK_FUNCTION(5, "SCP_JTAG_TDO"), + MTK_FUNCTION(6, "ADSP_JTAG_TDO"), + MTK_FUNCTION(7, "CONN_MCU_TDO") + ), + + MTK_PIN( + 14, "GPIO14", + MTK_EINT_FUNCTION(0, 14), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(4, "SPM_JTAG_TMS"), + MTK_FUNCTION(5, "SCP_JTAG_TMS"), + MTK_FUNCTION(6, "ADSP_JTAG_TMS"), + MTK_FUNCTION(7, "CONN_MCU_TMS") + ), + + MTK_PIN( + 15, "GPIO15", + MTK_EINT_FUNCTION(0, 15), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "EXT_FRAME_SYNC"), + MTK_FUNCTION(2, "SRCLKENAI1"), + MTK_FUNCTION(3, "CLKM1"), + MTK_FUNCTION(4, "PWM0") + ), + + MTK_PIN( + 16, "GPIO16", + MTK_EINT_FUNCTION(0, 16), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "CONN_WIFI_TXD"), + MTK_FUNCTION(2, "SRCLKENAI0"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(4, "PWM1") + ), + + MTK_PIN( + 17, "GPIO17", + MTK_EINT_FUNCTION(0, 17), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(3, "CLKM3"), + MTK_FUNCTION(4, "PWM2"), + MTK_FUNCTION(7, "dbg_mon_a32") + ), + + MTK_PIN( + 18, "GPIO18", + MTK_EINT_FUNCTION(0, 18), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(2, "CMVREF0"), + MTK_FUNCTION(6, "SPI2_CLK_B"), + MTK_FUNCTION(7, "dbg_mon_a26") + ), + + MTK_PIN( + 19, "GPIO19", + MTK_EINT_FUNCTION(0, 19), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(2, "CMVREF1"), + MTK_FUNCTION(5, "ANT_SEL3"), + MTK_FUNCTION(6, "SPI2_CSB_B"), + MTK_FUNCTION(7, "dbg_mon_a2") + ), + + MTK_PIN( + 20, "GPIO20", + MTK_EINT_FUNCTION(0, 20), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(2, "CMVREF2"), + MTK_FUNCTION(5, "ANT_SEL4"), + MTK_FUNCTION(6, "SPI2_MO_B"), + MTK_FUNCTION(7, "dbg_mon_a3") + ), + + MTK_PIN( + 21, "GPIO21", + MTK_EINT_FUNCTION(0, 21), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "I2S0_MCK"), + MTK_FUNCTION(2, "I2S1_MCK"), + MTK_FUNCTION(3, "I2S3_MCK"), + MTK_FUNCTION(5, "ANT_SEL5"), + MTK_FUNCTION(6, "SPI2_MI_B"), + MTK_FUNCTION(7, "dbg_mon_a4") + ), + + MTK_PIN( + 22, "GPIO22", + MTK_EINT_FUNCTION(0, 22), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "I2S0_BCK"), + MTK_FUNCTION(2, "I2S1_BCK"), + MTK_FUNCTION(3, "I2S3_BCK"), + MTK_FUNCTION(4, "TDM_RX_LRCK"), + MTK_FUNCTION(5, "ANT_SEL6"), + MTK_FUNCTION(7, "dbg_mon_a5") + ), + + MTK_PIN( + 23, "GPIO23", + MTK_EINT_FUNCTION(0, 23), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "I2S0_LRCK"), + MTK_FUNCTION(2, "I2S1_LRCK"), + MTK_FUNCTION(3, "I2S3_LRCK"), + MTK_FUNCTION(4, "TDM_RX_BCK"), + MTK_FUNCTION(5, "ANT_SEL7"), + MTK_FUNCTION(7, "dbg_mon_a6") + ), + + MTK_PIN( + 24, "GPIO24", + MTK_EINT_FUNCTION(0, 24), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "I2S0_DI"), + MTK_FUNCTION(2, "I2S1_DO"), + MTK_FUNCTION(3, "I2S3_DO"), + MTK_FUNCTION(4, "TDM_RX_MCK"), + MTK_FUNCTION(7, "dbg_mon_a7") + ), + + MTK_PIN( + 25, "GPIO25", + MTK_EINT_FUNCTION(0, 25), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "I2S2_MCK"), + MTK_FUNCTION(2, "PCM_CLK"), + MTK_FUNCTION(3, "SPI4_CLK_B"), + MTK_FUNCTION(4, "TDM_RX_DATA0"), + MTK_FUNCTION(7, "dbg_mon_a8") + ), + + MTK_PIN( + 26, "GPIO26", + MTK_EINT_FUNCTION(0, 26), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "I2S2_BCK"), + MTK_FUNCTION(2, "PCM_SYNC"), + MTK_FUNCTION(3, "SPI4_CSB_B"), + MTK_FUNCTION(4, "TDM_RX_DATA1"), + MTK_FUNCTION(7, "dbg_mon_a9") + ), + + MTK_PIN( + 27, "GPIO27", + MTK_EINT_FUNCTION(0, 27), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "I2S2_LRCK"), + MTK_FUNCTION(2, "PCM_DI"), + MTK_FUNCTION(3, "SPI4_MO_B"), + MTK_FUNCTION(4, "TDM_RX_DATA2"), + MTK_FUNCTION(7, "dbg_mon_a10") + ), + + MTK_PIN( + 28, "GPIO28", + MTK_EINT_FUNCTION(0, 28), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "I2S2_DI"), + MTK_FUNCTION(2, "PCM_DO"), + MTK_FUNCTION(3, "SPI4_MI_B"), + MTK_FUNCTION(4, "TDM_RX_DATA3") + ), + + MTK_PIN( + 29, "GPIO29", + MTK_EINT_FUNCTION(0, 29), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "ANT_SEL0"), + MTK_FUNCTION(2, "GPS_L1_ELNA_EN") + ), + + MTK_PIN( + 30, "GPIO30", + MTK_EINT_FUNCTION(0, 30), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "ANT_SEL1") + ), + + MTK_PIN( + 31, "GPIO31", + MTK_EINT_FUNCTION(0, 31), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "ANT_SEL2"), + MTK_FUNCTION(2, "EXT_FRAME_SYNC"), + MTK_FUNCTION(3, "SRCLKENAI1") + ), + + MTK_PIN( + 32, "GPIO32", + MTK_EINT_FUNCTION(0, 32), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "UTXD0"), + MTK_FUNCTION(3, "ADSP_UART_RX"), + MTK_FUNCTION(4, "TP_URXD1_AO") + ), + + MTK_PIN( + 33, "GPIO33", + MTK_EINT_FUNCTION(0, 33), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "URXD0"), + MTK_FUNCTION(3, "ADSP_UART_TX"), + MTK_FUNCTION(4, "TP_UTXD1_AO") + ), + + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(0, 34), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "TP_URXD2_AO"), + MTK_FUNCTION(3, "SSPM_URXD_AO"), + MTK_FUNCTION(4, "ADSP_UART_RX"), + MTK_FUNCTION(5, "CONN_UART0_RXD") + ), + + MTK_PIN( + 35, "GPIO35", + MTK_EINT_FUNCTION(0, 35), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "TP_UTXD2_AO"), + MTK_FUNCTION(3, "SSPM_UTXD_AO"), + MTK_FUNCTION(4, "ADSP_UART_TX"), + MTK_FUNCTION(5, "CONN_UART0_TXD"), + MTK_FUNCTION(6, "CONN_WIFI_TXD") + ), + + MTK_PIN( + 36, "GPIO36", + MTK_EINT_FUNCTION(0, 36), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "SPI0_CLK_A"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(4, "SCP_SPI0_CK"), + MTK_FUNCTION(5, "SPINOR_CK"), + MTK_FUNCTION(7, "dbg_mon_a11") + ), + + MTK_PIN( + 37, "GPIO37", + MTK_EINT_FUNCTION(0, 37), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "SPI0_CSB_A"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "PWM0"), + MTK_FUNCTION(4, "SCP_SPI0_CS"), + MTK_FUNCTION(5, "SPINOR_CS"), + MTK_FUNCTION(7, "dbg_mon_a12") + ), + + MTK_PIN( + 38, "GPIO38", + MTK_EINT_FUNCTION(0, 38), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "SPI0_MO_A"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "PWM1"), + MTK_FUNCTION(4, "SCP_SPI0_MO"), + MTK_FUNCTION(5, "SPINOR_IO0"), + MTK_FUNCTION(7, "dbg_mon_a13") + ), + + MTK_PIN( + 39, "GPIO39", + MTK_EINT_FUNCTION(0, 39), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "SPI0_MI_A"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "PWM2"), + MTK_FUNCTION(4, "SCP_SPI0_MI"), + MTK_FUNCTION(5, "SPINOR_IO1"), + MTK_FUNCTION(7, "dbg_mon_a14") + ), + + MTK_PIN( + 40, "GPIO40", + MTK_EINT_FUNCTION(0, 40), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "SPI1_CLK_A"), + MTK_FUNCTION(2, "SCP_SPI1_CK"), + MTK_FUNCTION(4, "UCTS0"), + MTK_FUNCTION(5, "SPINOR_IO2"), + MTK_FUNCTION(6, "TP_UCTS1_AO"), + MTK_FUNCTION(7, "dbg_mon_a15") + ), + + MTK_PIN( + 41, "GPIO41", + MTK_EINT_FUNCTION(0, 41), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "SPI1_CSB_A"), + MTK_FUNCTION(2, "SCP_SPI1_CS"), + MTK_FUNCTION(3, "PWM0"), + MTK_FUNCTION(4, "URTS0"), + MTK_FUNCTION(5, "SPINOR_IO3"), + MTK_FUNCTION(6, "TP_URTS1_AO"), + MTK_FUNCTION(7, "dbg_mon_a16") + ), + + MTK_PIN( + 42, "GPIO42", + MTK_EINT_FUNCTION(0, 42), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "SPI1_MO_A"), + MTK_FUNCTION(2, "SCP_SPI1_MO"), + MTK_FUNCTION(3, "PWM1"), + MTK_FUNCTION(4, "UCTS1"), + MTK_FUNCTION(6, "TP_UCTS2_AO"), + MTK_FUNCTION(7, "dbg_mon_a17") + ), + + MTK_PIN( + 43, "GPIO43", + MTK_EINT_FUNCTION(0, 43), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "SPI1_MI_A"), + MTK_FUNCTION(2, "SCP_SPI1_MI"), + MTK_FUNCTION(3, "PWM2"), + MTK_FUNCTION(4, "URTS1"), + MTK_FUNCTION(6, "TP_URTS2_AO"), + MTK_FUNCTION(7, "dbg_mon_a18") + ), + + MTK_PIN( + 44, "GPIO44", + MTK_EINT_FUNCTION(0, 44), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "SPI2_CLK_A"), + MTK_FUNCTION(2, "SCP_SPI0_CK"), + MTK_FUNCTION(7, "dbg_mon_a19") + ), + + MTK_PIN( + 45, "GPIO45", + MTK_EINT_FUNCTION(0, 45), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "SPI2_CSB_A"), + MTK_FUNCTION(2, "SCP_SPI0_CS"), + MTK_FUNCTION(7, "dbg_mon_a20") + ), + + MTK_PIN( + 46, "GPIO46", + MTK_EINT_FUNCTION(0, 46), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "SPI2_MO_A"), + MTK_FUNCTION(2, "SCP_SPI0_MO"), + MTK_FUNCTION(7, "dbg_mon_a21") + ), + + MTK_PIN( + 47, "GPIO47", + MTK_EINT_FUNCTION(0, 47), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "SPI2_MI_A"), + MTK_FUNCTION(2, "SCP_SPI0_MI"), + MTK_FUNCTION(7, "dbg_mon_a22") + ), + + MTK_PIN( + 48, "GPIO48", + MTK_EINT_FUNCTION(0, 48), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "SPI3_CLK"), + MTK_FUNCTION(2, "TP_URXD1_AO"), + MTK_FUNCTION(3, "TP_URXD2_AO"), + MTK_FUNCTION(4, "URXD1"), + MTK_FUNCTION(5, "I2S2_MCK"), + MTK_FUNCTION(6, "SCP_SPI0_CK") + ), + + MTK_PIN( + 49, "GPIO49", + MTK_EINT_FUNCTION(0, 49), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "SPI3_CSB"), + MTK_FUNCTION(2, "TP_UTXD1_AO"), + MTK_FUNCTION(3, "TP_UTXD2_AO"), + MTK_FUNCTION(4, "UTXD1"), + MTK_FUNCTION(5, "I2S2_BCK"), + MTK_FUNCTION(6, "SCP_SPI0_CS") + ), + + MTK_PIN( + 50, "GPIO50", + MTK_EINT_FUNCTION(0, 50), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "SPI3_MO"), + MTK_FUNCTION(5, "I2S2_LRCK"), + MTK_FUNCTION(6, "SCP_SPI0_MO") + ), + + MTK_PIN( + 51, "GPIO51", + MTK_EINT_FUNCTION(0, 51), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "SPI3_MI"), + MTK_FUNCTION(5, "I2S2_DI"), + MTK_FUNCTION(6, "SCP_SPI0_MI") + ), + + MTK_PIN( + 52, "GPIO52", + MTK_EINT_FUNCTION(0, 52), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "SPI5_CLK"), + MTK_FUNCTION(2, "I2S2_MCK"), + MTK_FUNCTION(3, "I2S1_MCK"), + MTK_FUNCTION(4, "SCP_SPI1_CK"), + MTK_FUNCTION(5, "LVTS_26M"), + MTK_FUNCTION(6, "DFD_TCK_XI"), + MTK_FUNCTION(7, "dbg_mon_b30") + ), + + MTK_PIN( + 53, "GPIO53", + MTK_EINT_FUNCTION(0, 53), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "SPI5_CSB"), + MTK_FUNCTION(2, "I2S2_BCK"), + MTK_FUNCTION(3, "I2S1_BCK"), + MTK_FUNCTION(4, "SCP_SPI1_CS"), + MTK_FUNCTION(5, "LVTS_FOUT"), + MTK_FUNCTION(6, "DFD_TDI"), + MTK_FUNCTION(7, "dbg_mon_b31") + ), + + MTK_PIN( + 54, "GPIO54", + MTK_EINT_FUNCTION(0, 54), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "SPI5_MO"), + MTK_FUNCTION(2, "I2S2_LRCK"), + MTK_FUNCTION(3, "I2S1_LRCK"), + MTK_FUNCTION(4, "SCP_SPI1_MO"), + MTK_FUNCTION(5, "LVTS_SCK"), + MTK_FUNCTION(6, "DFD_TDO"), + MTK_FUNCTION(7, "dbg_mon_a1") + ), + + MTK_PIN( + 55, "GPIO55", + MTK_EINT_FUNCTION(0, 55), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "SPI5_MI"), + MTK_FUNCTION(2, "I2S2_DI"), + MTK_FUNCTION(3, "I2S1_DO"), + MTK_FUNCTION(4, "SCP_SPI1_MI"), + MTK_FUNCTION(5, "LVTS_SDO"), + MTK_FUNCTION(6, "DFD_TMS"), + MTK_FUNCTION(7, "dbg_mon_b32") + ), + + MTK_PIN( + 56, "GPIO56", + MTK_EINT_FUNCTION(0, 56), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "I2S1_DO"), + MTK_FUNCTION(2, "I2S3_DO"), + MTK_FUNCTION(7, "dbg_mon_a23") + ), + + MTK_PIN( + 57, "GPIO57", + MTK_EINT_FUNCTION(0, 57), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "I2S1_BCK"), + MTK_FUNCTION(2, "I2S3_BCK"), + MTK_FUNCTION(7, "dbg_mon_a24") + ), + + MTK_PIN( + 58, "GPIO58", + MTK_EINT_FUNCTION(0, 58), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "I2S1_LRCK"), + MTK_FUNCTION(2, "I2S3_LRCK"), + MTK_FUNCTION(7, "dbg_mon_a25") + ), + + MTK_PIN( + 59, "GPIO59", + MTK_EINT_FUNCTION(0, 59), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "I2S1_MCK"), + MTK_FUNCTION(2, "I2S3_MCK"), + MTK_FUNCTION(7, "dbg_mon_a27") + ), + + MTK_PIN( + 60, "GPIO60", + MTK_EINT_FUNCTION(0, 60), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "TDM_RX_LRCK"), + MTK_FUNCTION(2, "ANT_SEL3"), + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N") + ), + + MTK_PIN( + 61, "GPIO61", + MTK_EINT_FUNCTION(0, 61), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "TDM_RX_BCK"), + MTK_FUNCTION(2, "ANT_SEL4"), + MTK_FUNCTION(4, "SPINOR_CK"), + MTK_FUNCTION(5, "CONN_MCU_DBGI_N") + ), + + MTK_PIN( + 62, "GPIO62", + MTK_EINT_FUNCTION(0, 62), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "TDM_RX_MCK"), + MTK_FUNCTION(2, "ANT_SEL5"), + MTK_FUNCTION(4, "SPINOR_CS"), + MTK_FUNCTION(5, "CONN_MCU_TDI") + ), + + MTK_PIN( + 63, "GPIO63", + MTK_EINT_FUNCTION(0, 63), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "TDM_RX_DATA0"), + MTK_FUNCTION(2, "ANT_SEL6"), + MTK_FUNCTION(4, "SPINOR_IO0"), + MTK_FUNCTION(5, "CONN_MCU_TRST_B") + ), + + MTK_PIN( + 64, "GPIO64", + MTK_EINT_FUNCTION(0, 64), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "TDM_RX_DATA1"), + MTK_FUNCTION(2, "ANT_SEL7"), + MTK_FUNCTION(3, "PWM0"), + MTK_FUNCTION(4, "SPINOR_IO1"), + MTK_FUNCTION(5, "CONN_MCU_TCK") + ), + + MTK_PIN( + 65, "GPIO65", + MTK_EINT_FUNCTION(0, 65), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "TDM_RX_DATA2"), + MTK_FUNCTION(2, "UCTS0"), + MTK_FUNCTION(3, "PWM1"), + MTK_FUNCTION(4, "SPINOR_IO2"), + MTK_FUNCTION(5, "CONN_MCU_TDO"), + MTK_FUNCTION(6, "TP_UCTS1_AO"), + MTK_FUNCTION(7, "TP_UCTS2_AO") + ), + + MTK_PIN( + 66, "GPIO66", + MTK_EINT_FUNCTION(0, 66), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "TDM_RX_DATA3"), + MTK_FUNCTION(2, "URTS0"), + MTK_FUNCTION(3, "PWM2"), + MTK_FUNCTION(4, "SPINOR_IO3"), + MTK_FUNCTION(5, "CONN_MCU_TMS"), + MTK_FUNCTION(6, "TP_URTS1_AO"), + MTK_FUNCTION(7, "TP_URTS2_AO") + ), + + MTK_PIN( + 67, "GPIO67", + MTK_EINT_FUNCTION(0, 67), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "MSDC0_DSL") + ), + + MTK_PIN( + 68, "GPIO68", + MTK_EINT_FUNCTION(0, 68), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "MSDC0_CLK") + ), + + MTK_PIN( + 69, "GPIO69", + MTK_EINT_FUNCTION(0, 69), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "MSDC0_CMD") + ), + + MTK_PIN( + 70, "GPIO70", + MTK_EINT_FUNCTION(0, 70), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "MSDC0_RSTB") + ), + + MTK_PIN( + 71, "GPIO71", + MTK_EINT_FUNCTION(0, 71), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "MSDC0_DAT0") + ), + + MTK_PIN( + 72, "GPIO72", + MTK_EINT_FUNCTION(0, 72), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "MSDC0_DAT1") + ), + + MTK_PIN( + 73, "GPIO73", + MTK_EINT_FUNCTION(0, 73), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "MSDC0_DAT2") + ), + + MTK_PIN( + 74, "GPIO74", + MTK_EINT_FUNCTION(0, 74), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "MSDC0_DAT3") + ), + + MTK_PIN( + 75, "GPIO75", + MTK_EINT_FUNCTION(0, 75), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "MSDC0_DAT4") + ), + + MTK_PIN( + 76, "GPIO76", + MTK_EINT_FUNCTION(0, 76), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "MSDC0_DAT5") + ), + + MTK_PIN( + 77, "GPIO77", + MTK_EINT_FUNCTION(0, 77), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "MSDC0_DAT6") + ), + + MTK_PIN( + 78, "GPIO78", + MTK_EINT_FUNCTION(0, 78), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "MSDC0_DAT7") + ), + + MTK_PIN( + 79, "GPIO79", + MTK_EINT_FUNCTION(0, 79), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "KPCOL0") + ), + + MTK_PIN( + 80, "GPIO80", + MTK_EINT_FUNCTION(0, 80), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "KPCOL1"), + MTK_FUNCTION(2, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(3, "PWM0"), + MTK_FUNCTION(4, "CLKM0") + ), + + MTK_PIN( + 81, "GPIO81", + MTK_EINT_FUNCTION(0, 81), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "KPROW0"), + MTK_FUNCTION(3, "PWM1"), + MTK_FUNCTION(4, "CLKM1") + ), + + MTK_PIN( + 82, "GPIO82", + MTK_EINT_FUNCTION(0, 82), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "KPROW1"), + MTK_FUNCTION(3, "PWM2"), + MTK_FUNCTION(4, "CLKM2") + ), + + MTK_PIN( + 83, "GPIO83", + MTK_EINT_FUNCTION(0, 83), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "AP_GOOD"), + MTK_FUNCTION(2, "GPS_PPS"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(7, "dbg_mon_a28") + ), + + MTK_PIN( + 84, "GPIO84", + MTK_EINT_FUNCTION(0, 84), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "ADSP_JTAG_TCK"), + MTK_FUNCTION(4, "UDI_TCK"), + MTK_FUNCTION(5, "CONN_DSP_JCK"), + MTK_FUNCTION(6, "SSPM_JTAG_TCK"), + MTK_FUNCTION(7, "DFD_TCK_XI") + ), + + MTK_PIN( + 85, "GPIO85", + MTK_EINT_FUNCTION(0, 85), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(2, "ADSP_JTAG_TMS"), + MTK_FUNCTION(3, "CONN_MCU_AICE_TMSC"), + MTK_FUNCTION(4, "UDI_TMS"), + MTK_FUNCTION(5, "CONN_DSP_JMS"), + MTK_FUNCTION(6, "SSPM_JTAG_TMS"), + MTK_FUNCTION(7, "DFD_TMS") + ), + + MTK_PIN( + 86, "GPIO86", + MTK_EINT_FUNCTION(0, 86), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "ADSP_JTAG_TDI"), + MTK_FUNCTION(4, "UDI_TDI"), + MTK_FUNCTION(5, "CONN_DSP_JDI"), + MTK_FUNCTION(6, "SSPM_JTAG_TDI"), + MTK_FUNCTION(7, "DFD_TDI") + ), + + MTK_PIN( + 87, "GPIO87", + MTK_EINT_FUNCTION(0, 87), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "ADSP_JTAG_TDO"), + MTK_FUNCTION(4, "UDI_TDO"), + MTK_FUNCTION(5, "CONN_DSP_JDO"), + MTK_FUNCTION(6, "SSPM_JTAG_TDO"), + MTK_FUNCTION(7, "DFD_TDO") + ), + + MTK_PIN( + 88, "GPIO88", + MTK_EINT_FUNCTION(0, 88), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "ADSP_JTAG_TRSTN"), + MTK_FUNCTION(3, "CONN_MCU_AICE_TCKC"), + MTK_FUNCTION(4, "UDI_NTRST"), + MTK_FUNCTION(5, "CONN_WIFI_TXD"), + MTK_FUNCTION(6, "SSPM_JTAG_TRSTN") + ), + + MTK_PIN( + 89, "GPIO89", + MTK_EINT_FUNCTION(0, 89), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(5, "CONN_DSP_JINTP") + ), + + MTK_PIN( + 90, "GPIO90", + MTK_EINT_FUNCTION(0, 90), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "IDDIG_P0"), + MTK_FUNCTION(4, "PGD_HV_HSC_PWR4"), + MTK_FUNCTION(5, "GDU_SUM_TROOP2_2") + ), + + MTK_PIN( + 91, "GPIO91", + MTK_EINT_FUNCTION(0, 91), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "USB_DRVVBUS_P0"), + MTK_FUNCTION(4, "PGD_HV_HSC_PWR5"), + MTK_FUNCTION(5, "GDU_TROOPS_DET0") + ), + + MTK_PIN( + 92, "GPIO92", + MTK_EINT_FUNCTION(0, 92), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "VBUS_VALID_P0"), + MTK_FUNCTION(4, "PGD_DA_EFUSE_RDY"), + MTK_FUNCTION(5, "GDU_TROOPS_DET1") + ), + + MTK_PIN( + 93, "GPIO93", + MTK_EINT_FUNCTION(0, 93), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "IDDIG_P1"), + MTK_FUNCTION(2, "PWM0"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(4, "PGD_DA_EFUSE_RDY_PRE"), + MTK_FUNCTION(5, "GDU_TROOPS_DET2") + ), + + MTK_PIN( + 94, "GPIO94", + MTK_EINT_FUNCTION(0, 94), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "USB_DRVVBUS_P1"), + MTK_FUNCTION(2, "PWM1"), + MTK_FUNCTION(3, "CLKM1"), + MTK_FUNCTION(4, "PGD_DA_PWRGD_RESET") + ), + + MTK_PIN( + 95, "GPIO95", + MTK_EINT_FUNCTION(0, 95), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "VBUS_VALID_P1"), + MTK_FUNCTION(2, "PWM2"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(4, "PGD_DA_PWRGD_ENB") + ), + + MTK_PIN( + 96, "GPIO96", + MTK_EINT_FUNCTION(0, 96), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "DSI_TE"), + MTK_FUNCTION(7, "dbg_mon_a29") + ), + + MTK_PIN( + 97, "GPIO97", + MTK_EINT_FUNCTION(0, 97), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(7, "dbg_mon_a30") + ), + + MTK_PIN( + 98, "GPIO98", + MTK_EINT_FUNCTION(0, 98), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "LCM_RST") + ), + + MTK_PIN( + 99, "GPIO99", + MTK_EINT_FUNCTION(0, 99), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "DPI_PCLK"), + MTK_FUNCTION(2, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(3, "SSPM_JTAG_TCK"), + MTK_FUNCTION(5, "ANT_SEL0"), + MTK_FUNCTION(6, "TP_GPIO0_AO"), + MTK_FUNCTION(7, "PGD_LV_LSC_PWR0") + ), + + MTK_PIN( + 100, "GPIO100", + MTK_EINT_FUNCTION(0, 100), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "DPI_VSYNC"), + MTK_FUNCTION(2, "KPCOL2"), + MTK_FUNCTION(3, "SSPM_JTAG_TMS"), + MTK_FUNCTION(5, "ANT_SEL1"), + MTK_FUNCTION(6, "TP_GPIO1_AO"), + MTK_FUNCTION(7, "PGD_LV_LSC_PWR1") + ), + + MTK_PIN( + 101, "GPIO101", + MTK_EINT_FUNCTION(0, 101), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "DPI_HSYNC"), + MTK_FUNCTION(2, "KPROW2"), + MTK_FUNCTION(3, "SSPM_JTAG_TDI"), + MTK_FUNCTION(5, "ANT_SEL2"), + MTK_FUNCTION(6, "TP_GPIO2_AO"), + MTK_FUNCTION(7, "PGD_LV_LSC_PWR2") + ), + + MTK_PIN( + 102, "GPIO102", + MTK_EINT_FUNCTION(0, 102), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "DPI_DE"), + MTK_FUNCTION(3, "SSPM_JTAG_TDO"), + MTK_FUNCTION(5, "ANT_SEL3"), + MTK_FUNCTION(6, "TP_GPIO3_AO"), + MTK_FUNCTION(7, "PGD_LV_LSC_PWR3") + ), + + MTK_PIN( + 103, "GPIO103", + MTK_EINT_FUNCTION(0, 103), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "DPI_DATA0"), + MTK_FUNCTION(3, "SSPM_JTAG_TRSTN"), + MTK_FUNCTION(4, "CLKM0"), + MTK_FUNCTION(5, "ANT_SEL4"), + MTK_FUNCTION(6, "TP_GPIO4_AO"), + MTK_FUNCTION(7, "PGD_LV_LSC_PWR4") + ), + + MTK_PIN( + 104, "GPIO104", + MTK_EINT_FUNCTION(0, 104), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "DPI_DATA1"), + MTK_FUNCTION(2, "GPS_PPS"), + MTK_FUNCTION(3, "UCTS2"), + MTK_FUNCTION(4, "CLKM1"), + MTK_FUNCTION(5, "ANT_SEL5"), + MTK_FUNCTION(6, "TP_GPIO5_AO"), + MTK_FUNCTION(7, "PGD_LV_LSC_PWR5") + ), + + MTK_PIN( + 105, "GPIO105", + MTK_EINT_FUNCTION(0, 105), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "DPI_DATA2"), + MTK_FUNCTION(2, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(3, "URTS2"), + MTK_FUNCTION(4, "CLKM2"), + MTK_FUNCTION(5, "ANT_SEL6"), + MTK_FUNCTION(6, "TP_GPIO6_AO"), + MTK_FUNCTION(7, "PGD_LV_HSC_PWR0") + ), + + MTK_PIN( + 106, "GPIO106", + MTK_EINT_FUNCTION(0, 106), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "DPI_DATA3"), + MTK_FUNCTION(2, "TP_UTXD1_AO"), + MTK_FUNCTION(3, "UTXD2"), + MTK_FUNCTION(4, "PWM0"), + MTK_FUNCTION(5, "ANT_SEL7"), + MTK_FUNCTION(6, "TP_GPIO7_AO"), + MTK_FUNCTION(7, "PGD_LV_HSC_PWR1") + ), + + MTK_PIN( + 107, "GPIO107", + MTK_EINT_FUNCTION(0, 107), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "DPI_DATA4"), + MTK_FUNCTION(2, "TP_URXD1_AO"), + MTK_FUNCTION(3, "URXD2"), + MTK_FUNCTION(4, "PWM1"), + MTK_FUNCTION(6, "GDU_SUM_TROOP0_0"), + MTK_FUNCTION(7, "PGD_LV_HSC_PWR2") + ), + + MTK_PIN( + 108, "GPIO108", + MTK_EINT_FUNCTION(0, 108), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "DPI_DATA5"), + MTK_FUNCTION(2, "TP_UCTS1_AO"), + MTK_FUNCTION(3, "UCTS0"), + MTK_FUNCTION(4, "PWM2"), + MTK_FUNCTION(6, "GDU_SUM_TROOP0_1"), + MTK_FUNCTION(7, "PGD_LV_HSC_PWR3") + ), + + MTK_PIN( + 109, "GPIO109", + MTK_EINT_FUNCTION(0, 109), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "DPI_DATA6"), + MTK_FUNCTION(2, "TP_URTS1_AO"), + MTK_FUNCTION(3, "URTS0"), + MTK_FUNCTION(4, "I2S0_DI"), + MTK_FUNCTION(5, "I2S2_DI"), + MTK_FUNCTION(6, "GDU_SUM_TROOP0_2"), + MTK_FUNCTION(7, "PGD_LV_HSC_PWR4") + ), + + MTK_PIN( + 110, "GPIO110", + MTK_EINT_FUNCTION(0, 110), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "DPI_DATA7"), + MTK_FUNCTION(2, "TP_UCTS2_AO"), + MTK_FUNCTION(3, "UCTS1"), + MTK_FUNCTION(4, "I2S3_BCK"), + MTK_FUNCTION(5, "I2S1_BCK"), + MTK_FUNCTION(6, "GDU_SUM_TROOP1_0"), + MTK_FUNCTION(7, "PGD_LV_HSC_PWR5") + ), + + MTK_PIN( + 111, "GPIO111", + MTK_EINT_FUNCTION(0, 111), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "DPI_DATA8"), + MTK_FUNCTION(2, "TP_URTS2_AO"), + MTK_FUNCTION(3, "URTS1"), + MTK_FUNCTION(4, "I2S3_MCK"), + MTK_FUNCTION(5, "I2S1_MCK"), + MTK_FUNCTION(6, "GDU_SUM_TROOP1_1"), + MTK_FUNCTION(7, "PGD_HV_HSC_PWR0") + ), + + MTK_PIN( + 112, "GPIO112", + MTK_EINT_FUNCTION(0, 112), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "DPI_DATA9"), + MTK_FUNCTION(2, "TP_URXD2_AO"), + MTK_FUNCTION(3, "URXD1"), + MTK_FUNCTION(4, "I2S3_LRCK"), + MTK_FUNCTION(5, "I2S1_LRCK"), + MTK_FUNCTION(6, "GDU_SUM_TROOP1_2"), + MTK_FUNCTION(7, "PGD_HV_HSC_PWR1") + ), + + MTK_PIN( + 113, "GPIO113", + MTK_EINT_FUNCTION(0, 113), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "DPI_DATA10"), + MTK_FUNCTION(2, "TP_UTXD2_AO"), + MTK_FUNCTION(3, "UTXD1"), + MTK_FUNCTION(4, "I2S3_DO"), + MTK_FUNCTION(5, "I2S1_DO"), + MTK_FUNCTION(6, "GDU_SUM_TROOP2_0"), + MTK_FUNCTION(7, "PGD_HV_HSC_PWR2") + ), + + MTK_PIN( + 114, "GPIO114", + MTK_EINT_FUNCTION(0, 114), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "DPI_DATA11"), + MTK_FUNCTION(6, "GDU_SUM_TROOP2_1"), + MTK_FUNCTION(7, "PGD_HV_HSC_PWR3") + ), + + MTK_PIN( + 115, "GPIO115", + MTK_EINT_FUNCTION(0, 115), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "PCM_CLK"), + MTK_FUNCTION(2, "I2S0_BCK"), + MTK_FUNCTION(3, "I2S2_BCK") + ), + + MTK_PIN( + 116, "GPIO116", + MTK_EINT_FUNCTION(0, 116), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "PCM_SYNC"), + MTK_FUNCTION(2, "I2S0_LRCK"), + MTK_FUNCTION(3, "I2S2_LRCK") + ), + + MTK_PIN( + 117, "GPIO117", + MTK_EINT_FUNCTION(0, 117), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "PCM_DI"), + MTK_FUNCTION(2, "I2S0_DI"), + MTK_FUNCTION(3, "I2S2_DI") + ), + + MTK_PIN( + 118, "GPIO118", + MTK_EINT_FUNCTION(0, 118), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "PCM_DO"), + MTK_FUNCTION(2, "I2S0_MCK"), + MTK_FUNCTION(3, "I2S2_MCK"), + MTK_FUNCTION(4, "I2S3_DO"), + MTK_FUNCTION(5, "I2S1_DO") + ), + + MTK_PIN( + 119, "GPIO119", + MTK_EINT_FUNCTION(0, 119), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "JTMS_SEL1"), + MTK_FUNCTION(2, "UDI_TMS"), + MTK_FUNCTION(3, "DFD_TMS"), + MTK_FUNCTION(4, "SPM_JTAG_TMS"), + MTK_FUNCTION(5, "SCP_JTAG_TMS"), + MTK_FUNCTION(6, "ADSP_JTAG_TMS") + ), + + MTK_PIN( + 120, "GPIO120", + MTK_EINT_FUNCTION(0, 120), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "JTCK_SEL1"), + MTK_FUNCTION(2, "UDI_TCK"), + MTK_FUNCTION(3, "DFD_TCK_XI"), + MTK_FUNCTION(4, "SPM_JTAG_TCK"), + MTK_FUNCTION(5, "SCP_JTAG_TCK"), + MTK_FUNCTION(6, "ADSP_JTAG_TCK") + ), + + MTK_PIN( + 121, "GPIO121", + MTK_EINT_FUNCTION(0, 121), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "JTDI_SEL1"), + MTK_FUNCTION(2, "UDI_TDI"), + MTK_FUNCTION(3, "DFD_TDI"), + MTK_FUNCTION(4, "SPM_JTAG_TDI"), + MTK_FUNCTION(5, "SCP_JTAG_TDI"), + MTK_FUNCTION(6, "ADSP_JTAG_TDI") + ), + + MTK_PIN( + 122, "GPIO122", + MTK_EINT_FUNCTION(0, 122), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "JTDO_SEL1"), + MTK_FUNCTION(2, "UDI_TDO"), + MTK_FUNCTION(3, "DFD_TDO"), + MTK_FUNCTION(4, "SPM_JTAG_TDO"), + MTK_FUNCTION(5, "SCP_JTAG_TDO"), + MTK_FUNCTION(6, "ADSP_JTAG_TDO") + ), + + MTK_PIN( + 123, "GPIO123", + MTK_EINT_FUNCTION(0, 123), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "JTRSTN_SEL1"), + MTK_FUNCTION(2, "UDI_NTRST"), + MTK_FUNCTION(4, "SPM_JTAG_TRSTN"), + MTK_FUNCTION(5, "SCP_JTAG_TRSTN"), + MTK_FUNCTION(6, "ADSP_JTAG_TRSTN") + ), + + MTK_PIN( + 124, "GPIO124", + MTK_EINT_FUNCTION(0, 124), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "CMMCLK0"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "PWM0") + ), + + MTK_PIN( + 125, "GPIO125", + MTK_EINT_FUNCTION(0, 125), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "CMMCLK1"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "PWM1"), + MTK_FUNCTION(7, "dbg_mon_b0") + ), + + MTK_PIN( + 126, "GPIO126", + MTK_EINT_FUNCTION(0, 126), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "CMMCLK2"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "PWM2"), + MTK_FUNCTION(7, "dbg_mon_b1") + ), + + MTK_PIN( + 127, "GPIO127", + MTK_EINT_FUNCTION(0, 127), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "SCL0"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1") + ), + + MTK_PIN( + 128, "GPIO128", + MTK_EINT_FUNCTION(0, 128), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "SDA0"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1") + ), + + MTK_PIN( + 129, "GPIO129", + MTK_EINT_FUNCTION(0, 129), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "SCL1"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1"), + MTK_FUNCTION(7, "dbg_mon_b4") + ), + + MTK_PIN( + 130, "GPIO130", + MTK_EINT_FUNCTION(0, 130), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "SDA1"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1"), + MTK_FUNCTION(7, "dbg_mon_b5") + ), + + MTK_PIN( + 131, "GPIO131", + MTK_EINT_FUNCTION(0, 131), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "SCL2"), + MTK_FUNCTION(2, "SSPM_UTXD_AO"), + MTK_FUNCTION(3, "CONN_UART0_TXD"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1"), + MTK_FUNCTION(7, "dbg_mon_b6") + ), + + MTK_PIN( + 132, "GPIO132", + MTK_EINT_FUNCTION(0, 132), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "SDA2"), + MTK_FUNCTION(2, "SSPM_URXD_AO"), + MTK_FUNCTION(3, "CONN_UART0_RXD"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1"), + MTK_FUNCTION(7, "dbg_mon_b7") + ), + + MTK_PIN( + 133, "GPIO133", + MTK_EINT_FUNCTION(0, 133), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "SCL3"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1"), + MTK_FUNCTION(7, "dbg_mon_b8") + ), + + MTK_PIN( + 134, "GPIO134", + MTK_EINT_FUNCTION(0, 134), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "SDA3"), + MTK_FUNCTION(3, "GPS_PPS"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1"), + MTK_FUNCTION(7, "dbg_mon_b9") + ), + + MTK_PIN( + 135, "GPIO135", + MTK_EINT_FUNCTION(0, 135), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "SCL4"), + MTK_FUNCTION(2, "TP_UTXD1_AO"), + MTK_FUNCTION(3, "UTXD1"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1"), + MTK_FUNCTION(7, "dbg_mon_b10") + ), + + MTK_PIN( + 136, "GPIO136", + MTK_EINT_FUNCTION(0, 136), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "SDA4"), + MTK_FUNCTION(2, "TP_URXD1_AO"), + MTK_FUNCTION(3, "URXD1"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1"), + MTK_FUNCTION(7, "dbg_mon_b11") + ), + + MTK_PIN( + 137, "GPIO137", + MTK_EINT_FUNCTION(0, 137), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "SCL5"), + MTK_FUNCTION(2, "UTXD2"), + MTK_FUNCTION(3, "UCTS1"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1") + ), + + MTK_PIN( + 138, "GPIO138", + MTK_EINT_FUNCTION(0, 138), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "SDA5"), + MTK_FUNCTION(2, "URXD2"), + MTK_FUNCTION(3, "URTS1"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1") + ), + + MTK_PIN( + 139, "GPIO139", + MTK_EINT_FUNCTION(0, 139), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "SCL6"), + MTK_FUNCTION(2, "UTXD1"), + MTK_FUNCTION(3, "TP_UTXD1_AO"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1"), + MTK_FUNCTION(7, "dbg_mon_b12") + ), + + MTK_PIN( + 140, "GPIO140", + MTK_EINT_FUNCTION(0, 140), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "SDA6"), + MTK_FUNCTION(2, "URXD1"), + MTK_FUNCTION(3, "TP_URXD1_AO"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1"), + MTK_FUNCTION(7, "dbg_mon_b13") + ), + + MTK_PIN( + 141, "GPIO141", + MTK_EINT_FUNCTION(0, 141), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "SCL7"), + MTK_FUNCTION(2, "URTS0"), + MTK_FUNCTION(3, "TP_URTS1_AO"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1"), + MTK_FUNCTION(6, "UDI_TCK"), + MTK_FUNCTION(7, "dbg_mon_b14") + ), + + MTK_PIN( + 142, "GPIO142", + MTK_EINT_FUNCTION(0, 142), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "SDA7"), + MTK_FUNCTION(2, "UCTS0"), + MTK_FUNCTION(3, "TP_UCTS1_AO"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1") + ), + + MTK_PIN( + 143, "GPIO143", + MTK_EINT_FUNCTION(0, 143), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "SCL8"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1"), + MTK_FUNCTION(7, "dbg_mon_b16") + ), + + MTK_PIN( + 144, "GPIO144", + MTK_EINT_FUNCTION(0, 144), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "SDA8"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1"), + MTK_FUNCTION(7, "dbg_mon_b17") + ), + + MTK_PIN( + 145, "GPIO145", + MTK_EINT_FUNCTION(0, 145), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "SCL9"), + MTK_FUNCTION(2, "CMVREF1"), + MTK_FUNCTION(3, "GPS_PPS"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1"), + MTK_FUNCTION(7, "dbg_mon_b18") + ), + + MTK_PIN( + 146, "GPIO146", + MTK_EINT_FUNCTION(0, 146), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "SDA9"), + MTK_FUNCTION(2, "CMVREF0"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1"), + MTK_FUNCTION(7, "dbg_mon_b19") + ), + + MTK_PIN( + 147, "GPIO147", + MTK_EINT_FUNCTION(0, 147), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "CMFLASH0"), + MTK_FUNCTION(2, "LVTS_SDI"), + MTK_FUNCTION(3, "DPI_DATA12"), + MTK_FUNCTION(4, "TP_GPIO0_AO"), + MTK_FUNCTION(5, "ANT_SEL3"), + MTK_FUNCTION(6, "DFD_TCK_XI"), + MTK_FUNCTION(7, "dbg_mon_b20") + ), + + MTK_PIN( + 148, "GPIO148", + MTK_EINT_FUNCTION(0, 148), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "CMFLASH1"), + MTK_FUNCTION(2, "LVTS_SCF"), + MTK_FUNCTION(3, "DPI_DATA13"), + MTK_FUNCTION(4, "TP_GPIO1_AO"), + MTK_FUNCTION(5, "ANT_SEL4"), + MTK_FUNCTION(6, "DFD_TMS"), + MTK_FUNCTION(7, "dbg_mon_b21") + ), + + MTK_PIN( + 149, "GPIO149", + MTK_EINT_FUNCTION(0, 149), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(1, "CMFLASH2"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "DPI_DATA14"), + MTK_FUNCTION(4, "TP_GPIO2_AO"), + MTK_FUNCTION(5, "ANT_SEL5"), + MTK_FUNCTION(6, "DFD_TDI"), + MTK_FUNCTION(7, "dbg_mon_b22") + ), + + MTK_PIN( + 150, "GPIO150", + MTK_EINT_FUNCTION(0, 150), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "DPI_DATA15"), + MTK_FUNCTION(4, "TP_GPIO3_AO"), + MTK_FUNCTION(5, "ANT_SEL6"), + MTK_FUNCTION(6, "DFD_TDO"), + MTK_FUNCTION(7, "dbg_mon_b23") + ), + + MTK_PIN( + 151, "GPIO151", + MTK_EINT_FUNCTION(0, 151), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(1, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "DPI_DATA16"), + MTK_FUNCTION(4, "TP_GPIO4_AO"), + MTK_FUNCTION(5, "ANT_SEL7"), + MTK_FUNCTION(6, "UDI_TMS"), + MTK_FUNCTION(7, "dbg_mon_b24") + ), + + MTK_PIN( + 152, "GPIO152", + MTK_EINT_FUNCTION(0, 152), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "DPI_DATA17"), + MTK_FUNCTION(4, "TP_GPIO5_AO") + ), + + MTK_PIN( + 153, "GPIO153", + MTK_EINT_FUNCTION(0, 153), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(1, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(3, "DPI_DATA18"), + MTK_FUNCTION(4, "TP_GPIO6_AO"), + MTK_FUNCTION(6, "UDI_TDI"), + MTK_FUNCTION(7, "dbg_mon_b26") + ), + + MTK_PIN( + 154, "GPIO154", + MTK_EINT_FUNCTION(0, 154), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO154"), + MTK_FUNCTION(1, "PWM0"), + MTK_FUNCTION(2, "CMVREF2"), + MTK_FUNCTION(3, "DPI_DATA19"), + MTK_FUNCTION(4, "TP_GPIO7_AO"), + MTK_FUNCTION(6, "UDI_TDO"), + MTK_FUNCTION(7, "dbg_mon_b27") + ), + + MTK_PIN( + 155, "GPIO155", + MTK_EINT_FUNCTION(0, 155), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO155"), + MTK_FUNCTION(1, "PWM1"), + MTK_FUNCTION(2, "CMVREF1"), + MTK_FUNCTION(3, "DPI_DATA20"), + MTK_FUNCTION(6, "UDI_NTRST"), + MTK_FUNCTION(7, "dbg_mon_b28") + ), + + MTK_PIN( + 156, "GPIO156", + MTK_EINT_FUNCTION(0, 156), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO156"), + MTK_FUNCTION(1, "PWM2"), + MTK_FUNCTION(2, "CMVREF0"), + MTK_FUNCTION(3, "DPI_DATA21") + ), + + MTK_PIN( + 157, "GPIO157", + MTK_EINT_FUNCTION(0, 157), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO157"), + MTK_FUNCTION(1, "PWRAP_SPI0_CSN") + ), + + MTK_PIN( + 158, "GPIO158", + MTK_EINT_FUNCTION(0, 158), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO158"), + MTK_FUNCTION(1, "PWRAP_SPI0_CK") + ), + + MTK_PIN( + 159, "GPIO159", + MTK_EINT_FUNCTION(0, 159), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO159"), + MTK_FUNCTION(1, "PWRAP_SPI0_MO"), + MTK_FUNCTION(2, "PWRAP_SPI0_MI") + ), + + MTK_PIN( + 160, "GPIO160", + MTK_EINT_FUNCTION(0, 160), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO160"), + MTK_FUNCTION(1, "PWRAP_SPI0_MI"), + MTK_FUNCTION(2, "PWRAP_SPI0_MO") + ), + + MTK_PIN( + 161, "GPIO161", + MTK_EINT_FUNCTION(0, 161), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO161"), + MTK_FUNCTION(1, "SRCLKENA0") + ), + + MTK_PIN( + 162, "GPIO162", + MTK_EINT_FUNCTION(0, 162), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO162"), + MTK_FUNCTION(1, "SRCLKENA1"), + MTK_FUNCTION(7, "dbg_mon_a31") + ), + + MTK_PIN( + 163, "GPIO163", + MTK_EINT_FUNCTION(0, 163), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO163"), + MTK_FUNCTION(1, "SCP_VREQ_VAO"), + MTK_FUNCTION(2, "DVFSRC_EXT_REQ") + ), + + MTK_PIN( + 164, "GPIO164", + MTK_EINT_FUNCTION(0, 164), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO164"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + + MTK_PIN( + 165, "GPIO165", + MTK_EINT_FUNCTION(0, 165), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO165"), + MTK_FUNCTION(1, "WATCHDOG") + ), + + MTK_PIN( + 166, "GPIO166", + MTK_EINT_FUNCTION(0, 166), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO166"), + MTK_FUNCTION(1, "AUD_CLK_MOSI"), + MTK_FUNCTION(2, "AUD_CLK_MISO"), + MTK_FUNCTION(3, "I2S1_MCK") + ), + + MTK_PIN( + 167, "GPIO167", + MTK_EINT_FUNCTION(0, 167), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO167"), + MTK_FUNCTION(1, "AUD_SYNC_MOSI"), + MTK_FUNCTION(2, "AUD_SYNC_MISO"), + MTK_FUNCTION(3, "I2S1_BCK") + ), + + MTK_PIN( + 168, "GPIO168", + MTK_EINT_FUNCTION(0, 168), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO168"), + MTK_FUNCTION(1, "AUD_DAT_MOSI0"), + MTK_FUNCTION(2, "AUD_DAT_MISO0"), + MTK_FUNCTION(3, "I2S1_LRCK") + ), + + MTK_PIN( + 169, "GPIO169", + MTK_EINT_FUNCTION(0, 169), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO169"), + MTK_FUNCTION(1, "AUD_DAT_MOSI1"), + MTK_FUNCTION(2, "AUD_DAT_MISO1"), + MTK_FUNCTION(3, "I2S1_DO") + ), + + MTK_PIN( + 170, "GPIO170", + MTK_EINT_FUNCTION(0, 170), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO170"), + MTK_FUNCTION(1, "AUD_CLK_MISO"), + MTK_FUNCTION(2, "AUD_CLK_MOSI"), + MTK_FUNCTION(3, "I2S2_MCK") + ), + + MTK_PIN( + 171, "GPIO171", + MTK_EINT_FUNCTION(0, 171), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO171"), + MTK_FUNCTION(1, "AUD_SYNC_MISO"), + MTK_FUNCTION(2, "AUD_SYNC_MOSI"), + MTK_FUNCTION(3, "I2S2_BCK") + ), + + MTK_PIN( + 172, "GPIO172", + MTK_EINT_FUNCTION(0, 172), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO172"), + MTK_FUNCTION(1, "AUD_DAT_MISO0"), + MTK_FUNCTION(2, "AUD_DAT_MOSI0"), + MTK_FUNCTION(3, "I2S2_LRCK"), + MTK_FUNCTION(4, "VOW_DAT_MISO") + ), + + MTK_PIN( + 173, "GPIO173", + MTK_EINT_FUNCTION(0, 173), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO173"), + MTK_FUNCTION(1, "AUD_DAT_MISO1"), + MTK_FUNCTION(2, "AUD_DAT_MOSI1"), + MTK_FUNCTION(3, "I2S2_DI"), + MTK_FUNCTION(4, "VOW_CLK_MISO") + ), + + MTK_PIN( + 174, "GPIO174", + MTK_EINT_FUNCTION(0, 174), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO174"), + MTK_FUNCTION(1, "CONN_TOP_CLK"), + MTK_FUNCTION(2, "AUXIF_CLK"), + MTK_FUNCTION(3, "DFD_TCK_XI"), + MTK_FUNCTION(7, "dbg_mon_b3") + ), + + MTK_PIN( + 175, "GPIO175", + MTK_EINT_FUNCTION(0, 175), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO175"), + MTK_FUNCTION(1, "CONN_TOP_DATA"), + MTK_FUNCTION(2, "AUXIF_ST"), + MTK_FUNCTION(3, "DFD_TMS"), + MTK_FUNCTION(7, "dbg_mon_b15") + ), + + MTK_PIN( + 176, "GPIO176", + MTK_EINT_FUNCTION(0, 176), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO176"), + MTK_FUNCTION(1, "CONN_BT_CLK"), + MTK_FUNCTION(3, "DFD_TDI"), + MTK_FUNCTION(7, "dbg_mon_b2") + ), + + MTK_PIN( + 177, "GPIO177", + MTK_EINT_FUNCTION(0, 177), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO177"), + MTK_FUNCTION(1, "CONN_BT_DATA"), + MTK_FUNCTION(3, "DFD_TDO") + ), + + MTK_PIN( + 178, "GPIO178", + MTK_EINT_FUNCTION(0, 178), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO178"), + MTK_FUNCTION(1, "CONN_HRST_B"), + MTK_FUNCTION(3, "UDI_TMS"), + MTK_FUNCTION(7, "dbg_mon_b25") + ), + + MTK_PIN( + 179, "GPIO179", + MTK_EINT_FUNCTION(0, 179), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO179"), + MTK_FUNCTION(1, "CONN_WB_PTA"), + MTK_FUNCTION(3, "UDI_TCK"), + MTK_FUNCTION(7, "dbg_mon_b29") + ), + + MTK_PIN( + 180, "GPIO180", + MTK_EINT_FUNCTION(0, 180), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO180"), + MTK_FUNCTION(1, "CONN_WF_CTRL0"), + MTK_FUNCTION(3, "UDI_TDI") + ), + + MTK_PIN( + 181, "GPIO181", + MTK_EINT_FUNCTION(0, 181), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO181"), + MTK_FUNCTION(1, "CONN_WF_CTRL1"), + MTK_FUNCTION(3, "UDI_TDO") + ), + + MTK_PIN( + 182, "GPIO182", + MTK_EINT_FUNCTION(0, 182), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO182"), + MTK_FUNCTION(1, "CONN_WF_CTRL2"), + MTK_FUNCTION(3, "UDI_NTRST") + ), + + MTK_PIN( + 183, "GPIO183", + MTK_EINT_FUNCTION(0, 183), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO183"), + MTK_FUNCTION(1, "SPMI_SCL") + ), + + MTK_PIN( + 184, "GPIO184", + MTK_EINT_FUNCTION(0, 184), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO184"), + MTK_FUNCTION(1, "SPMI_SDA") + ), + + MTK_PIN( + 185, "GPIO185", + MTK_EINT_FUNCTION(0, 197), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 186, "GPIO186", + MTK_EINT_FUNCTION(0, 198), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 187, "GPIO187", + MTK_EINT_FUNCTION(0, 199), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 188, "GPIO188", + MTK_EINT_FUNCTION(0, 200), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 189, "GPIO189", + MTK_EINT_FUNCTION(0, 201), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 190, "GPIO190", + MTK_EINT_FUNCTION(0, 202), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 191, "GPIO191", + MTK_EINT_FUNCTION(0, 203), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 192, "GPIO192", + MTK_EINT_FUNCTION(0, 204), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 193, "GPIO193", + MTK_EINT_FUNCTION(0, 205), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 194, "GPIO194", + MTK_EINT_FUNCTION(0, 206), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 195, "GPIO195", + MTK_EINT_FUNCTION(0, 207), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 196, "GPIO196", + MTK_EINT_FUNCTION(0, 208), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ) +}; + +#endif /* __PINCTRL_MTK_MT8186_H */ diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index f9f9110f2107..74517e810958 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -48,6 +48,53 @@ static const char * const mtk_gpio_functions[] = { "func12", "func13", "func14", "func15", }; +/* + * This section supports converting to/from custom MTK_PIN_CONFIG_DRV_ADV + * and standard PIN_CONFIG_DRIVE_STRENGTH_UA pin configs. + * + * The custom value encodes three hardware bits as follows: + * + * | Bits | + * | 2 (E1) | 1 (E0) | 0 (EN) | drive strength (uA) + * ------------------------------------------------ + * | x | x | 0 | disabled, use standard drive strength + * ------------------------------------- + * | 0 | 0 | 1 | 125 uA + * | 0 | 1 | 1 | 250 uA + * | 1 | 0 | 1 | 500 uA + * | 1 | 1 | 1 | 1000 uA + */ +static const int mtk_drv_adv_uA[] = { 125, 250, 500, 1000 }; + +static int mtk_drv_adv_to_uA(int val) +{ + /* This should never happen. */ + if (WARN_ON_ONCE(val < 0 || val > 7)) + return -EINVAL; + + /* Bit 0 simply enables this hardware part */ + if (!(val & BIT(0))) + return -EINVAL; + + return mtk_drv_adv_uA[(val >> 1)]; +} + +static int mtk_drv_uA_to_adv(int val) +{ + switch (val) { + case 125: + return 0x1; + case 250: + return 0x3; + case 500: + return 0x5; + case 1000: + return 0x7; + } + + return -EINVAL; +} + static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin) @@ -79,41 +126,34 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, { struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); u32 param = pinconf_to_config_param(*config); - int pullup, err, reg, ret = 1; + int pullup, reg, err = -ENOTSUPP, ret = 1; const struct mtk_pin_desc *desc; - if (pin >= hw->soc->npins) { - err = -EINVAL; - goto out; - } + if (pin >= hw->soc->npins) + return -EINVAL; + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; switch (param) { case PIN_CONFIG_BIAS_DISABLE: case PIN_CONFIG_BIAS_PULL_UP: case PIN_CONFIG_BIAS_PULL_DOWN: - if (hw->soc->bias_get_combo) { - err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); - if (err) - goto out; - if (param == PIN_CONFIG_BIAS_DISABLE) { - if (ret == MTK_PUPD_SET_R1R0_00) - ret = MTK_DISABLE; - } else if (param == PIN_CONFIG_BIAS_PULL_UP) { - /* When desire to get pull-up value, return - * error if current setting is pull-down - */ - if (!pullup) - err = -EINVAL; - } else if (param == PIN_CONFIG_BIAS_PULL_DOWN) { - /* When desire to get pull-down value, return - * error if current setting is pull-up - */ - if (pullup) - err = -EINVAL; - } - } else { - err = -ENOTSUPP; + if (!hw->soc->bias_get_combo) + break; + err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); + if (err) + break; + if (ret == MTK_PUPD_SET_R1R0_00) + ret = MTK_DISABLE; + if (param == PIN_CONFIG_BIAS_DISABLE) { + if (ret != MTK_DISABLE) + err = -EINVAL; + } else if (param == PIN_CONFIG_BIAS_PULL_UP) { + if (!pullup || ret == MTK_DISABLE) + err = -EINVAL; + } else if (param == PIN_CONFIG_BIAS_PULL_DOWN) { + if (pullup || ret == MTK_DISABLE) + err = -EINVAL; } break; case PIN_CONFIG_SLEW_RATE: @@ -123,7 +163,7 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_OUTPUT_ENABLE: err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret); if (err) - goto out; + break; /* CONFIG Current direction return value * ------------- ----------------- ---------------------- * OUTPUT_ENABLE output 1 (= HW value) @@ -138,23 +178,48 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_INPUT_SCHMITT_ENABLE: err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret); if (err) - goto out; + break; /* return error when in output mode * because schmitt trigger only work in input mode */ if (ret) { err = -EINVAL; - goto out; + break; } err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &ret); - break; case PIN_CONFIG_DRIVE_STRENGTH: - if (hw->soc->drive_get) - err = hw->soc->drive_get(hw, desc, &ret); - else - err = -ENOTSUPP; + if (!hw->soc->drive_get) + break; + + if (hw->soc->adv_drive_get) { + err = hw->soc->adv_drive_get(hw, desc, &ret); + if (!err) { + err = mtk_drv_adv_to_uA(ret); + if (err > 0) { + /* PIN_CONFIG_DRIVE_STRENGTH_UA used */ + err = -EINVAL; + break; + } + } + } + + err = hw->soc->drive_get(hw, desc, &ret); + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + if (!hw->soc->adv_drive_get) + break; + + err = hw->soc->adv_drive_get(hw, desc, &ret); + if (err) + break; + err = mtk_drv_adv_to_uA(ret); + if (err < 0) + break; + + ret = err; + err = 0; break; case MTK_PIN_CONFIG_TDSEL: case MTK_PIN_CONFIG_RDSEL: @@ -164,23 +229,18 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, break; case MTK_PIN_CONFIG_PU_ADV: case MTK_PIN_CONFIG_PD_ADV: - if (hw->soc->adv_pull_get) { - pullup = param == MTK_PIN_CONFIG_PU_ADV; - err = hw->soc->adv_pull_get(hw, desc, pullup, &ret); - } else - err = -ENOTSUPP; + if (!hw->soc->adv_pull_get) + break; + pullup = param == MTK_PIN_CONFIG_PU_ADV; + err = hw->soc->adv_pull_get(hw, desc, pullup, &ret); break; case MTK_PIN_CONFIG_DRV_ADV: - if (hw->soc->adv_drive_get) - err = hw->soc->adv_drive_get(hw, desc, &ret); - else - err = -ENOTSUPP; + if (!hw->soc->adv_drive_get) + break; + err = hw->soc->adv_drive_get(hw, desc, &ret); break; - default: - err = -ENOTSUPP; } -out: if (!err) *config = pinconf_to_config_packed(param, ret); @@ -188,38 +248,33 @@ out: } static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, - enum pin_config_param param, - enum pin_config_param arg) + enum pin_config_param param, u32 arg) { struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); const struct mtk_pin_desc *desc; - int err = 0; + int err = -ENOTSUPP; u32 reg; - if (pin >= hw->soc->npins) { - err = -EINVAL; - goto err; - } + if (pin >= hw->soc->npins) + return -EINVAL; + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; switch ((u32)param) { case PIN_CONFIG_BIAS_DISABLE: - if (hw->soc->bias_set_combo) - err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE); - else - err = -ENOTSUPP; + if (!hw->soc->bias_set_combo) + break; + err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE); break; case PIN_CONFIG_BIAS_PULL_UP: - if (hw->soc->bias_set_combo) - err = hw->soc->bias_set_combo(hw, desc, 1, arg); - else - err = -ENOTSUPP; + if (!hw->soc->bias_set_combo) + break; + err = hw->soc->bias_set_combo(hw, desc, 1, arg); break; case PIN_CONFIG_BIAS_PULL_DOWN: - if (hw->soc->bias_set_combo) - err = hw->soc->bias_set_combo(hw, desc, 0, arg); - else - err = -ENOTSUPP; + if (!hw->soc->bias_set_combo) + break; + err = hw->soc->bias_set_combo(hw, desc, 0, arg); break; case PIN_CONFIG_OUTPUT_ENABLE: err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, @@ -228,7 +283,7 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, * does not have SMT control */ if (err != -ENOTSUPP) - goto err; + break; err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_OUTPUT); @@ -237,7 +292,7 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, /* regard all non-zero value as enable */ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, !!arg); if (err) - goto err; + break; err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT); @@ -250,7 +305,7 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, arg); if (err) - goto err; + break; err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_OUTPUT); @@ -262,15 +317,23 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, */ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !arg); if (err) - goto err; + break; err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, !!arg); break; case PIN_CONFIG_DRIVE_STRENGTH: - if (hw->soc->drive_set) - err = hw->soc->drive_set(hw, desc, arg); - else - err = -ENOTSUPP; + if (!hw->soc->drive_set) + break; + err = hw->soc->drive_set(hw, desc, arg); + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + if (!hw->soc->adv_drive_set) + break; + + err = mtk_drv_uA_to_adv(arg); + if (err < 0) + break; + err = hw->soc->adv_drive_set(hw, desc, err); break; case MTK_PIN_CONFIG_TDSEL: case MTK_PIN_CONFIG_RDSEL: @@ -280,26 +343,19 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, break; case MTK_PIN_CONFIG_PU_ADV: case MTK_PIN_CONFIG_PD_ADV: - if (hw->soc->adv_pull_set) { - bool pullup; - - pullup = param == MTK_PIN_CONFIG_PU_ADV; - err = hw->soc->adv_pull_set(hw, desc, pullup, - arg); - } else - err = -ENOTSUPP; + if (!hw->soc->adv_pull_set) + break; + err = hw->soc->adv_pull_set(hw, desc, + (param == MTK_PIN_CONFIG_PU_ADV), + arg); break; case MTK_PIN_CONFIG_DRV_ADV: - if (hw->soc->adv_drive_set) - err = hw->soc->adv_drive_set(hw, desc, arg); - else - err = -ENOTSUPP; + if (!hw->soc->adv_drive_set) + break; + err = hw->soc->adv_drive_set(hw, desc, arg); break; - default: - err = -ENOTSUPP; } -err: return err; } @@ -586,6 +642,9 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, if (gpio >= hw->soc->npins) return -EINVAL; + if (mtk_is_virt_gpio(hw, gpio)) + return -EINVAL; + desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; pinmux = mtk_pctrl_get_pinmux(hw, gpio); if (pinmux >= hw->soc->nfuncs) @@ -639,14 +698,10 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, pullen, pullup); - if (r1 != -1) { - len += scnprintf(buf + len, buf_len - len, " (%1d %1d)\n", - r1, r0); - } else if (rsel != -1) { - len += scnprintf(buf + len, buf_len - len, " (%1d)\n", rsel); - } else { - len += scnprintf(buf + len, buf_len - len, "\n"); - } + if (r1 != -1) + len += scnprintf(buf + len, buf_len - len, " (%1d %1d)", r1, r0); + else if (rsel != -1) + len += scnprintf(buf + len, buf_len - len, " (%1d)", rsel); return len; } @@ -737,10 +792,10 @@ static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group, unsigned long *config) { struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); + struct mtk_pinctrl_group *grp = &hw->groups[group]; - *config = hw->groups[group].config; - - return 0; + /* One pin per group only */ + return mtk_pinconf_get(pctldev, grp->pin, config); } static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, @@ -748,6 +803,8 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, { struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); struct mtk_pinctrl_group *grp = &hw->groups[group]; + bool drive_strength_uA_found = false; + bool adv_drve_strength_found = false; int i, ret; for (i = 0; i < num_configs; i++) { @@ -757,9 +814,21 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, if (ret < 0) return ret; - grp->config = configs[i]; + if (pinconf_to_config_param(configs[i]) == PIN_CONFIG_DRIVE_STRENGTH_UA) + drive_strength_uA_found = true; + if (pinconf_to_config_param(configs[i]) == MTK_PIN_CONFIG_DRV_ADV) + adv_drve_strength_found = true; } + /* + * Disable advanced drive strength mode if drive-strength-microamp + * is not set. However, mediatek,drive-strength-adv takes precedence + * as its value can explicitly request the mode be enabled or not. + */ + if (hw->soc->adv_drive_set && !drive_strength_uA_found && + !adv_drve_strength_found) + hw->soc->adv_drive_set(hw, &hw->soc->pins[grp->pin], 0); + return 0; } @@ -952,9 +1021,9 @@ static int mtk_pctrl_build_state(struct platform_device *pdev) return 0; } -int mtk_paris_pinctrl_probe(struct platform_device *pdev, - const struct mtk_pin_soc *soc) +int mtk_paris_pinctrl_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct pinctrl_pin_desc *pins; struct mtk_pinctrl *hw; int err, i; @@ -964,14 +1033,16 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, return -ENOMEM; platform_set_drvdata(pdev, hw); - hw->soc = soc; + + hw->soc = device_get_match_data(dev); + if (!hw->soc) + return -ENOENT; + hw->dev = &pdev->dev; - if (!hw->soc->nbase_names) { - dev_err(&pdev->dev, + if (!hw->soc->nbase_names) + return dev_err_probe(dev, -EINVAL, "SoC should be assigned at least one register base\n"); - return -EINVAL; - } hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names, sizeof(*hw->base), GFP_KERNEL); @@ -988,7 +1059,7 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, hw->nbase = hw->soc->nbase_names; if (of_find_property(hw->dev->of_node, - "mediatek,rsel_resistance_in_si_unit", NULL)) + "mediatek,rsel-resistance-in-si-unit", NULL)) hw->rsel_si_unit = true; else hw->rsel_si_unit = false; @@ -996,10 +1067,8 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, spin_lock_init(&hw->lock); err = mtk_pctrl_build_state(pdev); - if (err) { - dev_err(&pdev->dev, "build state failed: %d\n", err); - return -EINVAL; - } + if (err) + return dev_err_probe(dev, err, "build state failed\n"); /* Copy from internal struct mtk_pin_desc to register to the core */ pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins), @@ -1037,10 +1106,8 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, /* Build gpiochip should be after pinctrl_enable is done */ err = mtk_build_gpiochip(hw); - if (err) { - dev_err(&pdev->dev, "Failed to add gpio_chip\n"); - return err; - } + if (err) + return dev_err_probe(dev, err, "Failed to add gpio_chip\n"); platform_set_drvdata(pdev, hw); diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.h b/drivers/pinctrl/mediatek/pinctrl-paris.h index afb7650fd25b..8762ac599329 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.h +++ b/drivers/pinctrl/mediatek/pinctrl-paris.h @@ -57,8 +57,7 @@ id##_funcs, \ } -int mtk_paris_pinctrl_probe(struct platform_device *pdev, - const struct mtk_pin_soc *soc); +int mtk_paris_pinctrl_probe(struct platform_device *pdev); ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, unsigned int gpio, char *buf, unsigned int bufLen); diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig index b2855e341a75..d1955c65b4b6 100644 --- a/drivers/pinctrl/meson/Kconfig +++ b/drivers/pinctrl/meson/Kconfig @@ -61,4 +61,10 @@ config PINCTRL_MESON_A1 select PINCTRL_MESON_AXG_PMX default y +config PINCTRL_MESON_S4 + tristate "Meson s4 Soc pinctrl driver" + depends on ARM64 + select PINCTRL_MESON_AXG_PMX + default y + endif diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile index 1a5bffe953f9..694f0596bfbc 100644 --- a/drivers/pinctrl/meson/Makefile +++ b/drivers/pinctrl/meson/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o +obj-$(CONFIG_PINCTRL_MESON_S4) += pinctrl-meson-s4.o diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c index cd9656b13836..d182a575981e 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c @@ -283,6 +283,8 @@ static const unsigned int pwm_d_x6_pins[] = { GPIOX_6 }; static const unsigned int pwm_e_pins[] = { GPIOX_16 }; /* pwm_f */ +static const unsigned int pwm_f_z_pins[] = { GPIOZ_12 }; +static const unsigned int pwm_f_a_pins[] = { GPIOA_11 }; static const unsigned int pwm_f_x_pins[] = { GPIOX_7 }; static const unsigned int pwm_f_h_pins[] = { GPIOH_5 }; @@ -618,6 +620,7 @@ static struct meson_pmx_group meson_g12a_periphs_groups[] = { GROUP(tdm_c_dout2_z, 4), GROUP(tdm_c_dout3_z, 4), GROUP(mclk1_z, 4), + GROUP(pwm_f_z, 5), /* bank GPIOX */ GROUP(sdio_d0, 1), @@ -768,6 +771,7 @@ static struct meson_pmx_group meson_g12a_periphs_groups[] = { GROUP(tdm_c_dout3_a, 2), GROUP(mclk0_a, 1), GROUP(mclk1_a, 2), + GROUP(pwm_f_a, 3), }; /* uart_ao_a */ @@ -1069,7 +1073,7 @@ static const char * const pwm_e_groups[] = { }; static const char * const pwm_f_groups[] = { - "pwm_f_x", "pwm_f_h", + "pwm_f_z", "pwm_f_a", "pwm_f_x", "pwm_f_h", }; static const char * const cec_ao_a_h_groups[] = { diff --git a/drivers/pinctrl/meson/pinctrl-meson-s4.c b/drivers/pinctrl/meson/pinctrl-meson-s4.c new file mode 100644 index 000000000000..3c7358f53302 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-s4.c @@ -0,0 +1,1232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Pin controller and GPIO driver for Amlogic Meson S4 SoC. + * + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + * Author: Qianggui Song <qianggui.song@amlogic.com> + */ + +#include <dt-bindings/gpio/meson-s4-gpio.h> +#include "pinctrl-meson.h" +#include "pinctrl-meson-axg-pmx.h" + +static const struct pinctrl_pin_desc meson_s4_periphs_pins[] = { + MESON_PIN(GPIOE_0), + MESON_PIN(GPIOE_1), + + MESON_PIN(GPIOB_0), + MESON_PIN(GPIOB_1), + MESON_PIN(GPIOB_2), + MESON_PIN(GPIOB_3), + MESON_PIN(GPIOB_4), + MESON_PIN(GPIOB_5), + MESON_PIN(GPIOB_6), + MESON_PIN(GPIOB_7), + MESON_PIN(GPIOB_8), + MESON_PIN(GPIOB_9), + MESON_PIN(GPIOB_10), + MESON_PIN(GPIOB_11), + MESON_PIN(GPIOB_12), + MESON_PIN(GPIOB_13), + + MESON_PIN(GPIOC_0), + MESON_PIN(GPIOC_1), + MESON_PIN(GPIOC_2), + MESON_PIN(GPIOC_3), + MESON_PIN(GPIOC_4), + MESON_PIN(GPIOC_5), + MESON_PIN(GPIOC_6), + MESON_PIN(GPIOC_7), + + MESON_PIN(GPIOD_0), + MESON_PIN(GPIOD_1), + MESON_PIN(GPIOD_2), + MESON_PIN(GPIOD_3), + MESON_PIN(GPIOD_4), + MESON_PIN(GPIOD_5), + MESON_PIN(GPIOD_6), + MESON_PIN(GPIOD_7), + MESON_PIN(GPIOD_8), + MESON_PIN(GPIOD_9), + MESON_PIN(GPIOD_10), + MESON_PIN(GPIOD_11), + + MESON_PIN(GPIOH_0), + MESON_PIN(GPIOH_1), + MESON_PIN(GPIOH_2), + MESON_PIN(GPIOH_3), + MESON_PIN(GPIOH_4), + MESON_PIN(GPIOH_5), + MESON_PIN(GPIOH_6), + MESON_PIN(GPIOH_7), + MESON_PIN(GPIOH_8), + MESON_PIN(GPIOH_9), + MESON_PIN(GPIOH_10), + MESON_PIN(GPIOH_11), + + MESON_PIN(GPIOX_0), + MESON_PIN(GPIOX_1), + MESON_PIN(GPIOX_2), + MESON_PIN(GPIOX_3), + MESON_PIN(GPIOX_4), + MESON_PIN(GPIOX_5), + MESON_PIN(GPIOX_6), + MESON_PIN(GPIOX_7), + MESON_PIN(GPIOX_8), + MESON_PIN(GPIOX_9), + MESON_PIN(GPIOX_10), + MESON_PIN(GPIOX_11), + MESON_PIN(GPIOX_12), + MESON_PIN(GPIOX_13), + MESON_PIN(GPIOX_14), + MESON_PIN(GPIOX_15), + MESON_PIN(GPIOX_16), + MESON_PIN(GPIOX_17), + MESON_PIN(GPIOX_18), + MESON_PIN(GPIOX_19), + + MESON_PIN(GPIOZ_0), + MESON_PIN(GPIOZ_1), + MESON_PIN(GPIOZ_2), + MESON_PIN(GPIOZ_3), + MESON_PIN(GPIOZ_4), + MESON_PIN(GPIOZ_5), + MESON_PIN(GPIOZ_6), + MESON_PIN(GPIOZ_7), + MESON_PIN(GPIOZ_8), + MESON_PIN(GPIOZ_9), + MESON_PIN(GPIOZ_10), + MESON_PIN(GPIOZ_11), + MESON_PIN(GPIOZ_12), + + MESON_PIN(GPIO_TEST_N), +}; + +/* BANK E func1 */ +static const unsigned int i2c0_sda_pins[] = { GPIOE_0 }; +static const unsigned int i2c0_scl_pins[] = { GPIOE_1 }; + +/* BANK E func2 */ +static const unsigned int uart_b_tx_e_pins[] = { GPIOE_0 }; +static const unsigned int uart_b_rx_e_pins[] = { GPIOE_1 }; + +/* BANK E func3 */ +static const unsigned int pwm_h_pins[] = { GPIOE_0 }; +static const unsigned int pwm_j_pins[] = { GPIOE_1 }; + +/* BANK B func1 */ +static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 }; +static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 }; +static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 }; +static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 }; +static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 }; +static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 }; +static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 }; +static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 }; +static const unsigned int emmc_clk_pins[] = { GPIOB_8 }; +static const unsigned int emmc_rst_pins[] = { GPIOB_9 }; +static const unsigned int emmc_cmd_pins[] = { GPIOB_10 }; +static const unsigned int emmc_nand_ds_pins[] = { GPIOB_11 }; + +/* Bank B func2 */ +static const unsigned int nand_wen_clk_pins[] = { GPIOB_8 }; +static const unsigned int nand_ale_pins[] = { GPIOB_9 }; +static const unsigned int nand_ren_wr_pins[] = { GPIOB_10 }; +static const unsigned int nand_cle_pins[] = { GPIOB_11 }; +static const unsigned int nand_ce0_pins[] = { GPIOB_12 }; + +/* Bank B func3 */ +static const unsigned int spif_hold_pins[] = { GPIOB_3 }; +static const unsigned int spif_mo_pins[] = { GPIOB_4 }; +static const unsigned int spif_mi_pins[] = { GPIOB_5 }; +static const unsigned int spif_clk_pins[] = { GPIOB_6 }; +static const unsigned int spif_wp_pins[] = { GPIOB_7 }; +static const unsigned int spif_cs_pins[] = { GPIOB_13 }; + +/* Bank C func1 */ +static const unsigned int sdcard_d0_c_pins[] = { GPIOC_0 }; +static const unsigned int sdcard_d1_c_pins[] = { GPIOC_1 }; +static const unsigned int sdcard_d2_c_pins[] = { GPIOC_2 }; +static const unsigned int sdcard_d3_c_pins[] = { GPIOC_3 }; +static const unsigned int sdcard_clk_c_pins[] = { GPIOC_4 }; +static const unsigned int sdcard_cmd_c_pins[] = { GPIOC_5 }; +static const unsigned int sdcard_cd_pins[] = { GPIOC_6 }; + +/* Bank C func2 */ +static const unsigned int jtag_2_tdo_pins[] = { GPIOC_0 }; +static const unsigned int jtag_2_tdi_pins[] = { GPIOC_1 }; +static const unsigned int uart_b_rx_c_pins[] = { GPIOC_2 }; +static const unsigned int uart_b_tx_c_pins[] = { GPIOC_3 }; +static const unsigned int jtag_2_clk_pins[] = { GPIOC_4 }; +static const unsigned int jtag_2_tms_pins[] = { GPIOC_5 }; +static const unsigned int i2c1_sda_c_pins[] = { GPIOC_6 }; +static const unsigned int i2c1_scl_c_pins[] = { GPIOC_7 }; + +/* Bank C func3 */ +static const unsigned int pdm_din1_c_pins[] = { GPIOC_0 }; +static const unsigned int pdm_din0_c_pins[] = { GPIOC_1 }; +static const unsigned int i2c4_sda_c_pins[] = { GPIOC_2 }; +static const unsigned int i2c4_scl_c_pins[] = { GPIOC_3 }; +static const unsigned int pdm_dclk_c_pins[] = { GPIOC_4 }; +static const unsigned int iso7816_clk_c_pins[] = { GPIOC_5 }; +static const unsigned int iso7816_data_c_pins[] = { GPIOC_6 }; + +/* Bank C func4 */ +static const unsigned int tdm_d2_c_pins[] = { GPIOC_0 }; +static const unsigned int tdm_d3_c_pins[] = { GPIOC_1 }; +static const unsigned int tdm_fs1_c_pins[] = { GPIOC_2 }; +static const unsigned int tdm_sclk1_c_pins[] = { GPIOC_3 }; +static const unsigned int mclk_1_c_pins[] = { GPIOC_4 }; +static const unsigned int tdm_d4_c_pins[] = { GPIOC_5 }; +static const unsigned int tdm_d5_c_pins[] = { GPIOC_6 }; + +/* Bank D func1 */ +static const unsigned int uart_b_tx_d_pins[] = { GPIOD_0 }; +static const unsigned int uart_b_rx_d_pins[] = { GPIOD_1 }; +static const unsigned int uart_b_cts_d_pins[] = { GPIOD_2 }; +static const unsigned int uart_b_rts_d_pins[] = { GPIOD_3 }; +static const unsigned int remote_out_pins[] = { GPIOD_4 }; +static const unsigned int remote_in_pins[] = { GPIOD_5 }; +static const unsigned int jtag_1_clk_pins[] = { GPIOD_6 }; +static const unsigned int jtag_1_tms_pins[] = { GPIOD_7 }; +static const unsigned int jtag_1_tdi_pins[] = { GPIOD_8 }; +static const unsigned int jtag_1_tdo_pins[] = { GPIOD_9 }; +static const unsigned int clk12_24_pins[] = { GPIOD_10 }; +static const unsigned int pwm_g_hiz_pins[] = { GPIOD_11 }; + +/* Bank D func2 */ +static const unsigned int i2c4_sda_d_pins[] = { GPIOD_2 }; +static const unsigned int i2c4_scl_d_pins[] = { GPIOD_3 }; +static const unsigned int mclk_1_d_pins[] = { GPIOD_4 }; +static const unsigned int tdm_sclk1_d_pins[] = { GPIOD_6 }; +static const unsigned int tdm_fs1_d_pins[] = { GPIOD_7 }; +static const unsigned int tdm_d4_d_pins[] = { GPIOD_8 }; +static const unsigned int tdm_d3_d_pins[] = { GPIOD_9 }; +static const unsigned int tdm_d2_d_pins[] = { GPIOD_10 }; +static const unsigned int pwm_g_d_pins[] = { GPIOD_11 }; + +/* Bank D func3 */ +static const unsigned int uart_c_tx_pins[] = { GPIOD_2 }; +static const unsigned int uart_c_rx_pins[] = { GPIOD_3 }; +static const unsigned int pwm_b_d_pins[] = { GPIOD_4 }; +static const unsigned int pwm_a_d_pins[] = { GPIOD_6 }; +static const unsigned int pwm_c_d_pins[] = { GPIOD_7 }; +static const unsigned int pwm_d_d_pins[] = { GPIOD_8 }; +static const unsigned int pwm_i_d_pins[] = { GPIOD_9 }; + +/* Bank D func4 */ +static const unsigned int clk_32k_in_pins[] = { GPIOD_2 }; +static const unsigned int pwm_b_hiz_pins[] = { GPIOD_4 }; +static const unsigned int pwm_a_hiz_pins[] = { GPIOD_6 }; +static const unsigned int pwm_c_hiz_pins[] = { GPIOD_7 }; +static const unsigned int pdm_dclk_d_pins[] = { GPIOD_8 }; +static const unsigned int pdm_din0_d_pins[] = { GPIOD_9 }; +static const unsigned int pdm_din1_d_pins[] = { GPIOD_10 }; + +/* Bank D func5 */ +static const unsigned int mic_mute_en_pins[] = { GPIOD_2 }; +static const unsigned int mic_mute_key_pins[] = { GPIOD_3 }; +static const unsigned int i2c1_sda_d_pins[] = { GPIOD_6 }; +static const unsigned int i2c1_scl_d_pins[] = { GPIOD_7 }; +static const unsigned int i2c2_sda_d_pins[] = { GPIOD_10 }; +static const unsigned int i2c2_scl_d_pins[] = { GPIOD_11 }; + +/* Bank D func6 */ +static const unsigned int gen_clk_d_pins[] = { GPIOD_10 }; +static const unsigned int tsin_b_clk_c_pins[] = { GPIOD_6 }; +static const unsigned int tsin_b_sop_c_pins[] = { GPIOD_7 }; +static const unsigned int tsin_b_valid_c_pins[] = { GPIOD_8 }; +static const unsigned int tsin_b_d0_c_pins[] = { GPIOD_9 }; + +/* Bank H func1 */ +static const unsigned int hdmitx_sda_pins[] = { GPIOH_0 }; +static const unsigned int hdmitx_sck_pins[] = { GPIOH_1 }; +static const unsigned int hdmitx_hpd_in_pins[] = { GPIOH_2 }; +static const unsigned int ao_cec_a_pins[] = { GPIOH_3 }; +static const unsigned int spdif_out_h_pins[] = { GPIOH_4 }; +static const unsigned int spdif_in_pins[] = { GPIOH_5 }; +static const unsigned int i2c1_sda_h_pins[] = { GPIOH_6 }; +static const unsigned int i2c1_scl_h_pins[] = { GPIOH_7 }; +static const unsigned int i2c2_sda_h8_pins[] = { GPIOH_8 }; +static const unsigned int i2c2_scl_h9_pins[] = { GPIOH_9 }; +static const unsigned int eth_link_led_pins[] = { GPIOH_10 }; +static const unsigned int eth_act_led_pins[] = { GPIOH_11 }; + +/* Bank H func2 */ +static const unsigned int i2c2_sda_h0_pins[] = { GPIOH_0 }; +static const unsigned int i2c2_scl_h1_pins[] = { GPIOH_1 }; +static const unsigned int ao_cec_b_pins[] = { GPIOH_3 }; +static const unsigned int uart_d_tx_h_pins[] = { GPIOH_4 }; +static const unsigned int uart_d_rx_h_pins[] = { GPIOH_5 }; +static const unsigned int uart_d_cts_h_pins[] = { GPIOH_6 }; +static const unsigned int uart_d_rts_h_pins[] = { GPIOH_7 }; +static const unsigned int iso7816_clk_h_pins[] = { GPIOH_8 }; +static const unsigned int iso7816_data_h_pins[] = { GPIOH_9 }; +static const unsigned int uart_e_tx_h_pins[] = { GPIOH_10 }; +static const unsigned int uart_e_rx_h_pins[] = { GPIOH_11 }; + +/* Bank H func3 */ +static const unsigned int pwm_d_h_pins[] = { GPIOH_6 }; +static const unsigned int pwm_i_h_pins[] = { GPIOH_7 }; +static const unsigned int pdm_dclk_h_pins[] = { GPIOH_8 }; +static const unsigned int pdm_din0_h_pins[] = { GPIOH_9 }; +static const unsigned int pdm_din1_h_pins[] = { GPIOH_10 }; + +/* Bank H func4 */ +static const unsigned int mclk_1_h_pins[] = { GPIOH_4 }; +static const unsigned int tdm_sclk1_h_pins[] = { GPIOH_5 }; +static const unsigned int tdm_fs1_h_pins[] = { GPIOH_6 }; +static const unsigned int tdm_d2_h_pins[] = { GPIOH_7 }; +static const unsigned int tdm_d3_h_pins[] = { GPIOH_8 }; +static const unsigned int tdm_d4_h_pins[] = { GPIOH_9 }; + +/* Bank H func5 */ +static const unsigned int spi_a_miso_h_pins[] = { GPIOH_4 }; +static const unsigned int spi_a_mosi_h_pins[] = { GPIOH_5 }; +static const unsigned int spi_a_clk_h_pins[] = { GPIOH_6 }; +static const unsigned int spi_a_ss0_h_pins[] = { GPIOH_7 }; + +/* Bank H func6 */ +static const unsigned int gen_clk_h_pins[] = { GPIOH_11 }; +static const unsigned int tsin_b1_clk_pins[] = { GPIOH_4 }; +static const unsigned int tsin_b1_sop_pins[] = { GPIOH_5 }; +static const unsigned int tsin_b1_valid_pins[] = { GPIOH_6 }; +static const unsigned int tsin_b1_d0_pins[] = { GPIOH_7 }; + +/* Bank X func1 */ +static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; +static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; +static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; +static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; +static const unsigned int pwm_a_x_pins[] = { GPIOX_6 }; +static const unsigned int pwm_f_x_pins[] = { GPIOX_7 }; +static const unsigned int tdm_d1_pins[] = { GPIOX_8 }; +static const unsigned int tdm_d0_pins[] = { GPIOX_9 }; +static const unsigned int tdm_fs0_pins[] = { GPIOX_10 }; +static const unsigned int tdm_sclk0_pins[] = { GPIOX_11 }; +static const unsigned int uart_a_tx_pins[] = { GPIOX_12 }; +static const unsigned int uart_a_rx_pins[] = { GPIOX_13 }; +static const unsigned int uart_a_cts_pins[] = { GPIOX_14 }; +static const unsigned int uart_a_rts_pins[] = { GPIOX_15 }; +static const unsigned int pwm_e_x_pins[] = { GPIOX_16 }; +static const unsigned int i2c1_sda_x_pins[] = { GPIOX_17 }; +static const unsigned int i2c1_scl_x_pins[] = { GPIOX_18 }; +static const unsigned int pwm_b_x_pins[] = { GPIOX_19 }; + +/* Bank X func2 */ +static const unsigned int pdm_din0_x_pins[] = { GPIOX_8 }; +static const unsigned int pdm_din1_x_pins[] = { GPIOX_9 }; +static const unsigned int pdm_dclk_x_pins[] = { GPIOX_11 }; + +/* Bank X func3 */ +static const unsigned int spi_a_mosi_x_pins[] = { GPIOX_8 }; +static const unsigned int spi_a_miso_x_pins[] = { GPIOX_9 }; +static const unsigned int spi_a_ss0_x_pins[] = { GPIOX_10 }; +static const unsigned int spi_a_clk_x_pins[] = { GPIOX_11 }; + +/* Bank X func4 */ +static const unsigned int pwm_c_x_pins[] = { GPIOX_8 }; +static const unsigned int i2c_slave_scl_pins[] = { GPIOX_10 }; +static const unsigned int i2c_slave_sda_pins[] = { GPIOX_11 }; + +/* Bank X func5 */ +static const unsigned int i2c3_sda_x_pins[] = { GPIOX_10 }; +static const unsigned int i2c3_scl_x_pins[] = { GPIOX_11 }; + +/* Bank Z func1 */ +static const unsigned int tdm_fs2_pins[] = { GPIOZ_0 }; +static const unsigned int tdm_sclk2_pins[] = { GPIOZ_1 }; +static const unsigned int tdm_d4_z_pins[] = { GPIOZ_2 }; +static const unsigned int tdm_d5_z_pins[] = { GPIOZ_3 }; +static const unsigned int tdm_d6_pins[] = { GPIOZ_4 }; +static const unsigned int tdm_d7_pins[] = { GPIOZ_5 }; +static const unsigned int mclk_2_pins[] = { GPIOZ_6 }; +static const unsigned int spdif_out_z_pins[] = { GPIOZ_9 }; +static const unsigned int dtv_a_if_agc_z10_pins[] = { GPIOZ_10 }; +static const unsigned int uart_e_tx_z11_pins[] = { GPIOZ_11 }; +static const unsigned int uart_e_rx_z12_pins[] = { GPIOZ_12 }; + +/* Bank Z func2 */ +static const unsigned int tsin_a_clk_pins[] = { GPIOZ_0 }; +static const unsigned int tsin_a_sop_pins[] = { GPIOZ_1 }; +static const unsigned int tsin_a_valid_pins[] = { GPIOZ_2 }; +static const unsigned int tsin_a_din0_pins[] = { GPIOZ_3 }; +static const unsigned int dtv_a_if_agc_z6_pins[] = { GPIOZ_6 }; +static const unsigned int dtv_b_if_agc_pins[] = { GPIOZ_7 }; +static const unsigned int i2c3_sda_z_pins[] = { GPIOZ_8 }; +static const unsigned int i2c3_scl_z_pins[] = { GPIOZ_9 }; +static const unsigned int dtv_a_rf_agc_pins[] = { GPIOZ_10 }; +static const unsigned int dtv_b_rf_agc_pins[] = { GPIOZ_11 }; + +/* Bank Z func3 */ +static const unsigned int sdcard_d0_z_pins[] = { GPIOZ_0 }; +static const unsigned int sdcard_d1_z_pins[] = { GPIOZ_1 }; +static const unsigned int sdcard_d2_z_pins[] = { GPIOZ_2 }; +static const unsigned int sdcard_d3_z_pins[] = { GPIOZ_3 }; +static const unsigned int sdcard_clk_z_pins[] = { GPIOZ_4 }; +static const unsigned int sdcard_cmd_z_pins[] = { GPIOZ_5 }; +static const unsigned int uart_e_tx_z8_pins[] = { GPIOZ_8 }; +static const unsigned int uart_e_rx_z9_pins[] = { GPIOZ_9 }; +static const unsigned int pdm_din1_z_pins[] = { GPIOZ_10 }; +static const unsigned int pdm_din0_z_pins[] = { GPIOZ_11 }; +static const unsigned int pdm_dclk_z_pins[] = { GPIOZ_12 }; + +/* Bank Z func4 */ +static const unsigned int spi_a_miso_z_pins[] = { GPIOZ_0 }; +static const unsigned int spi_a_mosi_z_pins[] = { GPIOZ_1 }; +static const unsigned int spi_a_clk_z_pins[] = { GPIOZ_2 }; +static const unsigned int spi_a_ss0_z_pins[] = { GPIOZ_3 }; +static const unsigned int spi_a_ss1_z_pins[] = { GPIOZ_4 }; +static const unsigned int spi_a_ss2_z_pins[] = { GPIOZ_5 }; +static const unsigned int i2c4_scl_z_pins[] = { GPIOZ_11 }; +static const unsigned int i2c4_sda_z_pins[] = { GPIOZ_12 }; + +/* Bank Z func5 */ +static const unsigned int uart_d_tx_z_pins[] = { GPIOZ_0 }; +static const unsigned int uart_d_rx_z_pins[] = { GPIOZ_1 }; +static const unsigned int uart_d_cts_z_pins[] = { GPIOZ_2 }; +static const unsigned int uart_d_rts_z_pins[] = { GPIOZ_3 }; +static const unsigned int pwm_g_z_pins[] = { GPIOZ_4 }; +static const unsigned int pwm_f_z_pins[] = { GPIOZ_5 }; +static const unsigned int pwm_e_z_pins[] = { GPIOZ_6 }; +static const unsigned int tsin_b_clk_z_pins[] = { GPIOZ_7 }; +static const unsigned int tsin_b_sop_z_pins[] = { GPIOZ_10 }; +static const unsigned int tsin_b_valid_z_pins[] = { GPIOZ_11 }; +static const unsigned int tsin_b_d0_z_pins[] = { GPIOZ_12 }; + +/* Bank Z func6 */ +static const unsigned int s2_demod_gpio7_pins[] = { GPIOZ_0 }; +static const unsigned int s2_demod_gpio6_pins[] = { GPIOZ_1 }; +static const unsigned int s2_demod_gpio5_pins[] = { GPIOZ_2 }; +static const unsigned int s2_demod_gpio4_pins[] = { GPIOZ_3 }; +static const unsigned int s2_demod_gpio3_pins[] = { GPIOZ_4 }; +static const unsigned int s2_demod_gpio2_pins[] = { GPIOZ_5 }; +static const unsigned int diseqc_out_pins[] = { GPIOZ_7 }; +static const unsigned int s2_demod_gpio1_pins[] = { GPIOZ_8 }; +static const unsigned int s2_demod_gpio0_pins[] = { GPIOZ_12 }; + +/* Bank Z func7 */ +static const unsigned int gen_clk_z9_pins[] = { GPIOZ_9 }; +static const unsigned int gen_clk_z12_pins[] = { GPIOZ_12 }; + +static struct meson_pmx_group meson_s4_periphs_groups[] = { + GPIO_GROUP(GPIOE_0), + GPIO_GROUP(GPIOE_1), + + GPIO_GROUP(GPIOB_0), + GPIO_GROUP(GPIOB_1), + GPIO_GROUP(GPIOB_2), + GPIO_GROUP(GPIOB_3), + GPIO_GROUP(GPIOB_4), + GPIO_GROUP(GPIOB_5), + GPIO_GROUP(GPIOB_6), + GPIO_GROUP(GPIOB_7), + GPIO_GROUP(GPIOB_8), + GPIO_GROUP(GPIOB_9), + GPIO_GROUP(GPIOB_10), + GPIO_GROUP(GPIOB_11), + GPIO_GROUP(GPIOB_12), + GPIO_GROUP(GPIOB_13), + + GPIO_GROUP(GPIOC_0), + GPIO_GROUP(GPIOC_1), + GPIO_GROUP(GPIOC_2), + GPIO_GROUP(GPIOC_3), + GPIO_GROUP(GPIOC_4), + GPIO_GROUP(GPIOC_5), + GPIO_GROUP(GPIOC_6), + GPIO_GROUP(GPIOC_7), + + GPIO_GROUP(GPIOD_0), + GPIO_GROUP(GPIOD_1), + GPIO_GROUP(GPIOD_2), + GPIO_GROUP(GPIOD_3), + GPIO_GROUP(GPIOD_4), + GPIO_GROUP(GPIOD_5), + GPIO_GROUP(GPIOD_6), + GPIO_GROUP(GPIOD_7), + GPIO_GROUP(GPIOD_8), + GPIO_GROUP(GPIOD_9), + GPIO_GROUP(GPIOD_10), + GPIO_GROUP(GPIOD_11), + + GPIO_GROUP(GPIOH_0), + GPIO_GROUP(GPIOH_1), + GPIO_GROUP(GPIOH_2), + GPIO_GROUP(GPIOH_3), + GPIO_GROUP(GPIOH_4), + GPIO_GROUP(GPIOH_5), + GPIO_GROUP(GPIOH_6), + GPIO_GROUP(GPIOH_7), + GPIO_GROUP(GPIOH_8), + GPIO_GROUP(GPIOH_9), + GPIO_GROUP(GPIOH_10), + GPIO_GROUP(GPIOH_11), + + GPIO_GROUP(GPIOX_0), + GPIO_GROUP(GPIOX_1), + GPIO_GROUP(GPIOX_2), + GPIO_GROUP(GPIOX_3), + GPIO_GROUP(GPIOX_4), + GPIO_GROUP(GPIOX_5), + GPIO_GROUP(GPIOX_6), + GPIO_GROUP(GPIOX_7), + GPIO_GROUP(GPIOX_8), + GPIO_GROUP(GPIOX_9), + GPIO_GROUP(GPIOX_10), + GPIO_GROUP(GPIOX_11), + GPIO_GROUP(GPIOX_12), + GPIO_GROUP(GPIOX_13), + GPIO_GROUP(GPIOX_14), + GPIO_GROUP(GPIOX_15), + GPIO_GROUP(GPIOX_16), + GPIO_GROUP(GPIOX_17), + GPIO_GROUP(GPIOX_18), + GPIO_GROUP(GPIOX_19), + + GPIO_GROUP(GPIOZ_0), + GPIO_GROUP(GPIOZ_1), + GPIO_GROUP(GPIOZ_2), + GPIO_GROUP(GPIOZ_3), + GPIO_GROUP(GPIOZ_4), + GPIO_GROUP(GPIOZ_5), + GPIO_GROUP(GPIOZ_6), + GPIO_GROUP(GPIOZ_7), + GPIO_GROUP(GPIOZ_8), + GPIO_GROUP(GPIOZ_9), + GPIO_GROUP(GPIOZ_10), + GPIO_GROUP(GPIOZ_11), + GPIO_GROUP(GPIOZ_12), + + GPIO_GROUP(GPIO_TEST_N), + + /* BANK E func1 */ + GROUP(i2c0_sda, 1), + GROUP(i2c0_scl, 1), + + /* BANK E func2 */ + GROUP(uart_b_tx_e, 2), + GROUP(uart_b_rx_e, 2), + + /* BANK E func3 */ + GROUP(pwm_h, 3), + GROUP(pwm_j, 3), + + /* BANK B func1 */ + GROUP(emmc_nand_d0, 1), + GROUP(emmc_nand_d1, 1), + GROUP(emmc_nand_d2, 1), + GROUP(emmc_nand_d3, 1), + GROUP(emmc_nand_d4, 1), + GROUP(emmc_nand_d5, 1), + GROUP(emmc_nand_d6, 1), + GROUP(emmc_nand_d7, 1), + GROUP(emmc_clk, 1), + GROUP(emmc_rst, 1), + GROUP(emmc_cmd, 1), + GROUP(emmc_nand_ds, 1), + + /* Bank B func2 */ + GROUP(nand_wen_clk, 2), + GROUP(nand_ale, 2), + GROUP(nand_ren_wr, 2), + GROUP(nand_cle, 2), + GROUP(nand_ce0, 2), + + /* Bank B func3 */ + GROUP(spif_hold, 3), + GROUP(spif_mo, 3), + GROUP(spif_mi, 3), + GROUP(spif_clk, 3), + GROUP(spif_wp, 3), + GROUP(spif_cs, 3), + + /* Bank C func1 */ + GROUP(sdcard_d0_c, 1), + GROUP(sdcard_d1_c, 1), + GROUP(sdcard_d2_c, 1), + GROUP(sdcard_d3_c, 1), + GROUP(sdcard_clk_c, 1), + GROUP(sdcard_cmd_c, 1), + GROUP(sdcard_cd, 1), + + /* Bank C func2 */ + GROUP(jtag_2_tdo, 2), + GROUP(jtag_2_tdi, 2), + GROUP(uart_b_rx_c, 2), + GROUP(uart_b_tx_c, 2), + GROUP(jtag_2_clk, 2), + GROUP(jtag_2_tms, 2), + GROUP(i2c1_sda_c, 2), + GROUP(i2c1_scl_c, 2), + + /* Bank C func3 */ + GROUP(pdm_din1_c, 3), + GROUP(pdm_din0_c, 3), + GROUP(i2c4_sda_c, 3), + GROUP(i2c4_scl_c, 3), + GROUP(pdm_dclk_c, 3), + GROUP(iso7816_clk_c, 3), + GROUP(iso7816_data_c, 3), + + /* Bank C func4 */ + GROUP(tdm_d2_c, 4), + GROUP(tdm_d3_c, 4), + GROUP(tdm_fs1_c, 4), + GROUP(mclk_1_c, 4), + GROUP(tdm_d4_c, 4), + GROUP(tdm_d5_c, 4), + + /* Bank D func1 */ + GROUP(uart_b_tx_d, 1), + GROUP(uart_b_rx_d, 1), + GROUP(uart_b_cts_d, 1), + GROUP(uart_b_rts_d, 1), + GROUP(remote_out, 1), + GROUP(remote_in, 1), + GROUP(jtag_1_clk, 1), + GROUP(jtag_1_tms, 1), + GROUP(jtag_1_tdi, 1), + GROUP(jtag_1_tdo, 1), + GROUP(clk12_24, 1), + GROUP(pwm_g_hiz, 1), + + /* Bank D func2 */ + GROUP(i2c4_sda_d, 2), + GROUP(i2c4_scl_d, 2), + GROUP(mclk_1_d, 2), + GROUP(tdm_sclk1_d, 2), + GROUP(tdm_fs1_d, 2), + GROUP(tdm_d4_d, 2), + GROUP(tdm_d3_d, 2), + GROUP(tdm_d2_d, 2), + GROUP(pwm_g_d, 2), + + /* Bank D func3 */ + GROUP(uart_c_tx, 3), + GROUP(uart_c_rx, 3), + GROUP(pwm_b_d, 3), + GROUP(pwm_a_d, 3), + GROUP(pwm_c_d, 3), + GROUP(pwm_d_d, 3), + GROUP(pwm_i_d, 3), + + /* Bank D func4 */ + GROUP(clk_32k_in, 4), + GROUP(pwm_b_hiz, 4), + GROUP(pwm_a_hiz, 4), + GROUP(pwm_c_hiz, 4), + GROUP(pdm_dclk_d, 4), + GROUP(pdm_din0_d, 4), + GROUP(pdm_din1_d, 4), + + /* Bank D func5 */ + GROUP(mic_mute_en, 5), + GROUP(mic_mute_key, 5), + GROUP(i2c1_sda_d, 5), + GROUP(i2c1_scl_d, 5), + GROUP(i2c2_sda_d, 5), + GROUP(i2c2_scl_d, 5), + + /* Bank D func6 */ + GROUP(gen_clk_d, 6), + GROUP(tsin_b_clk_c, 6), + GROUP(tsin_b_sop_c, 6), + GROUP(tsin_b_valid_c, 6), + GROUP(tsin_b_d0_c, 6), + + /* Bank H func1 */ + GROUP(hdmitx_sda, 1), + GROUP(hdmitx_sck, 1), + GROUP(hdmitx_hpd_in, 1), + GROUP(ao_cec_a, 1), + GROUP(spdif_out_h, 1), + GROUP(spdif_in, 1), + GROUP(i2c1_sda_h, 1), + GROUP(i2c1_scl_h, 1), + GROUP(i2c2_sda_h8, 1), + GROUP(i2c2_scl_h9, 1), + GROUP(eth_link_led, 1), + GROUP(eth_act_led, 1), + + /* Bank H func2 */ + GROUP(i2c2_sda_h0, 2), + GROUP(i2c2_scl_h1, 2), + GROUP(ao_cec_b, 2), + GROUP(uart_d_tx_h, 2), + GROUP(uart_d_rx_h, 2), + GROUP(uart_d_cts_h, 2), + GROUP(uart_d_rts_h, 2), + GROUP(iso7816_clk_h, 2), + GROUP(iso7816_data_h, 2), + GROUP(uart_e_tx_h, 2), + GROUP(uart_e_rx_h, 2), + + /* Bank H func3 */ + GROUP(pwm_d_h, 3), + GROUP(pwm_i_h, 3), + GROUP(pdm_dclk_h, 3), + GROUP(pdm_din0_h, 3), + GROUP(pdm_din1_h, 3), + + /* Bank H func4 */ + GROUP(mclk_1_h, 4), + GROUP(tdm_sclk1_h, 4), + GROUP(tdm_fs1_h, 4), + GROUP(tdm_d2_h, 4), + GROUP(tdm_d3_h, 4), + GROUP(tdm_d4_h, 4), + + /* Bank H func5 */ + GROUP(spi_a_miso_h, 5), + GROUP(spi_a_mosi_h, 5), + GROUP(spi_a_clk_h, 5), + GROUP(spi_a_ss0_h, 5), + + /* Bank H func6 */ + GROUP(gen_clk_h, 6), + GROUP(tsin_b1_clk, 6), + GROUP(tsin_b1_sop, 6), + GROUP(tsin_b1_valid, 6), + GROUP(tsin_b1_d0, 6), + + /* Bank X func1 */ + GROUP(sdio_d0, 1), + GROUP(sdio_d1, 1), + GROUP(sdio_d2, 1), + GROUP(sdio_d3, 1), + GROUP(sdio_clk, 1), + GROUP(sdio_cmd, 1), + GROUP(pwm_a_x, 1), + GROUP(pwm_f_x, 1), + GROUP(tdm_d1, 1), + GROUP(tdm_d0, 1), + GROUP(tdm_fs0, 1), + GROUP(tdm_sclk0, 1), + GROUP(uart_a_tx, 1), + GROUP(uart_a_rx, 1), + GROUP(uart_a_cts, 1), + GROUP(uart_a_rts, 1), + GROUP(pwm_e_x, 1), + GROUP(i2c1_sda_x, 1), + GROUP(i2c1_scl_x, 1), + GROUP(pwm_b_x, 1), + + /* Bank X func2 */ + GROUP(pdm_din0_x, 2), + GROUP(pdm_din1_x, 2), + GROUP(pdm_dclk_x, 2), + + /* Bank X func3 */ + GROUP(spi_a_mosi_x, 3), + GROUP(spi_a_miso_x, 3), + GROUP(spi_a_ss0_x, 3), + GROUP(spi_a_clk_x, 3), + + /* Bank X func4 */ + GROUP(pwm_c_x, 4), + GROUP(i2c_slave_scl, 4), + GROUP(i2c_slave_sda, 4), + + /* Bank X func5 */ + GROUP(i2c3_sda_x, 5), + GROUP(i2c3_scl_x, 5), + + /* Bank Z func1 */ + GROUP(tdm_fs2, 1), + GROUP(tdm_sclk2, 1), + GROUP(tdm_d4_z, 1), + GROUP(tdm_d5_z, 1), + GROUP(tdm_d6, 1), + GROUP(tdm_d7, 1), + GROUP(mclk_2, 1), + GROUP(spdif_out_z, 1), + GROUP(dtv_a_if_agc_z10, 1), + GROUP(uart_e_tx_z11, 1), + GROUP(uart_e_rx_z12, 1), + + /* Bank Z func2 */ + GROUP(tsin_a_clk, 2), + GROUP(tsin_a_sop, 2), + GROUP(tsin_a_valid, 2), + GROUP(tsin_a_din0, 2), + GROUP(dtv_a_if_agc_z6, 2), + GROUP(dtv_b_if_agc, 2), + GROUP(i2c3_sda_z, 2), + GROUP(i2c3_scl_z, 2), + GROUP(dtv_a_rf_agc, 2), + GROUP(dtv_b_rf_agc, 2), + + /* Bank Z func3 */ + GROUP(sdcard_d0_z, 3), + GROUP(sdcard_d1_z, 3), + GROUP(sdcard_d2_z, 3), + GROUP(sdcard_d3_z, 3), + GROUP(sdcard_clk_z, 3), + GROUP(sdcard_cmd_z, 3), + GROUP(uart_e_tx_z8, 3), + GROUP(uart_e_rx_z9, 3), + GROUP(pdm_din1_z, 3), + GROUP(pdm_din0_z, 3), + GROUP(pdm_dclk_z, 3), + + /* Bank Z func4 */ + GROUP(spi_a_miso_z, 4), + GROUP(spi_a_mosi_z, 4), + GROUP(spi_a_clk_z, 4), + GROUP(spi_a_ss0_z, 4), + GROUP(spi_a_ss1_z, 4), + GROUP(spi_a_ss2_z, 4), + GROUP(i2c4_scl_z, 4), + GROUP(i2c4_sda_z, 4), + + /* Bank Z func5 */ + GROUP(uart_d_tx_z, 5), + GROUP(uart_d_rx_z, 5), + GROUP(uart_d_cts_z, 5), + GROUP(uart_d_rts_z, 5), + GROUP(pwm_g_z, 5), + GROUP(pwm_f_z, 5), + GROUP(pwm_e_z, 5), + GROUP(tsin_b_clk_z, 5), + GROUP(tsin_b_sop_z, 5), + GROUP(tsin_b_valid_z, 5), + GROUP(tsin_b_d0_z, 5), + + /* Bank Z func6 */ + GROUP(s2_demod_gpio7, 6), + GROUP(s2_demod_gpio6, 6), + GROUP(s2_demod_gpio5, 6), + GROUP(s2_demod_gpio4, 6), + GROUP(s2_demod_gpio3, 6), + GROUP(s2_demod_gpio2, 6), + GROUP(diseqc_out, 6), + GROUP(s2_demod_gpio1, 6), + GROUP(s2_demod_gpio0, 6), + + /* Bank Z func7 */ + GROUP(gen_clk_z9, 7), + GROUP(gen_clk_z12, 7), +}; + +static const char * const gpio_periphs_groups[] = { + "GPIOE_0", "GPIOE_1", + + "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4", "GPIOB_5", + "GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9", "GPIOB_10", "GPIOB_11", + "GPIOB_12", "GPIOB_13", + + "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", "GPIOC_5", + "GPIOC_6", "GPIOC_7", + + "GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4", "GPIOD_5", + "GPIOD_6", "GPIOD_7", "GPIOD_8", "GPIOD_9", "GPIOD_10", "GPIOD_11", + + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", "GPIOH_5", + "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9", "GPIOH_10", "GPIOH_11", + + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", "GPIOX_5", + "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11", + "GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15", "GPIOX_16", "GPIOX_17", + "GPIOX_18", "GPIOX_19", + + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", "GPIOZ_5", + "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", "GPIOZ_10", + "GPIOZ_11", "GPIOZ_12", + + "GPIO_TEST_N", +}; + +static const char * const i2c0_groups[] = { + "i2c0_sda", "i2c0_scl", +}; + +static const char * const i2c1_groups[] = { + "i2c1_sda_c", "i2c1_scl_c", + "i2c1_sda_d", "i2c1_scl_d", + "i2c1_sda_h", "i2c1_scl_h", + "i2c1_sda_x", "i2c1_scl_x", +}; + +static const char * const i2c2_groups[] = { + "i2c2_sda_d", "i2c2_scl_d", + "i2c2_sda_h8", "i2c2_scl_h9", + "i2c2_sda_h0", "i2c2_scl_h1l," +}; + +static const char * const i2c3_groups[] = { + "i2c3_sda_x", "i2c3_scl_x", + "i2c3_sda_z", "i2c3_scl_z", +}; + +static const char * const i2c4_groups[] = { + "i2c4_sda_c", "i2c4_scl_c", + "i2c4_sda_d", "i2c4_scl_d", + "i2c4_scl_z", "i2c4_sda_z", +}; + +static const char * const uart_a_groups[] = { + "uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts", +}; + +static const char * const uart_b_groups[] = { + "uart_b_tx_e", "uart_b_rx_e", "uart_b_rx_c", "uart_b_tx_c", + "uart_b_tx_d", "uart_b_rx_d", "uart_b_cts_d", "uart_b_rts_d", +}; + +static const char * const uart_c_groups[] = { + "uart_c_tx", "uart_c_rx", +}; + +static const char * const uart_d_groups[] = { + "uart_d_tx_h", "uart_d_rx_h", "uart_d_cts_h", "uart_d_rts_h", + "uart_d_tx_z", "uart_d_rx_z", "uart_d_cts_z", "uart_d_rts_z", +}; + +static const char * const uart_e_groups[] = { + "uart_e_tx_h", "uart_e_rx_h", "uart_e_tx_z11", "uart_e_rx_z12", + "uart_e_tx_z8", "uart_e_rx_z9", +}; + +static const char * const emmc_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", + "emmc_clk", "emmc_rst", "emmc_cmd", "emmc_nand_ds", +}; + +static const char * const nand_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", + "nand_wen_clk", "nand_ale", "nand_ren_wr", "nand_cle", "nand_ce0", +}; + +static const char * const spif_groups[] = { + "spif_hold", "spif_mo", "spif_mi", "spif_clk", "spif_wp", + "spif_cs", +}; + +static const char * const sdcard_groups[] = { + "sdcard_d0_c", "sdcard_d1_c", "sdcard_d2_c", "sdcard_d3_c", + "sdcard_clk_c", "sdcard_cmd_c", "sdcard_cd", + "sdcard_d0_z", "sdcard_d1_z", "sdcard_d2_z", "sdcard_d3_z", + "sdcard_clk_z", "sdcard_cmd_z", +}; + +static const char * const jtag_1_groups[] = { + "jtag_1_clk", "jtag_1_tms", "jtag_1_tdi", "jtag_1_tdo", +}; + +static const char * const jtag_2_groups[] = { + "jtag_2_tdo", "jtag_2_tdi", "jtag_2_clk", "jtag_2_tms", +}; + +static const char * const pdm_groups[] = { + "pdm_din1_c", "pdm_din0_c", "pdm_dclk_c", + "pdm_dclk_d", "pdm_din0_d", "pdm_din1_d", + "pdm_dclk_h", "pdm_din0_h", "pdm_din1_h", + "pdm_din0_x", "pdm_din1_x", "pdm_dclk_x", + "pdm_din1_z", "pdm_din0_z", "pdm_dclk_z", +}; + +static const char * const iso7816_groups[] = { + "iso7816_clk_c", "iso7816_data_c", + "iso7816_clk_h", "iso7816_data_h", +}; + +static const char * const tdm_groups[] = { + "tdm_d2_c", "tdm_d3_c", "tdm_fs1_c", "tdm_d4_c", "tdm_d5_c", + "tdm_fs1_d", "tdm_d4_d", "tdm_d3_d", "tdm_d2_d", "tdm_sclk1_d", + "tdm_sclk1_h", "tdm_fs1_h", "tdm_d2_h", "tdm_d3_h", "tdm_d4_h", + "tdm_d1", "tdm_d0", "tdm_fs0", "tdm_sclk0", "tdm_fs2", "tdm_sclk2", + "tdm_d4_z", "tdm_d5_z", "tdm_d6", "tdm_d7", +}; + +static const char * const mclk_1_groups[] = { + "mclk_1_c", "mclk_1_d", "mclk_1_h", "mclk_2", +}; + +static const char * const mclk_2_groups[] = { + "mclk_2", +}; + +static const char * const remote_out_groups[] = { + "remote_out", +}; + +static const char * const remote_in_groups[] = { + "remote_in", +}; + +static const char * const clk12_24_groups[] = { + "clk12_24", +}; + +static const char * const clk_32k_in_groups[] = { + "clk_32k_in", +}; + +static const char * const pwm_a_hiz_groups[] = { + "pwm_a_hiz", +}; + +static const char * const pwm_b_hiz_groups[] = { + "pwm_b_hiz", +}; + +static const char * const pwm_c_hiz_groups[] = { + "pwm_c_hiz", +}; + +static const char * const pwm_g_hiz_groups[] = { + "pwm_g_hiz", +}; + +static const char * const pwm_a_groups[] = { + "pwm_a_d", +}; + +static const char * const pwm_b_groups[] = { + "pwm_b_d", "pwm_b_x", +}; + +static const char * const pwm_c_groups[] = { + "pwm_c_d", "pwm_c_x", +}; + +static const char * const pwm_d_groups[] = { + "pwm_d_d", "pwm_d_h", +}; + +static const char * const pwm_e_groups[] = { + "pwm_e_x", "pwm_e_z", +}; + +static const char * const pwm_f_groups[] = { + "pwm_f_x", "pwm_f_z", +}; + +static const char * const pwm_g_groups[] = { + "pwm_g_d", "pwm_g_z", +}; + +static const char * const pwm_h_groups[] = { + "pwm_h", +}; + +static const char * const pwm_i_groups[] = { + "pwm_i_d", "pwm_i_h" +}; + +static const char * const pwm_j_groups[] = { + "pwm_j", +}; + +static const char * const mic_mute_groups[] = { + "mic_mute_en", "mic_mute_key", +}; + +static const char * const hdmitx_groups[] = { + "hdmitx_sda", "hdmitx_sck", "hdmitx_hpd_in", +}; + +static const char * const ao_cec_a_groups[] = { + "ao_cec_a", +}; + +static const char * const ao_cec_b_groups[] = { + "ao_cec_b", +}; + +static const char * const spdif_out_groups[] = { + "spdif_out_h", "spdif_out_z", +}; + +static const char * const spdif_in_groups[] = { + "spdif_in", +}; + +static const char * const eth_groups[] = { + "eth_link_led", "eth_act_led", +}; + +static const char * const spi_a_groups[] = { + "spi_a_miso_h", "spi_a_mosi_h", "spi_a_clk_h", "spi_a_ss0_h", + + "spi_a_mosi_x", "spi_a_miso_x", "spi_a_ss0_x", "spi_a_clk_x", + + "spi_a_miso_z", "spi_a_mosi_z", "spi_a_clk_z", "spi_a_ss0_z", + "spi_a_ss1_z", "spi_a_ss2_z", +}; + +static const char * const gen_clk_groups[] = { + "gen_clk_h", "gen_clk_z9", "gen_clk_z12", +}; + +static const char * const sdio_groups[] = { + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", "sdio_clk", "sdio_cmd", +}; + +static const char * const i2c_slave_groups[] = { + "i2c_slave_scl", "i2c_slave_sda", +}; + +static const char * const dtv_groups[] = { + "dtv_a_if_agc_z10", "dtv_a_if_agc_z6", "dtv_b_if_agc", + "dtv_a_rf_agc", "dtv_b_rf_agc", +}; + +static const char * const tsin_a_groups[] = { + "tsin_a_clk", "tsin_a_sop", "tsin_a_valid", "tsin_a_din0", +}; + +static const char * const tsin_b_groups[] = { + "tsin_b_clk_c", "tsin_b_sop_c", "tsin_b_valid_c", "tsin_b_d0_c", + "tsin_b_clk_z", "tsin_b_sop_z", "tsin_b_valid_z", "tsin_b_d0_z", +}; + +static const char * const tsin_b1_groups[] = { + "tsin_b1_clk", "tsin_b1_sop", "tsin_b1_valid", "tsin_b1_d0", +}; + +static const char * const diseqc_out_groups[] = { + "diseqc_out", +}; + +static const char * const s2_demod_groups[] = { + "s2_demod_gpio7", "s2_demod_gpio6", "s2_demod_gpio5", "s2_demod_gpio4", + "s2_demod_gpio3", "s2_demod_gpio2", "s2_demod_gpio1", "s2_demod_gpio0", +}; + +static struct meson_pmx_func meson_s4_periphs_functions[] = { + FUNCTION(gpio_periphs), + FUNCTION(i2c0), + FUNCTION(i2c1), + FUNCTION(i2c2), + FUNCTION(i2c3), + FUNCTION(i2c4), + FUNCTION(uart_a), + FUNCTION(uart_b), + FUNCTION(uart_c), + FUNCTION(uart_d), + FUNCTION(uart_e), + FUNCTION(emmc), + FUNCTION(nand), + FUNCTION(spif), + FUNCTION(sdcard), + FUNCTION(jtag_1), + FUNCTION(jtag_2), + FUNCTION(pdm), + FUNCTION(iso7816), + FUNCTION(tdm), + FUNCTION(mclk_1), + FUNCTION(mclk_2), + FUNCTION(remote_out), + FUNCTION(remote_in), + FUNCTION(clk12_24), + FUNCTION(clk_32k_in), + FUNCTION(pwm_a_hiz), + FUNCTION(pwm_b_hiz), + FUNCTION(pwm_c_hiz), + FUNCTION(pwm_g_hiz), + FUNCTION(pwm_a), + FUNCTION(pwm_b), + FUNCTION(pwm_c), + FUNCTION(pwm_d), + FUNCTION(pwm_e), + FUNCTION(pwm_f), + FUNCTION(pwm_g), + FUNCTION(pwm_h), + FUNCTION(pwm_i), + FUNCTION(pwm_j), + FUNCTION(mic_mute), + FUNCTION(hdmitx), + FUNCTION(ao_cec_a), + FUNCTION(ao_cec_b), + FUNCTION(spdif_out), + FUNCTION(spdif_in), + FUNCTION(eth), + FUNCTION(spi_a), + FUNCTION(gen_clk), + FUNCTION(sdio), + FUNCTION(i2c_slave), + FUNCTION(dtv), + FUNCTION(tsin_a), + FUNCTION(tsin_b), + FUNCTION(tsin_b1), + FUNCTION(diseqc_out), + FUNCTION(s2_demod), +}; + +static struct meson_bank meson_s4_periphs_banks[] = { + /* name first last irq pullen pull dir out in */ + BANK_DS("B", GPIOB_0, GPIOB_13, 0, 13, + 0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0, 0x67, 0), + BANK_DS("C", GPIOC_0, GPIOC_7, 14, 21, + 0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0, 0x57, 0), + BANK_DS("E", GPIOE_0, GPIOE_1, 22, 23, + 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0, 0x47, 0), + BANK_DS("D", GPIOD_0, GPIOD_11, 24, 35, + 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0, 0x37, 0), + BANK_DS("H", GPIOH_0, GPIOH_11, 36, 47, + 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0, 0x27, 0), + BANK_DS("X", GPIOX_0, GPIOX_19, 48, 67, + 0x13, 0, 0x14, 0, 0x12, 0, 0x11, 0, 0x10, 0, 0x17, 0), + BANK_DS("Z", GPIOZ_0, GPIOZ_12, 68, 80, + 0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0, 0x07, 0), + BANK_DS("TEST_N", GPIO_TEST_N, GPIO_TEST_N, -1, -1, + 0x83, 0, 0x84, 0, 0x82, 0, 0x81, 0, 0x80, 0, 0x87, 0), +}; + +static struct meson_pmx_bank meson_s4_periphs_pmx_banks[] = { + /*name first lask reg offset*/ + BANK_PMX("B", GPIOB_0, GPIOB_13, 0x00, 0), + BANK_PMX("C", GPIOC_0, GPIOC_7, 0x9, 0), + BANK_PMX("E", GPIOE_0, GPIOE_1, 0x12, 0), + BANK_PMX("D", GPIOD_0, GPIOD_11, 0x10, 0), + BANK_PMX("H", GPIOH_0, GPIOH_11, 0xb, 0), + BANK_PMX("X", GPIOX_0, GPIOX_19, 0x3, 0), + BANK_PMX("Z", GPIOZ_0, GPIOZ_12, 0x6, 0), + BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0xf, 0) +}; + +static struct meson_axg_pmx_data meson_s4_periphs_pmx_banks_data = { + .pmx_banks = meson_s4_periphs_pmx_banks, + .num_pmx_banks = ARRAY_SIZE(meson_s4_periphs_pmx_banks), +}; + +static struct meson_pinctrl_data meson_s4_periphs_pinctrl_data = { + .name = "periphs-banks", + .pins = meson_s4_periphs_pins, + .groups = meson_s4_periphs_groups, + .funcs = meson_s4_periphs_functions, + .banks = meson_s4_periphs_banks, + .num_pins = ARRAY_SIZE(meson_s4_periphs_pins), + .num_groups = ARRAY_SIZE(meson_s4_periphs_groups), + .num_funcs = ARRAY_SIZE(meson_s4_periphs_functions), + .num_banks = ARRAY_SIZE(meson_s4_periphs_banks), + .pmx_ops = &meson_axg_pmx_ops, + .pmx_data = &meson_s4_periphs_pmx_banks_data, + .parse_dt = &meson_a1_parse_dt_extra, +}; + +static const struct of_device_id meson_s4_pinctrl_dt_match[] = { + { + .compatible = "amlogic,meson-s4-periphs-pinctrl", + .data = &meson_s4_periphs_pinctrl_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, meson_s4_pinctrl_dt_match); + +static struct platform_driver meson_s4_pinctrl_driver = { + .probe = meson_pinctrl_probe, + .driver = { + .name = "meson-s4-pinctrl", + .of_match_table = meson_s4_pinctrl_dt_match, + }, +}; +module_platform_driver(meson_s4_pinctrl_driver); + +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index 39828e9c3120..4757bf964d3c 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -1883,8 +1883,10 @@ static int nmk_pinctrl_probe(struct platform_device *pdev) } prcm_np = of_parse_phandle(np, "prcm", 0); - if (prcm_np) + if (prcm_np) { npct->prcm_base = of_iomap(prcm_np, 0); + of_node_put(prcm_np); + } if (!npct->prcm_base) { if (version == PINCTRL_NMK_STN8815) { dev_info(&pdev->dev, diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig index 48ba0469edda..852b0d0eb08e 100644 --- a/drivers/pinctrl/nuvoton/Kconfig +++ b/drivers/pinctrl/nuvoton/Kconfig @@ -1,4 +1,24 @@ # SPDX-License-Identifier: GPL-2.0-only + +config PINCTRL_WPCM450 + tristate "Pinctrl and GPIO driver for Nuvoton WPCM450" + depends on ARCH_WPCM450 || COMPILE_TEST + depends on OF + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GPIOLIB + select GPIO_GENERIC + select GPIOLIB_IRQCHIP + help + Say Y or M here to enable pin controller and GPIO support for + the Nuvoton WPCM450 SoC. This is strongly recommended when + building a kernel that will run on this chip. + + If this driver is compiled as a module, it will be named + pinctrl-wpcm450. + config PINCTRL_NPCM7XX bool "Pinctrl and GPIO driver for Nuvoton NPCM7XX" depends on (ARCH_NPCM7XX || COMPILE_TEST) && OF diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile index 886d00784cef..9e66f5dc74bf 100644 --- a/drivers/pinctrl/nuvoton/Makefile +++ b/drivers/pinctrl/nuvoton/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 # Nuvoton pinctrl support +obj-$(CONFIG_PINCTRL_WPCM450) += pinctrl-wpcm450.o obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c index ba536fd4d674..9557fac5d11c 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -216,7 +216,7 @@ static void npcmgpio_irq_handler(struct irq_desc *desc) struct gpio_chip *gc; struct irq_chip *chip; struct npcm7xx_gpio *bank; - u32 sts, en, bit; + unsigned long sts, en, bit; gc = irq_desc_get_handler_data(desc); bank = gpiochip_get_data(gc); @@ -225,11 +225,11 @@ static void npcmgpio_irq_handler(struct irq_desc *desc) chained_irq_enter(chip, desc); sts = ioread32(bank->base + NPCM7XX_GP_N_EVST); en = ioread32(bank->base + NPCM7XX_GP_N_EVEN); - dev_dbg(bank->gc.parent, "==> got irq sts %.8x %.8x\n", sts, + dev_dbg(bank->gc.parent, "==> got irq sts %.8lx %.8lx\n", sts, en); sts &= en; - for_each_set_bit(bit, (const void *)&sts, NPCM7XX_GPIO_PER_BANK) + for_each_set_bit(bit, &sts, NPCM7XX_GPIO_PER_BANK) generic_handle_domain_irq(gc->irq.domain, bit); chained_irq_exit(chip, desc); } @@ -894,7 +894,7 @@ static struct npcm7xx_func npcm7xx_funcs[] = { }; #define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \ - [a] { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \ + [a] = { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \ .fn1 = fn_ ## e, .reg1 = NPCM7XX_GCR_ ## f, .bit1 = g, \ .fn2 = fn_ ## h, .reg2 = NPCM7XX_GCR_ ## i, .bit2 = j, \ .flag = k } @@ -904,7 +904,7 @@ static struct npcm7xx_func npcm7xx_funcs[] = { #define DRIVE_STRENGTH_HI_SHIFT 12 #define DRIVE_STRENGTH_MASK 0x0000FF00 -#define DS(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \ +#define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \ ((hi) << DRIVE_STRENGTH_HI_SHIFT)) #define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF) #define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF) @@ -924,31 +924,31 @@ struct npcm7xx_pincfg { static const struct npcm7xx_pincfg pincfg[] = { /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */ NPCM7XX_PINCFG(0, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(3, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW), NPCM7XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW), NPCM7XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW), NPCM7XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW), - NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW), NPCM7XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW), NPCM7XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW), NPCM7XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW), - NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(20, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0), NPCM7XX_PINCFG(21, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0), NPCM7XX_PINCFG(22, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0), NPCM7XX_PINCFG(23, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0), - NPCM7XX_PINCFG(24, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(25, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(24, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(25, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0), @@ -964,12 +964,12 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(39, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW), NPCM7XX_PINCFG(40, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW), NPCM7XX_PINCFG(41, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DS(2, 4) | GPO), + NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DSTR(2, 4) | GPO), NPCM7XX_PINCFG(43, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0), NPCM7XX_PINCFG(44, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0), NPCM7XX_PINCFG(45, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DS(2, 8)), - NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DS(2, 8)), + NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)), + NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)), NPCM7XX_PINCFG(48, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, GPO), NPCM7XX_PINCFG(49, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, 0), NPCM7XX_PINCFG(50, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), @@ -979,8 +979,8 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(54, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(55, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DS(2, 4)), - NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DS(2, 4)), + NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), + NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), NPCM7XX_PINCFG(59, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(60, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(61, uart1, MFSEL1, 10, none, NONE, 0, none, NONE, 0, GPO), @@ -1003,19 +1003,19 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM7XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DS(2, 4)), - NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DS(2, 4)), + NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), + NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), NPCM7XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0), NPCM7XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0), NPCM7XX_PINCFG(95, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0), @@ -1061,34 +1061,34 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(134, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(135, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM7XX_PINCFG(141, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM7XX_PINCFG(143, sd1, MFSEL3, 12, sd1pwr, MFSEL4, 5, none, NONE, 0, 0), - NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM7XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, 0), /* Z1/A1 */ - NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM7XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, 0), /* Z1/A1 */ - NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - - NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DS(8, 12)), - NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + + NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DSTR(8, 12)), + NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(163, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0), NPCM7XX_PINCFG(164, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), NPCM7XX_PINCFG(165, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), @@ -1101,25 +1101,25 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM7XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), - NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), - NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DS(2, 4)), - NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), /* XX */ - - NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), /* XX */ + NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), + NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), + NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DSTR(2, 4)), + NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */ + + NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */ NPCM7XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(194, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(195, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0), @@ -1130,11 +1130,11 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(202, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(204, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW), NPCM7XX_PINCFG(205, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW), - NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)), + NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)), NPCM7XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), NPCM7XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), NPCM7XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), @@ -1146,20 +1146,20 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0), NPCM7XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0), NPCM7XX_PINCFG(218, wdog1, MFSEL3, 19, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DS(4, 8)), + NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), NPCM7XX_PINCFG(220, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(221, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(224, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, SLEW), - NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), - NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), - NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), + NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), + NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */ NPCM7XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */ NPCM7XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */ @@ -1560,7 +1560,7 @@ static int npcm7xx_get_groups_count(struct pinctrl_dev *pctldev) { struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); - dev_dbg(npcm->dev, "group size: %d\n", ARRAY_SIZE(npcm7xx_groups)); + dev_dbg(npcm->dev, "group size: %zu\n", ARRAY_SIZE(npcm7xx_groups)); return ARRAY_SIZE(npcm7xx_groups); } diff --git a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c new file mode 100644 index 000000000000..0dbeb91f0bf2 --- /dev/null +++ b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c @@ -0,0 +1,1151 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2016-2018 Nuvoton Technology corporation. +// Copyright (c) 2016, Dell Inc +// Copyright (c) 2021-2022 Jonathan Neuschäfer +// +// This driver uses the following registers: +// - Pin mux registers, in the GCR (general control registers) block +// - GPIO registers, specific to each GPIO bank +// - GPIO event (interrupt) registers, located centrally in the GPIO register +// block, shared between all GPIO banks + +#include <linux/device.h> +#include <linux/fwnode.h> +#include <linux/gpio/driver.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include "../core.h" + +/* GCR registers */ +#define WPCM450_GCR_MFSEL1 0x0c +#define WPCM450_GCR_MFSEL2 0x10 +#define WPCM450_GCR_NONE 0 + +/* GPIO event (interrupt) registers */ +#define WPCM450_GPEVTYPE 0x00 +#define WPCM450_GPEVPOL 0x04 +#define WPCM450_GPEVDBNC 0x08 +#define WPCM450_GPEVEN 0x0c +#define WPCM450_GPEVST 0x10 + +#define WPCM450_NUM_BANKS 8 +#define WPCM450_NUM_GPIOS 128 +#define WPCM450_NUM_GPIO_IRQS 4 + +struct wpcm450_pinctrl; +struct wpcm450_bank; + +struct wpcm450_gpio { + struct gpio_chip gc; + struct wpcm450_pinctrl *pctrl; + struct irq_chip irqc; + const struct wpcm450_bank *bank; +}; + +struct wpcm450_pinctrl { + struct pinctrl_dev *pctldev; + struct device *dev; + struct irq_domain *domain; + struct regmap *gcr_regmap; + void __iomem *gpio_base; + struct wpcm450_gpio gpio_bank[WPCM450_NUM_BANKS]; + unsigned long both_edges; + + /* + * This spin lock protects registers and struct wpcm450_pinctrl fields + * against concurrent access. + */ + raw_spinlock_t lock; +}; + +struct wpcm450_bank { + /* Range of GPIOs in this port */ + u8 base; + u8 length; + + /* Register offsets (0 = register doesn't exist in this port) */ + u8 cfg0, cfg1, cfg2; + u8 blink; + u8 dataout, datain; + + /* Interrupt bit mapping */ + u8 first_irq_bit; /* First bit in GPEVST that belongs to this bank */ + u8 num_irqs; /* Number of IRQ-capable GPIOs in this bank */ + u8 first_irq_gpio; /* First IRQ-capable GPIO in this bank */ +}; + +static const struct wpcm450_bank wpcm450_banks[WPCM450_NUM_BANKS] = { + /* range cfg0 cfg1 cfg2 blink out in IRQ map */ + { 0, 16, 0x14, 0x18, 0, 0, 0x1c, 0x20, 0, 16, 0 }, + { 16, 16, 0x24, 0x28, 0x2c, 0x30, 0x34, 0x38, 16, 2, 8 }, + { 32, 16, 0x3c, 0x40, 0x44, 0, 0x48, 0x4c, 0, 0, 0 }, + { 48, 16, 0x50, 0x54, 0x58, 0, 0x5c, 0x60, 0, 0, 0 }, + { 64, 16, 0x64, 0x68, 0x6c, 0, 0x70, 0x74, 0, 0, 0 }, + { 80, 16, 0x78, 0x7c, 0x80, 0, 0x84, 0x88, 0, 0, 0 }, + { 96, 18, 0, 0, 0, 0, 0, 0x8c, 0, 0, 0 }, + { 114, 14, 0x90, 0x94, 0x98, 0, 0x9c, 0xa0, 0, 0, 0 }, +}; + +static int wpcm450_gpio_irq_bitnum(struct wpcm450_gpio *gpio, struct irq_data *d) +{ + const struct wpcm450_bank *bank = gpio->bank; + int hwirq = irqd_to_hwirq(d); + + if (hwirq < bank->first_irq_gpio) + return -EINVAL; + + if (hwirq - bank->first_irq_gpio >= bank->num_irqs) + return -EINVAL; + + return hwirq - bank->first_irq_gpio + bank->first_irq_bit; +} + +static int wpcm450_irq_bitnum_to_gpio(struct wpcm450_gpio *gpio, int bitnum) +{ + const struct wpcm450_bank *bank = gpio->bank; + + if (bitnum < bank->first_irq_bit) + return -EINVAL; + + if (bitnum - bank->first_irq_bit > bank->num_irqs) + return -EINVAL; + + return bitnum - bank->first_irq_bit + bank->first_irq_gpio; +} + +static void wpcm450_gpio_irq_ack(struct irq_data *d) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct wpcm450_pinctrl *pctrl = gpio->pctrl; + unsigned long flags; + int bit; + + bit = wpcm450_gpio_irq_bitnum(gpio, d); + if (bit < 0) + return; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void wpcm450_gpio_irq_mask(struct irq_data *d) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct wpcm450_pinctrl *pctrl = gpio->pctrl; + unsigned long flags; + unsigned long even; + int bit; + + bit = wpcm450_gpio_irq_bitnum(gpio, d); + if (bit < 0) + return; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN); + __assign_bit(bit, &even, 0); + iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void wpcm450_gpio_irq_unmask(struct irq_data *d) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct wpcm450_pinctrl *pctrl = gpio->pctrl; + unsigned long flags; + unsigned long even; + int bit; + + bit = wpcm450_gpio_irq_bitnum(gpio, d); + if (bit < 0) + return; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN); + __assign_bit(bit, &even, 1); + iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); +} + +/* + * This is an implementation of the gpio_chip->get() function, for use in + * wpcm450_gpio_fix_evpol. Unfortunately, we can't use the bgpio-provided + * implementation there, because it would require taking gpio_chip->bgpio_lock, + * which is a spin lock, but wpcm450_gpio_fix_evpol must work in contexts where + * a raw spin lock is held. + */ +static int wpcm450_gpio_get(struct wpcm450_gpio *gpio, int offset) +{ + void __iomem *reg = gpio->pctrl->gpio_base + gpio->bank->datain; + unsigned long flags; + u32 level; + + raw_spin_lock_irqsave(&gpio->pctrl->lock, flags); + level = !!(ioread32(reg) & BIT(offset)); + raw_spin_unlock_irqrestore(&gpio->pctrl->lock, flags); + + return level; +} + +/* + * Since the GPIO controller does not support dual-edge triggered interrupts + * (IRQ_TYPE_EDGE_BOTH), they are emulated using rising/falling edge triggered + * interrupts. wpcm450_gpio_fix_evpol sets the interrupt polarity for the + * specified emulated dual-edge triggered interrupts, so that the next edge can + * be detected. + */ +static void wpcm450_gpio_fix_evpol(struct wpcm450_gpio *gpio, unsigned long all) +{ + struct wpcm450_pinctrl *pctrl = gpio->pctrl; + unsigned int bit; + + for_each_set_bit(bit, &all, 32) { + int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit); + unsigned long evpol; + unsigned long flags; + int level; + + do { + level = wpcm450_gpio_get(gpio, offset); + + /* Switch event polarity to the opposite of the current level */ + raw_spin_lock_irqsave(&pctrl->lock, flags); + evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL); + __assign_bit(bit, &evpol, !level); + iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + } while (wpcm450_gpio_get(gpio, offset) != level); + } +} + +static int wpcm450_gpio_set_irq_type(struct irq_data *d, unsigned int flow_type) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct wpcm450_pinctrl *pctrl = gpio->pctrl; + unsigned long evtype, evpol; + unsigned long flags; + int ret = 0; + int bit; + + bit = wpcm450_gpio_irq_bitnum(gpio, d); + if (bit < 0) + return bit; + + irq_set_handler_locked(d, handle_level_irq); + + raw_spin_lock_irqsave(&pctrl->lock, flags); + evtype = ioread32(pctrl->gpio_base + WPCM450_GPEVTYPE); + evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL); + __assign_bit(bit, &pctrl->both_edges, 0); + switch (flow_type) { + case IRQ_TYPE_LEVEL_LOW: + __assign_bit(bit, &evtype, 1); + __assign_bit(bit, &evpol, 0); + break; + case IRQ_TYPE_LEVEL_HIGH: + __assign_bit(bit, &evtype, 1); + __assign_bit(bit, &evpol, 1); + break; + case IRQ_TYPE_EDGE_FALLING: + __assign_bit(bit, &evtype, 0); + __assign_bit(bit, &evpol, 0); + break; + case IRQ_TYPE_EDGE_RISING: + __assign_bit(bit, &evtype, 0); + __assign_bit(bit, &evpol, 1); + break; + case IRQ_TYPE_EDGE_BOTH: + __assign_bit(bit, &evtype, 0); + __assign_bit(bit, &pctrl->both_edges, 1); + break; + default: + ret = -EINVAL; + } + iowrite32(evtype, pctrl->gpio_base + WPCM450_GPEVTYPE); + iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL); + + /* clear the event status for good measure */ + iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST); + + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + /* fix event polarity after clearing event status */ + wpcm450_gpio_fix_evpol(gpio, BIT(bit)); + + return ret; +} + +static const struct irq_chip wpcm450_gpio_irqchip = { + .name = "WPCM450-GPIO-IRQ", + .irq_ack = wpcm450_gpio_irq_ack, + .irq_unmask = wpcm450_gpio_irq_unmask, + .irq_mask = wpcm450_gpio_irq_mask, + .irq_set_type = wpcm450_gpio_set_irq_type, +}; + +static void wpcm450_gpio_irqhandler(struct irq_desc *desc) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(irq_desc_get_handler_data(desc)); + struct wpcm450_pinctrl *pctrl = gpio->pctrl; + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned long pending; + unsigned long flags; + unsigned long ours; + unsigned int bit; + + ours = GENMASK(gpio->bank->num_irqs - 1, 0) << gpio->bank->first_irq_bit; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + + pending = ioread32(pctrl->gpio_base + WPCM450_GPEVST); + pending &= ioread32(pctrl->gpio_base + WPCM450_GPEVEN); + pending &= ours; + + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + if (pending & pctrl->both_edges) + wpcm450_gpio_fix_evpol(gpio, pending & pctrl->both_edges); + + chained_irq_enter(chip, desc); + for_each_set_bit(bit, &pending, 32) { + int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit); + + generic_handle_domain_irq(gpio->gc.irq.domain, offset); + } + chained_irq_exit(chip, desc); +} + +static int smb0_pins[] = { 115, 114 }; +static int smb1_pins[] = { 117, 116 }; +static int smb2_pins[] = { 119, 118 }; +static int smb3_pins[] = { 30, 31 }; +static int smb4_pins[] = { 28, 29 }; +static int smb5_pins[] = { 26, 27 }; + +static int scs1_pins[] = { 32 }; +static int scs2_pins[] = { 33 }; +static int scs3_pins[] = { 34 }; + +static int bsp_pins[] = { 41, 42 }; +static int hsp1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 }; +static int hsp2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 }; + +static int r1err_pins[] = { 56 }; +static int r1md_pins[] = { 57, 58 }; +static int rmii2_pins[] = { 84, 85, 86, 87, 88, 89 }; +static int r2err_pins[] = { 90 }; +static int r2md_pins[] = { 91, 92 }; + +static int kbcc_pins[] = { 94, 93 }; +static int clko_pins[] = { 96 }; +static int smi_pins[] = { 97 }; +static int uinc_pins[] = { 19 }; +static int mben_pins[] = {}; + +static int gspi_pins[] = { 12, 13, 14, 15 }; +static int sspi_pins[] = { 12, 13, 14, 15 }; + +static int xcs1_pins[] = { 35 }; +static int xcs2_pins[] = { 36 }; + +static int sdio_pins[] = { 7, 22, 43, 44, 45, 46, 47, 60 }; + +static int fi0_pins[] = { 64 }; +static int fi1_pins[] = { 65 }; +static int fi2_pins[] = { 66 }; +static int fi3_pins[] = { 67 }; +static int fi4_pins[] = { 68 }; +static int fi5_pins[] = { 69 }; +static int fi6_pins[] = { 70 }; +static int fi7_pins[] = { 71 }; +static int fi8_pins[] = { 72 }; +static int fi9_pins[] = { 73 }; +static int fi10_pins[] = { 74 }; +static int fi11_pins[] = { 75 }; +static int fi12_pins[] = { 76 }; +static int fi13_pins[] = { 77 }; +static int fi14_pins[] = { 78 }; +static int fi15_pins[] = { 79 }; + +static int pwm0_pins[] = { 80 }; +static int pwm1_pins[] = { 81 }; +static int pwm2_pins[] = { 82 }; +static int pwm3_pins[] = { 83 }; +static int pwm4_pins[] = { 20 }; +static int pwm5_pins[] = { 21 }; +static int pwm6_pins[] = { 16 }; +static int pwm7_pins[] = { 17 }; + +static int hg0_pins[] = { 20 }; +static int hg1_pins[] = { 21 }; +static int hg2_pins[] = { 22 }; +static int hg3_pins[] = { 23 }; +static int hg4_pins[] = { 24 }; +static int hg5_pins[] = { 25 }; +static int hg6_pins[] = { 59 }; +static int hg7_pins[] = { 60 }; + +#define WPCM450_GRPS \ + WPCM450_GRP(smb3), \ + WPCM450_GRP(smb4), \ + WPCM450_GRP(smb5), \ + WPCM450_GRP(scs1), \ + WPCM450_GRP(scs2), \ + WPCM450_GRP(scs3), \ + WPCM450_GRP(smb0), \ + WPCM450_GRP(smb1), \ + WPCM450_GRP(smb2), \ + WPCM450_GRP(bsp), \ + WPCM450_GRP(hsp1), \ + WPCM450_GRP(hsp2), \ + WPCM450_GRP(r1err), \ + WPCM450_GRP(r1md), \ + WPCM450_GRP(rmii2), \ + WPCM450_GRP(r2err), \ + WPCM450_GRP(r2md), \ + WPCM450_GRP(kbcc), \ + WPCM450_GRP(clko), \ + WPCM450_GRP(smi), \ + WPCM450_GRP(uinc), \ + WPCM450_GRP(gspi), \ + WPCM450_GRP(mben), \ + WPCM450_GRP(xcs2), \ + WPCM450_GRP(xcs1), \ + WPCM450_GRP(sdio), \ + WPCM450_GRP(sspi), \ + WPCM450_GRP(fi0), \ + WPCM450_GRP(fi1), \ + WPCM450_GRP(fi2), \ + WPCM450_GRP(fi3), \ + WPCM450_GRP(fi4), \ + WPCM450_GRP(fi5), \ + WPCM450_GRP(fi6), \ + WPCM450_GRP(fi7), \ + WPCM450_GRP(fi8), \ + WPCM450_GRP(fi9), \ + WPCM450_GRP(fi10), \ + WPCM450_GRP(fi11), \ + WPCM450_GRP(fi12), \ + WPCM450_GRP(fi13), \ + WPCM450_GRP(fi14), \ + WPCM450_GRP(fi15), \ + WPCM450_GRP(pwm0), \ + WPCM450_GRP(pwm1), \ + WPCM450_GRP(pwm2), \ + WPCM450_GRP(pwm3), \ + WPCM450_GRP(pwm4), \ + WPCM450_GRP(pwm5), \ + WPCM450_GRP(pwm6), \ + WPCM450_GRP(pwm7), \ + WPCM450_GRP(hg0), \ + WPCM450_GRP(hg1), \ + WPCM450_GRP(hg2), \ + WPCM450_GRP(hg3), \ + WPCM450_GRP(hg4), \ + WPCM450_GRP(hg5), \ + WPCM450_GRP(hg6), \ + WPCM450_GRP(hg7), \ + +enum { +#define WPCM450_GRP(x) fn_ ## x + WPCM450_GRPS + /* add placeholder for none/gpio */ + WPCM450_GRP(gpio), + WPCM450_GRP(none), +#undef WPCM450_GRP +}; + +static struct group_desc wpcm450_groups[] = { +#define WPCM450_GRP(x) { .name = #x, .pins = x ## _pins, \ + .num_pins = ARRAY_SIZE(x ## _pins) } + WPCM450_GRPS +#undef WPCM450_GRP +}; + +#define WPCM450_SFUNC(a) WPCM450_FUNC(a, #a) +#define WPCM450_FUNC(a, b...) static const char *a ## _grp[] = { b } +#define WPCM450_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \ + .groups = nm ## _grp } +struct wpcm450_func { + const char *name; + const unsigned int ngroups; + const char *const *groups; +}; + +WPCM450_SFUNC(smb3); +WPCM450_SFUNC(smb4); +WPCM450_SFUNC(smb5); +WPCM450_SFUNC(scs1); +WPCM450_SFUNC(scs2); +WPCM450_SFUNC(scs3); +WPCM450_SFUNC(smb0); +WPCM450_SFUNC(smb1); +WPCM450_SFUNC(smb2); +WPCM450_SFUNC(bsp); +WPCM450_SFUNC(hsp1); +WPCM450_SFUNC(hsp2); +WPCM450_SFUNC(r1err); +WPCM450_SFUNC(r1md); +WPCM450_SFUNC(rmii2); +WPCM450_SFUNC(r2err); +WPCM450_SFUNC(r2md); +WPCM450_SFUNC(kbcc); +WPCM450_SFUNC(clko); +WPCM450_SFUNC(smi); +WPCM450_SFUNC(uinc); +WPCM450_SFUNC(gspi); +WPCM450_SFUNC(mben); +WPCM450_SFUNC(xcs2); +WPCM450_SFUNC(xcs1); +WPCM450_SFUNC(sdio); +WPCM450_SFUNC(sspi); +WPCM450_SFUNC(fi0); +WPCM450_SFUNC(fi1); +WPCM450_SFUNC(fi2); +WPCM450_SFUNC(fi3); +WPCM450_SFUNC(fi4); +WPCM450_SFUNC(fi5); +WPCM450_SFUNC(fi6); +WPCM450_SFUNC(fi7); +WPCM450_SFUNC(fi8); +WPCM450_SFUNC(fi9); +WPCM450_SFUNC(fi10); +WPCM450_SFUNC(fi11); +WPCM450_SFUNC(fi12); +WPCM450_SFUNC(fi13); +WPCM450_SFUNC(fi14); +WPCM450_SFUNC(fi15); +WPCM450_SFUNC(pwm0); +WPCM450_SFUNC(pwm1); +WPCM450_SFUNC(pwm2); +WPCM450_SFUNC(pwm3); +WPCM450_SFUNC(pwm4); +WPCM450_SFUNC(pwm5); +WPCM450_SFUNC(pwm6); +WPCM450_SFUNC(pwm7); +WPCM450_SFUNC(hg0); +WPCM450_SFUNC(hg1); +WPCM450_SFUNC(hg2); +WPCM450_SFUNC(hg3); +WPCM450_SFUNC(hg4); +WPCM450_SFUNC(hg5); +WPCM450_SFUNC(hg6); +WPCM450_SFUNC(hg7); + +#define WPCM450_GRP(x) #x +WPCM450_FUNC(gpio, WPCM450_GRPS); +#undef WPCM450_GRP + +/* Function names */ +static struct wpcm450_func wpcm450_funcs[] = { + WPCM450_MKFUNC(smb3), + WPCM450_MKFUNC(smb4), + WPCM450_MKFUNC(smb5), + WPCM450_MKFUNC(scs1), + WPCM450_MKFUNC(scs2), + WPCM450_MKFUNC(scs3), + WPCM450_MKFUNC(smb0), + WPCM450_MKFUNC(smb1), + WPCM450_MKFUNC(smb2), + WPCM450_MKFUNC(bsp), + WPCM450_MKFUNC(hsp1), + WPCM450_MKFUNC(hsp2), + WPCM450_MKFUNC(r1err), + WPCM450_MKFUNC(r1md), + WPCM450_MKFUNC(rmii2), + WPCM450_MKFUNC(r2err), + WPCM450_MKFUNC(r2md), + WPCM450_MKFUNC(kbcc), + WPCM450_MKFUNC(clko), + WPCM450_MKFUNC(smi), + WPCM450_MKFUNC(uinc), + WPCM450_MKFUNC(gspi), + WPCM450_MKFUNC(mben), + WPCM450_MKFUNC(xcs2), + WPCM450_MKFUNC(xcs1), + WPCM450_MKFUNC(sdio), + WPCM450_MKFUNC(sspi), + WPCM450_MKFUNC(fi0), + WPCM450_MKFUNC(fi1), + WPCM450_MKFUNC(fi2), + WPCM450_MKFUNC(fi3), + WPCM450_MKFUNC(fi4), + WPCM450_MKFUNC(fi5), + WPCM450_MKFUNC(fi6), + WPCM450_MKFUNC(fi7), + WPCM450_MKFUNC(fi8), + WPCM450_MKFUNC(fi9), + WPCM450_MKFUNC(fi10), + WPCM450_MKFUNC(fi11), + WPCM450_MKFUNC(fi12), + WPCM450_MKFUNC(fi13), + WPCM450_MKFUNC(fi14), + WPCM450_MKFUNC(fi15), + WPCM450_MKFUNC(pwm0), + WPCM450_MKFUNC(pwm1), + WPCM450_MKFUNC(pwm2), + WPCM450_MKFUNC(pwm3), + WPCM450_MKFUNC(pwm4), + WPCM450_MKFUNC(pwm5), + WPCM450_MKFUNC(pwm6), + WPCM450_MKFUNC(pwm7), + WPCM450_MKFUNC(hg0), + WPCM450_MKFUNC(hg1), + WPCM450_MKFUNC(hg2), + WPCM450_MKFUNC(hg3), + WPCM450_MKFUNC(hg4), + WPCM450_MKFUNC(hg5), + WPCM450_MKFUNC(hg6), + WPCM450_MKFUNC(hg7), + WPCM450_MKFUNC(gpio), +}; + +#define WPCM450_PINCFG(a, b, c, d, e, f, g) \ + [a] = { .fn0 = fn_ ## b, .reg0 = WPCM450_GCR_ ## c, .bit0 = d, \ + .fn1 = fn_ ## e, .reg1 = WPCM450_GCR_ ## f, .bit1 = g } + +struct wpcm450_pincfg { + int fn0, reg0, bit0; + int fn1, reg1, bit1; +}; + +static const struct wpcm450_pincfg pincfg[] = { + /* PIN FUNCTION 1 FUNCTION 2 */ + WPCM450_PINCFG(0, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(1, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(2, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(3, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(4, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(5, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(6, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(7, none, NONE, 0, sdio, MFSEL1, 30), + WPCM450_PINCFG(8, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(9, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(10, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(11, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(12, gspi, MFSEL1, 24, sspi, MFSEL1, 31), + WPCM450_PINCFG(13, gspi, MFSEL1, 24, sspi, MFSEL1, 31), + WPCM450_PINCFG(14, gspi, MFSEL1, 24, sspi, MFSEL1, 31), + WPCM450_PINCFG(15, gspi, MFSEL1, 24, sspi, MFSEL1, 31), + WPCM450_PINCFG(16, none, NONE, 0, pwm6, MFSEL2, 22), + WPCM450_PINCFG(17, none, NONE, 0, pwm7, MFSEL2, 23), + WPCM450_PINCFG(18, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(19, uinc, MFSEL1, 23, none, NONE, 0), + WPCM450_PINCFG(20, hg0, MFSEL2, 24, pwm4, MFSEL2, 20), + WPCM450_PINCFG(21, hg1, MFSEL2, 25, pwm5, MFSEL2, 21), + WPCM450_PINCFG(22, hg2, MFSEL2, 26, none, NONE, 0), + WPCM450_PINCFG(23, hg3, MFSEL2, 27, none, NONE, 0), + WPCM450_PINCFG(24, hg4, MFSEL2, 28, none, NONE, 0), + WPCM450_PINCFG(25, hg5, MFSEL2, 29, none, NONE, 0), + WPCM450_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0), + WPCM450_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0), + WPCM450_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0), + WPCM450_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0), + WPCM450_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0), + WPCM450_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0), + + WPCM450_PINCFG(32, scs1, MFSEL1, 3, none, NONE, 0), + WPCM450_PINCFG(33, scs2, MFSEL1, 4, none, NONE, 0), + WPCM450_PINCFG(34, scs3, MFSEL1, 5, none, NONE, 0), + WPCM450_PINCFG(35, xcs1, MFSEL1, 29, none, NONE, 0), + WPCM450_PINCFG(36, xcs2, MFSEL1, 28, none, NONE, 0), + WPCM450_PINCFG(37, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(38, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(39, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(40, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(41, bsp, MFSEL1, 9, none, NONE, 0), + WPCM450_PINCFG(42, bsp, MFSEL1, 9, none, NONE, 0), + WPCM450_PINCFG(43, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(44, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(45, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(46, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(47, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(48, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(49, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(50, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(51, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(52, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(53, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(54, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(55, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0), + WPCM450_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0), + WPCM450_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0), + WPCM450_PINCFG(59, hg6, MFSEL2, 30, none, NONE, 0), + WPCM450_PINCFG(60, hg7, MFSEL2, 31, sdio, MFSEL1, 30), + WPCM450_PINCFG(61, hsp1, MFSEL1, 10, none, NONE, 0), + WPCM450_PINCFG(62, hsp1, MFSEL1, 10, none, NONE, 0), + WPCM450_PINCFG(63, hsp1, MFSEL1, 10, none, NONE, 0), + + WPCM450_PINCFG(64, fi0, MFSEL2, 0, none, NONE, 0), + WPCM450_PINCFG(65, fi1, MFSEL2, 1, none, NONE, 0), + WPCM450_PINCFG(66, fi2, MFSEL2, 2, none, NONE, 0), + WPCM450_PINCFG(67, fi3, MFSEL2, 3, none, NONE, 0), + WPCM450_PINCFG(68, fi4, MFSEL2, 4, none, NONE, 0), + WPCM450_PINCFG(69, fi5, MFSEL2, 5, none, NONE, 0), + WPCM450_PINCFG(70, fi6, MFSEL2, 6, none, NONE, 0), + WPCM450_PINCFG(71, fi7, MFSEL2, 7, none, NONE, 0), + WPCM450_PINCFG(72, fi8, MFSEL2, 8, none, NONE, 0), + WPCM450_PINCFG(73, fi9, MFSEL2, 9, none, NONE, 0), + WPCM450_PINCFG(74, fi10, MFSEL2, 10, none, NONE, 0), + WPCM450_PINCFG(75, fi11, MFSEL2, 11, none, NONE, 0), + WPCM450_PINCFG(76, fi12, MFSEL2, 12, none, NONE, 0), + WPCM450_PINCFG(77, fi13, MFSEL2, 13, none, NONE, 0), + WPCM450_PINCFG(78, fi14, MFSEL2, 14, none, NONE, 0), + WPCM450_PINCFG(79, fi15, MFSEL2, 15, none, NONE, 0), + WPCM450_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0), + WPCM450_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0), + WPCM450_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0), + WPCM450_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0), + WPCM450_PINCFG(84, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(85, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(86, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(87, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(88, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(89, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0), + WPCM450_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0), + WPCM450_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0), + WPCM450_PINCFG(93, kbcc, MFSEL1, 17, none, NONE, 0), + WPCM450_PINCFG(94, kbcc, MFSEL1, 17, none, NONE, 0), + WPCM450_PINCFG(95, none, NONE, 0, none, NONE, 0), + + WPCM450_PINCFG(96, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(97, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(98, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(99, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(100, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(101, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(102, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(103, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(104, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(105, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(106, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(107, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(108, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(109, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(110, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(111, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(112, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(113, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0), + WPCM450_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0), + WPCM450_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0), + WPCM450_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0), + WPCM450_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0), + WPCM450_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0), + WPCM450_PINCFG(120, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(121, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(122, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(123, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(124, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(125, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(126, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(127, none, NONE, 0, none, NONE, 0), /* DVO */ +}; + +#define WPCM450_PIN(n) PINCTRL_PIN(n, "gpio" #n) + +static const struct pinctrl_pin_desc wpcm450_pins[] = { + WPCM450_PIN(0), WPCM450_PIN(1), WPCM450_PIN(2), WPCM450_PIN(3), + WPCM450_PIN(4), WPCM450_PIN(5), WPCM450_PIN(6), WPCM450_PIN(7), + WPCM450_PIN(8), WPCM450_PIN(9), WPCM450_PIN(10), WPCM450_PIN(11), + WPCM450_PIN(12), WPCM450_PIN(13), WPCM450_PIN(14), WPCM450_PIN(15), + WPCM450_PIN(16), WPCM450_PIN(17), WPCM450_PIN(18), WPCM450_PIN(19), + WPCM450_PIN(20), WPCM450_PIN(21), WPCM450_PIN(22), WPCM450_PIN(23), + WPCM450_PIN(24), WPCM450_PIN(25), WPCM450_PIN(26), WPCM450_PIN(27), + WPCM450_PIN(28), WPCM450_PIN(29), WPCM450_PIN(30), WPCM450_PIN(31), + WPCM450_PIN(32), WPCM450_PIN(33), WPCM450_PIN(34), WPCM450_PIN(35), + WPCM450_PIN(36), WPCM450_PIN(37), WPCM450_PIN(38), WPCM450_PIN(39), + WPCM450_PIN(40), WPCM450_PIN(41), WPCM450_PIN(42), WPCM450_PIN(43), + WPCM450_PIN(44), WPCM450_PIN(45), WPCM450_PIN(46), WPCM450_PIN(47), + WPCM450_PIN(48), WPCM450_PIN(49), WPCM450_PIN(50), WPCM450_PIN(51), + WPCM450_PIN(52), WPCM450_PIN(53), WPCM450_PIN(54), WPCM450_PIN(55), + WPCM450_PIN(56), WPCM450_PIN(57), WPCM450_PIN(58), WPCM450_PIN(59), + WPCM450_PIN(60), WPCM450_PIN(61), WPCM450_PIN(62), WPCM450_PIN(63), + WPCM450_PIN(64), WPCM450_PIN(65), WPCM450_PIN(66), WPCM450_PIN(67), + WPCM450_PIN(68), WPCM450_PIN(69), WPCM450_PIN(70), WPCM450_PIN(71), + WPCM450_PIN(72), WPCM450_PIN(73), WPCM450_PIN(74), WPCM450_PIN(75), + WPCM450_PIN(76), WPCM450_PIN(77), WPCM450_PIN(78), WPCM450_PIN(79), + WPCM450_PIN(80), WPCM450_PIN(81), WPCM450_PIN(82), WPCM450_PIN(83), + WPCM450_PIN(84), WPCM450_PIN(85), WPCM450_PIN(86), WPCM450_PIN(87), + WPCM450_PIN(88), WPCM450_PIN(89), WPCM450_PIN(90), WPCM450_PIN(91), + WPCM450_PIN(92), WPCM450_PIN(93), WPCM450_PIN(94), WPCM450_PIN(95), + WPCM450_PIN(96), WPCM450_PIN(97), WPCM450_PIN(98), WPCM450_PIN(99), + WPCM450_PIN(100), WPCM450_PIN(101), WPCM450_PIN(102), WPCM450_PIN(103), + WPCM450_PIN(104), WPCM450_PIN(105), WPCM450_PIN(106), WPCM450_PIN(107), + WPCM450_PIN(108), WPCM450_PIN(109), WPCM450_PIN(110), WPCM450_PIN(111), + WPCM450_PIN(112), WPCM450_PIN(113), WPCM450_PIN(114), WPCM450_PIN(115), + WPCM450_PIN(116), WPCM450_PIN(117), WPCM450_PIN(118), WPCM450_PIN(119), + WPCM450_PIN(120), WPCM450_PIN(121), WPCM450_PIN(122), WPCM450_PIN(123), + WPCM450_PIN(124), WPCM450_PIN(125), WPCM450_PIN(126), WPCM450_PIN(127), +}; + +/* Enable mode in pin group */ +static void wpcm450_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, + int npins, int func) +{ + const struct wpcm450_pincfg *cfg; + int i; + + for (i = 0; i < npins; i++) { + cfg = &pincfg[pin[i]]; + if (func == fn_gpio || cfg->fn0 == func || cfg->fn1 == func) { + if (cfg->reg0) + regmap_update_bits(gcr_regmap, cfg->reg0, + BIT(cfg->bit0), + (cfg->fn0 == func) ? BIT(cfg->bit0) : 0); + if (cfg->reg1) + regmap_update_bits(gcr_regmap, cfg->reg1, + BIT(cfg->bit1), + (cfg->fn1 == func) ? BIT(cfg->bit1) : 0); + } + } +} + +static int wpcm450_get_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(wpcm450_groups); +} + +static const char *wpcm450_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return wpcm450_groups[selector].name; +} + +static int wpcm450_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *npins) +{ + *npins = wpcm450_groups[selector].num_pins; + *pins = wpcm450_groups[selector].pins; + + return 0; +} + +static int wpcm450_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + u32 *num_maps) +{ + return pinconf_generic_dt_node_to_map(pctldev, np_config, + map, num_maps, + PIN_MAP_TYPE_INVALID); +} + +static void wpcm450_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, u32 num_maps) +{ + kfree(map); +} + +static const struct pinctrl_ops wpcm450_pinctrl_ops = { + .get_groups_count = wpcm450_get_groups_count, + .get_group_name = wpcm450_get_group_name, + .get_group_pins = wpcm450_get_group_pins, + .dt_node_to_map = wpcm450_dt_node_to_map, + .dt_free_map = wpcm450_dt_free_map, +}; + +static int wpcm450_get_functions_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(wpcm450_funcs); +} + +static const char *wpcm450_get_function_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + return wpcm450_funcs[function].name; +} + +static int wpcm450_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char * const **groups, + unsigned int * const ngroups) +{ + *ngroups = wpcm450_funcs[function].ngroups; + *groups = wpcm450_funcs[function].groups; + + return 0; +} + +static int wpcm450_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, + unsigned int group) +{ + struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + wpcm450_setfunc(pctrl->gcr_regmap, wpcm450_groups[group].pins, + wpcm450_groups[group].num_pins, function); + + return 0; +} + +static const struct pinmux_ops wpcm450_pinmux_ops = { + .get_functions_count = wpcm450_get_functions_count, + .get_function_name = wpcm450_get_function_name, + .get_function_groups = wpcm450_get_function_groups, + .set_mux = wpcm450_pinmux_set_mux, +}; + +static int debounce_bitnum(int gpio) +{ + if (gpio >= 0 && gpio < 16) + return gpio; + return -EINVAL; +} + +static int wpcm450_config_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + unsigned long flags; + int bit; + u32 reg; + + switch (param) { + case PIN_CONFIG_INPUT_DEBOUNCE: + bit = debounce_bitnum(pin); + if (bit < 0) + return bit; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + *config = pinconf_to_config_packed(param, !!(reg & BIT(bit))); + return 0; + default: + return -ENOTSUPP; + } +} + +static int wpcm450_config_set_one(struct wpcm450_pinctrl *pctrl, + unsigned int pin, unsigned long config) +{ + enum pin_config_param param = pinconf_to_config_param(config); + unsigned long flags; + unsigned long reg; + int bit; + int arg; + + switch (param) { + case PIN_CONFIG_INPUT_DEBOUNCE: + bit = debounce_bitnum(pin); + if (bit < 0) + return bit; + + arg = pinconf_to_config_argument(config); + + raw_spin_lock_irqsave(&pctrl->lock, flags); + reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC); + __assign_bit(bit, ®, arg); + iowrite32(reg, pctrl->gpio_base + WPCM450_GPEVDBNC); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + return 0; + default: + return -ENOTSUPP; + } +} + +static int wpcm450_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + int ret; + + while (num_configs--) { + ret = wpcm450_config_set_one(pctrl, pin, *configs++); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinconf_ops wpcm450_pinconf_ops = { + .is_generic = true, + .pin_config_get = wpcm450_config_get, + .pin_config_set = wpcm450_config_set, +}; + +static struct pinctrl_desc wpcm450_pinctrl_desc = { + .name = "wpcm450-pinctrl", + .pins = wpcm450_pins, + .npins = ARRAY_SIZE(wpcm450_pins), + .pctlops = &wpcm450_pinctrl_ops, + .pmxops = &wpcm450_pinmux_ops, + .confops = &wpcm450_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int wpcm450_gpio_set_config(struct gpio_chip *chip, + unsigned int offset, unsigned long config) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(chip); + + return wpcm450_config_set_one(gpio->pctrl, offset, config); +} + +static int wpcm450_gpio_add_pin_ranges(struct gpio_chip *chip) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(chip); + const struct wpcm450_bank *bank = gpio->bank; + + return gpiochip_add_pin_range(&gpio->gc, dev_name(gpio->pctrl->dev), + 0, bank->base, bank->length); +} + +static int wpcm450_gpio_register(struct platform_device *pdev, + struct wpcm450_pinctrl *pctrl) +{ + struct device *dev = &pdev->dev; + struct fwnode_handle *child; + int ret; + + pctrl->gpio_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pctrl->gpio_base)) + return dev_err_probe(dev, PTR_ERR(pctrl->gpio_base), + "Resource fail for GPIO controller\n"); + + device_for_each_child_node(dev, child) { + void __iomem *dat = NULL; + void __iomem *set = NULL; + void __iomem *dirout = NULL; + unsigned long flags = 0; + const struct wpcm450_bank *bank; + struct wpcm450_gpio *gpio; + struct gpio_irq_chip *girq; + u32 reg; + int i; + + if (!fwnode_property_read_bool(child, "gpio-controller")) + continue; + + ret = fwnode_property_read_u32(child, "reg", ®); + if (ret < 0) + return ret; + + gpio = &pctrl->gpio_bank[reg]; + gpio->pctrl = pctrl; + + if (reg >= WPCM450_NUM_BANKS) + return dev_err_probe(dev, -EINVAL, + "GPIO index %d out of range!\n", reg); + + bank = &wpcm450_banks[reg]; + gpio->bank = bank; + + dat = pctrl->gpio_base + bank->datain; + if (bank->dataout) { + set = pctrl->gpio_base + bank->dataout; + dirout = pctrl->gpio_base + bank->cfg0; + } else { + flags = BGPIOF_NO_OUTPUT; + } + ret = bgpio_init(&gpio->gc, dev, 4, + dat, set, NULL, dirout, NULL, flags); + if (ret < 0) + return dev_err_probe(dev, ret, "GPIO initialization failed\n"); + + gpio->gc.ngpio = bank->length; + gpio->gc.set_config = wpcm450_gpio_set_config; + gpio->gc.fwnode = child; + gpio->gc.add_pin_ranges = wpcm450_gpio_add_pin_ranges; + + gpio->irqc = wpcm450_gpio_irqchip; + girq = &gpio->gc.irq; + girq->chip = &gpio->irqc; + girq->parent_handler = wpcm450_gpio_irqhandler; + girq->parents = devm_kcalloc(dev, WPCM450_NUM_GPIO_IRQS, + sizeof(*girq->parents), GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + + girq->num_parents = 0; + for (i = 0; i < WPCM450_NUM_GPIO_IRQS; i++) { + int irq = fwnode_irq_get(child, i); + + if (irq < 0) + break; + + girq->parents[i] = irq; + girq->num_parents++; + } + + ret = devm_gpiochip_add_data(dev, &gpio->gc, gpio); + if (ret) + return dev_err_probe(dev, ret, "Failed to add GPIO chip\n"); + } + + return 0; +} + +static int wpcm450_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct wpcm450_pinctrl *pctrl; + int ret; + + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->dev = &pdev->dev; + raw_spin_lock_init(&pctrl->lock); + dev_set_drvdata(dev, pctrl); + + pctrl->gcr_regmap = + syscon_regmap_lookup_by_compatible("nuvoton,wpcm450-gcr"); + if (IS_ERR(pctrl->gcr_regmap)) + return dev_err_probe(dev, PTR_ERR(pctrl->gcr_regmap), + "Failed to find nuvoton,wpcm450-gcr\n"); + + pctrl->pctldev = devm_pinctrl_register(dev, + &wpcm450_pinctrl_desc, pctrl); + if (IS_ERR(pctrl->pctldev)) + return dev_err_probe(dev, PTR_ERR(pctrl->pctldev), + "Failed to register pinctrl device\n"); + + ret = wpcm450_gpio_register(pdev, pctrl); + if (ret < 0) + return ret; + + return 0; +} + +static const struct of_device_id wpcm450_pinctrl_match[] = { + { .compatible = "nuvoton,wpcm450-pinctrl" }, + { } +}; +MODULE_DEVICE_TABLE(of, wpcm450_pinctrl_match); + +static struct platform_driver wpcm450_pinctrl_driver = { + .probe = wpcm450_pinctrl_probe, + .driver = { + .name = "wpcm450-pinctrl", + .of_match_table = wpcm450_pinctrl_match, + }, +}; +module_platform_driver(wpcm450_pinctrl_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Jonathan Neuschäfer <j.neuschaefer@gmx.net>"); +MODULE_DESCRIPTION("Nuvoton WPCM450 Pinctrl and GPIO driver"); diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index f8edcc88ac01..415d1df8f46a 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -30,10 +30,10 @@ static const struct pin_config_item conf_items[] = { PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL, false), PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL, false), PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL, false), - PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL, false), + PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", "ohms", true), PCONFDUMP(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, - "input bias pull to pin specific state", NULL, false), - PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL, false), + "input bias pull to pin specific state", "ohms", true), + PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", "ohms", true), PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL, false), PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL, false), PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL, false), diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index fafd1f55cba7..517f2a6330ad 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -1045,7 +1045,6 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) const char **group_names; const struct of_device_id *match; int i, ret; - struct resource *res; struct atmel_pioctrl *atmel_pioctrl; const struct atmel_pioctrl_data *atmel_pioctrl_data; @@ -1164,16 +1163,15 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) /* There is one controller but each bank has its own irq line. */ for (i = 0; i < atmel_pioctrl->nbanks; i++) { - res = platform_get_resource(pdev, IORESOURCE_IRQ, i); - if (!res) { - dev_err(dev, "missing irq resource for group %c\n", + ret = platform_get_irq(pdev, i); + if (ret < 0) { + dev_dbg(dev, "missing irq resource for group %c\n", 'A' + i); - return -EINVAL; + return ret; } - atmel_pioctrl->irqs[i] = res->start; - irq_set_chained_handler_and_data(res->start, - atmel_gpio_irq_handler, atmel_pioctrl); - dev_dbg(dev, "bank %i: irq=%pr\n", i, res); + atmel_pioctrl->irqs[i] = ret; + irq_set_chained_handler_and_data(ret, atmel_gpio_irq_handler, atmel_pioctrl); + dev_dbg(dev, "bank %i: irq=%d\n", i, ret); } atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node, diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 2712f51eb238..fa6becca1788 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -119,6 +119,8 @@ struct ingenic_chip_info { unsigned int num_functions; const u32 *pull_ups, *pull_downs; + + const struct regmap_access_table *access_table; }; struct ingenic_pinctrl { @@ -2179,6 +2181,17 @@ static const struct function_desc x1000_functions[] = { { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), }, }; +static const struct regmap_range x1000_access_ranges[] = { + regmap_reg_range(0x000, 0x400 - 4), + regmap_reg_range(0x700, 0x800 - 4), +}; + +/* shared with X1500 */ +static const struct regmap_access_table x1000_access_table = { + .yes_ranges = x1000_access_ranges, + .n_yes_ranges = ARRAY_SIZE(x1000_access_ranges), +}; + static const struct ingenic_chip_info x1000_chip_info = { .num_chips = 4, .reg_offset = 0x100, @@ -2189,6 +2202,7 @@ static const struct ingenic_chip_info x1000_chip_info = { .num_functions = ARRAY_SIZE(x1000_functions), .pull_ups = x1000_pull_ups, .pull_downs = x1000_pull_downs, + .access_table = &x1000_access_table, }; static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; @@ -2300,6 +2314,7 @@ static const struct ingenic_chip_info x1500_chip_info = { .num_functions = ARRAY_SIZE(x1500_functions), .pull_ups = x1000_pull_ups, .pull_downs = x1000_pull_downs, + .access_table = &x1000_access_table, }; static const u32 x1830_pull_ups[4] = { @@ -2506,6 +2521,16 @@ static const struct function_desc x1830_functions[] = { { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), }, }; +static const struct regmap_range x1830_access_ranges[] = { + regmap_reg_range(0x0000, 0x4000 - 4), + regmap_reg_range(0x7000, 0x8000 - 4), +}; + +static const struct regmap_access_table x1830_access_table = { + .yes_ranges = x1830_access_ranges, + .n_yes_ranges = ARRAY_SIZE(x1830_access_ranges), +}; + static const struct ingenic_chip_info x1830_chip_info = { .num_chips = 4, .reg_offset = 0x1000, @@ -2516,6 +2541,7 @@ static const struct ingenic_chip_info x1830_chip_info = { .num_functions = ARRAY_SIZE(x1830_functions), .pull_ups = x1830_pull_ups, .pull_downs = x1830_pull_downs, + .access_table = &x1830_access_table, }; static const u32 x2000_pull_ups[5] = { @@ -2969,6 +2995,17 @@ static const struct function_desc x2000_functions[] = { { "otg", x2000_otg_groups, ARRAY_SIZE(x2000_otg_groups), }, }; +static const struct regmap_range x2000_access_ranges[] = { + regmap_reg_range(0x000, 0x500 - 4), + regmap_reg_range(0x700, 0x800 - 4), +}; + +/* shared with X2100 */ +static const struct regmap_access_table x2000_access_table = { + .yes_ranges = x2000_access_ranges, + .n_yes_ranges = ARRAY_SIZE(x2000_access_ranges), +}; + static const struct ingenic_chip_info x2000_chip_info = { .num_chips = 5, .reg_offset = 0x100, @@ -2979,6 +3016,7 @@ static const struct ingenic_chip_info x2000_chip_info = { .num_functions = ARRAY_SIZE(x2000_functions), .pull_ups = x2000_pull_ups, .pull_downs = x2000_pull_downs, + .access_table = &x2000_access_table, }; static const u32 x2100_pull_ups[5] = { @@ -3189,6 +3227,7 @@ static const struct ingenic_chip_info x2100_chip_info = { .num_functions = ARRAY_SIZE(x2100_functions), .pull_ups = x2100_pull_ups, .pull_downs = x2100_pull_downs, + .access_table = &x2000_access_table, }; static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) @@ -4168,7 +4207,12 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) return PTR_ERR(base); regmap_config = ingenic_pinctrl_regmap_config; - regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset; + if (chip_info->access_table) { + regmap_config.rd_table = chip_info->access_table; + regmap_config.wr_table = chip_info->access_table; + } else { + regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset - 4; + } jzpc->map = devm_regmap_init_mmio(dev, base, ®map_config); if (IS_ERR(jzpc->map)) { diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c index 639f1130e989..80a8939ad0c0 100644 --- a/drivers/pinctrl/pinctrl-microchip-sgpio.c +++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c @@ -19,6 +19,7 @@ #include <linux/property.h> #include <linux/regmap.h> #include <linux/reset.h> +#include <linux/spinlock.h> #include "core.h" #include "pinconf.h" @@ -63,11 +64,13 @@ struct sgpio_properties { #define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0) #define SGPIO_OCELOT_AUTO_REPEAT BIT(10) +#define SGPIO_OCELOT_SINGLE_SHOT BIT(11) #define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7) #define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8) #define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12) #define SGPIO_SPARX5_AUTO_REPEAT BIT(6) +#define SGPIO_SPARX5_SINGLE_SHOT BIT(7) #define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3) #define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8) #define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12) @@ -116,6 +119,9 @@ struct sgpio_priv { u32 clock; struct regmap *regs; const struct sgpio_properties *properties; + spinlock_t lock; + /* protects the config register and single shot mode */ + struct mutex poll_lock; }; struct sgpio_port_addr { @@ -166,12 +172,11 @@ static void sgpio_writel(struct sgpio_priv *priv, static inline void sgpio_clrsetbits(struct sgpio_priv *priv, u32 rno, u32 off, u32 clear, u32 set) { - u32 val = sgpio_readl(priv, rno, off); - - val &= ~clear; - val |= set; + u32 addr = sgpio_get_addr(priv, rno, off); + int ret; - sgpio_writel(priv, val, rno, off); + ret = regmap_update_bits(priv->regs, addr, clear | set, set); + WARN_ONCE(ret, "error updating sgpio reg %d\n", ret); } static inline void sgpio_configure_bitstream(struct sgpio_priv *priv) @@ -224,12 +229,64 @@ static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq) sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set); } -static void sgpio_output_set(struct sgpio_priv *priv, - struct sgpio_port_addr *addr, - int value) +static int sgpio_single_shot(struct sgpio_priv *priv) +{ + u32 addr = sgpio_get_addr(priv, REG_SIO_CONFIG, 0); + int ret, ret2; + u32 ctrl; + unsigned int single_shot; + unsigned int auto_repeat; + + switch (priv->properties->arch) { + case SGPIO_ARCH_LUTON: + /* not supported for now */ + return 0; + case SGPIO_ARCH_OCELOT: + single_shot = SGPIO_OCELOT_SINGLE_SHOT; + auto_repeat = SGPIO_OCELOT_AUTO_REPEAT; + break; + case SGPIO_ARCH_SPARX5: + single_shot = SGPIO_SPARX5_SINGLE_SHOT; + auto_repeat = SGPIO_SPARX5_AUTO_REPEAT; + break; + default: + return -EINVAL; + } + + /* + * Trigger immediate burst. This only works when auto repeat is turned + * off. Otherwise, the single shot bit will never be cleared by the + * hardware. Measurements showed that an update might take as long as + * the burst gap. On a LAN9668 this is about 50ms for the largest + * setting. + * After the manual burst, reenable the auto repeat mode again. + */ + mutex_lock(&priv->poll_lock); + ret = regmap_update_bits(priv->regs, addr, single_shot | auto_repeat, + single_shot); + if (ret) + goto out; + + ret = regmap_read_poll_timeout(priv->regs, addr, ctrl, + !(ctrl & single_shot), 100, 60000); + + /* reenable auto repeat mode even if there was an error */ + ret2 = regmap_update_bits(priv->regs, addr, auto_repeat, auto_repeat); +out: + mutex_unlock(&priv->poll_lock); + + return ret ?: ret2; +} + +static int sgpio_output_set(struct sgpio_priv *priv, + struct sgpio_port_addr *addr, + int value) { unsigned int bit = SGPIO_SRC_BITS * addr->bit; + u32 reg = sgpio_get_addr(priv, REG_PORT_CONFIG, addr->port); + bool changed; u32 clr, set; + int ret; switch (priv->properties->arch) { case SGPIO_ARCH_LUTON: @@ -245,9 +302,21 @@ static void sgpio_output_set(struct sgpio_priv *priv, set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit); break; default: - return; + return -EINVAL; } - sgpio_clrsetbits(priv, REG_PORT_CONFIG, addr->port, clr, set); + + ret = regmap_update_bits_check(priv->regs, reg, clr | set, set, + &changed); + if (ret) + return ret; + + if (changed) { + ret = sgpio_single_shot(priv); + if (ret) + return ret; + } + + return 0; } static int sgpio_output_get(struct sgpio_priv *priv, @@ -333,7 +402,7 @@ static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, case PIN_CONFIG_OUTPUT: if (bank->is_input) return -EINVAL; - sgpio_output_set(priv, &addr, arg); + err = sgpio_output_set(priv, &addr, arg); break; default: @@ -473,9 +542,7 @@ static int microchip_sgpio_direction_output(struct gpio_chip *gc, sgpio_pin_to_addr(priv, gpio, &addr); - sgpio_output_set(priv, &addr, value); - - return 0; + return sgpio_output_set(priv, &addr, value); } static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio) @@ -575,10 +642,13 @@ static void microchip_sgpio_irq_settype(struct irq_data *data, struct sgpio_bank *bank = gpiochip_get_data(chip); unsigned int gpio = irqd_to_hwirq(data); struct sgpio_port_addr addr; + unsigned long flags; u32 ena; sgpio_pin_to_addr(bank->priv, gpio, &addr); + spin_lock_irqsave(&bank->priv->lock, flags); + /* Disable interrupt while changing type */ ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit); sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit); @@ -595,6 +665,8 @@ static void microchip_sgpio_irq_settype(struct irq_data *data, /* Possibly re-enable interrupts */ sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit); + + spin_unlock_irqrestore(&bank->priv->lock, flags); } static void microchip_sgpio_irq_setreg(struct irq_data *data, @@ -626,7 +698,14 @@ static void microchip_sgpio_irq_unmask(struct irq_data *data) static void microchip_sgpio_irq_ack(struct irq_data *data) { - microchip_sgpio_irq_setreg(data, REG_INT_ACK, false); + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + struct sgpio_bank *bank = gpiochip_get_data(chip); + unsigned int gpio = irqd_to_hwirq(data); + struct sgpio_port_addr addr; + + sgpio_pin_to_addr(bank->priv, gpio, &addr); + + sgpio_writel(bank->priv, BIT(addr.port), REG_INT_ACK, addr.bit); } static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type) @@ -774,6 +853,7 @@ static int microchip_sgpio_register_bank(struct device *dev, gc->of_gpio_n_cells = 3; gc->base = -1; gc->ngpio = ngpios; + gc->can_sleep = !bank->is_input; if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) { int irq = fwnode_irq_get(fwnode, 0); @@ -833,6 +913,8 @@ static int microchip_sgpio_probe(struct platform_device *pdev) return -ENOMEM; priv->dev = dev; + spin_lock_init(&priv->lock); + mutex_init(&priv->poll_lock); reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); if (IS_ERR(reset)) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index fc969208d904..003fb0e34153 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -695,6 +695,98 @@ static const struct pinctrl_pin_desc jaguar2_pins[] = { JAGUAR2_PIN(63), }; +#define SERVALT_P(p, f0, f1, f2) \ +static struct ocelot_pin_caps servalt_pin_##p = { \ + .pin = p, \ + .functions = { \ + FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ + }, \ +} + +SERVALT_P(0, SG0, NONE, NONE); +SERVALT_P(1, SG0, NONE, NONE); +SERVALT_P(2, SG0, NONE, NONE); +SERVALT_P(3, SG0, NONE, NONE); +SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); +SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M); +SERVALT_P(6, UART, NONE, NONE); +SERVALT_P(7, UART, NONE, NONE); +SERVALT_P(8, SI, SFP, TWI_SCL_M); +SERVALT_P(9, PCI_WAKE, SFP, SI); +SERVALT_P(10, PTP0, SFP, TWI_SCL_M); +SERVALT_P(11, PTP1, SFP, TWI_SCL_M); +SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M); +SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M); +SERVALT_P(14, REF_CLK, IRQ0_OUT, SI); +SERVALT_P(15, REF_CLK, IRQ1_OUT, SI); +SERVALT_P(16, TACHO, SFP, SI); +SERVALT_P(17, PWM, NONE, TWI_SCL_M); +SERVALT_P(18, PTP2, SFP, SI); +SERVALT_P(19, PTP3, SFP, SI); +SERVALT_P(20, UART2, SFP, SI); +SERVALT_P(21, UART2, NONE, NONE); +SERVALT_P(22, MIIM, SFP, TWI2); +SERVALT_P(23, MIIM, SFP, TWI2); +SERVALT_P(24, TWI, NONE, NONE); +SERVALT_P(25, TWI, SFP, TWI_SCL_M); +SERVALT_P(26, TWI_SCL_M, SFP, SI); +SERVALT_P(27, TWI_SCL_M, SFP, SI); +SERVALT_P(28, TWI_SCL_M, SFP, SI); +SERVALT_P(29, TWI_SCL_M, NONE, NONE); +SERVALT_P(30, TWI_SCL_M, NONE, NONE); +SERVALT_P(31, TWI_SCL_M, NONE, NONE); +SERVALT_P(32, TWI_SCL_M, NONE, NONE); +SERVALT_P(33, RCVRD_CLK, NONE, NONE); +SERVALT_P(34, RCVRD_CLK, NONE, NONE); +SERVALT_P(35, RCVRD_CLK, NONE, NONE); +SERVALT_P(36, RCVRD_CLK, NONE, NONE); + +#define SERVALT_PIN(n) { \ + .number = n, \ + .name = "GPIO_"#n, \ + .drv_data = &servalt_pin_##n \ +} + +static const struct pinctrl_pin_desc servalt_pins[] = { + SERVALT_PIN(0), + SERVALT_PIN(1), + SERVALT_PIN(2), + SERVALT_PIN(3), + SERVALT_PIN(4), + SERVALT_PIN(5), + SERVALT_PIN(6), + SERVALT_PIN(7), + SERVALT_PIN(8), + SERVALT_PIN(9), + SERVALT_PIN(10), + SERVALT_PIN(11), + SERVALT_PIN(12), + SERVALT_PIN(13), + SERVALT_PIN(14), + SERVALT_PIN(15), + SERVALT_PIN(16), + SERVALT_PIN(17), + SERVALT_PIN(18), + SERVALT_PIN(19), + SERVALT_PIN(20), + SERVALT_PIN(21), + SERVALT_PIN(22), + SERVALT_PIN(23), + SERVALT_PIN(24), + SERVALT_PIN(25), + SERVALT_PIN(26), + SERVALT_PIN(27), + SERVALT_PIN(28), + SERVALT_PIN(29), + SERVALT_PIN(30), + SERVALT_PIN(31), + SERVALT_PIN(32), + SERVALT_PIN(33), + SERVALT_PIN(34), + SERVALT_PIN(35), + SERVALT_PIN(36), +}; + #define SPARX5_P(p, f0, f1, f2) \ static struct ocelot_pin_caps sparx5_pin_##p = { \ .pin = p, \ @@ -1497,6 +1589,15 @@ static struct pinctrl_desc jaguar2_desc = { .owner = THIS_MODULE, }; +static struct pinctrl_desc servalt_desc = { + .name = "servalt-pinctrl", + .pins = servalt_pins, + .npins = ARRAY_SIZE(servalt_pins), + .pctlops = &ocelot_pctl_ops, + .pmxops = &ocelot_pmx_ops, + .owner = THIS_MODULE, +}; + static struct pinctrl_desc sparx5_desc = { .name = "sparx5-pinctrl", .pins = sparx5_pins, @@ -1750,8 +1851,8 @@ static int ocelot_gpiochip_register(struct platform_device *pdev, gc->base = -1; gc->label = "ocelot-gpio"; - irq = irq_of_parse_and_map(gc->of_node, 0); - if (irq) { + irq = platform_get_irq_optional(pdev, 0); + if (irq > 0) { girq = &gc->irq; girq->chip = &ocelot_irqchip; girq->parent_handler = ocelot_irq_handler; @@ -1774,6 +1875,7 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = { { .compatible = "mscc,serval-pinctrl", .data = &serval_desc }, { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, + { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc }, { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, {}, @@ -1788,9 +1890,10 @@ static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev) .val_bits = 32, .reg_stride = 4, .max_register = 32, + .name = "pincfg", }; - base = devm_platform_ioremap_resource(pdev, 0); + base = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(base)) { dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n"); return NULL; diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index d8dd8415fa81..a1b598b86aa9 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2693,6 +2693,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) node = of_parse_phandle(np, "rockchip,grf", 0); if (node) { info->regmap_base = syscon_node_to_regmap(node); + of_node_put(node); if (IS_ERR(info->regmap_base)) return PTR_ERR(info->regmap_base); } else { @@ -2725,6 +2726,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) node = of_parse_phandle(np, "rockchip,pmu", 0); if (node) { info->regmap_pmu = syscon_node_to_regmap(node); + of_node_put(node); if (IS_ERR(info->regmap_pmu)) return PTR_ERR(info->regmap_pmu); } diff --git a/drivers/pinctrl/pinctrl-starfive.c b/drivers/pinctrl/pinctrl-starfive.c index ab4b2ee9f217..c586cfd09fa8 100644 --- a/drivers/pinctrl/pinctrl-starfive.c +++ b/drivers/pinctrl/pinctrl-starfive.c @@ -1026,7 +1026,7 @@ static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio, break; default: return -ENOTSUPP; - }; + } starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value); return 0; diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index a96af8a76a7a..0e8de27d0de8 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -8,6 +8,7 @@ */ #include <linux/io.h> #include <linux/mfd/syscon.h> +#include <linux/module.h> #include <linux/init.h> #include <linux/of.h> #include <linux/platform_device.h> @@ -1210,8 +1211,4 @@ static struct platform_driver zynq_pinctrl_driver = { .probe = zynq_pinctrl_probe, }; -static int __init zynq_pinctrl_init(void) -{ - return platform_driver_register(&zynq_pinctrl_driver); -} -arch_initcall(zynq_pinctrl_init); +module_platform_driver(zynq_pinctrl_driver); diff --git a/drivers/pinctrl/pxa/pinctrl-pxa27x.c b/drivers/pinctrl/pxa/pinctrl-pxa27x.c index 48ccfb50b23e..ff9302e4803a 100644 --- a/drivers/pinctrl/pxa/pinctrl-pxa27x.c +++ b/drivers/pinctrl/pxa/pinctrl-pxa27x.c @@ -504,7 +504,7 @@ static const struct pxa_desc_pin pxa27x_pins[] = { static int pxa27x_pinctrl_probe(struct platform_device *pdev) { - int ret, i; + int i; void __iomem *base_af[8]; void __iomem *base_dir[4]; void __iomem *base_sleep[4]; @@ -532,9 +532,8 @@ static int pxa27x_pinctrl_probe(struct platform_device *pdev) for (i = 0; i < ARRAY_SIZE(base_sleep); i++) base_sleep[i] = base_sleep[0] + sizeof(base_af[0]) * i; - ret = pxa2xx_pinctrl_init(pdev, pxa27x_pins, ARRAY_SIZE(pxa27x_pins), + return pxa2xx_pinctrl_init(pdev, pxa27x_pins, ARRAY_SIZE(pxa27x_pins), base_af, base_dir, base_sleep); - return ret; } static const struct of_device_id pxa27x_pinctrl_match[] = { diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index ca6f68a061a8..c51ef54a9f61 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -248,6 +248,15 @@ config PINCTRL_SC8180X Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SC8180x platform. +config PINCTRL_SC8280XP + tristate "Qualcomm Technologies Inc SC8280xp pin controller driver" + depends on OF + depends on PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SC8280xp platform. + config PINCTRL_SDM660 tristate "Qualcomm Technologies Inc SDM660 pin controller driver" depends on OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 709882f54d25..5efbfd9f6248 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o +obj-$(CONFIG_PINCTRL_SC8280XP) += pinctrl-sc8280xp.o obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 780878dede9e..966ea6622ff3 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -615,6 +615,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, int drive; int pull; int val; + int egpio_enable; u32 ctl_reg, io_reg; static const char * const pulls_keeper[] = { @@ -641,12 +642,20 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, func = (ctl_reg >> g->mux_bit) & 7; drive = (ctl_reg >> g->drv_bit) & 7; pull = (ctl_reg >> g->pull_bit) & 3; + egpio_enable = 0; + if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present)) + egpio_enable = !(ctl_reg & BIT(g->egpio_enable)); if (is_out) val = !!(io_reg & BIT(g->out_bit)); else val = !!(io_reg & BIT(g->in_bit)); + if (egpio_enable) { + seq_printf(s, " %-8s: egpio\n", g->name); + return; + } + seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in"); seq_printf(s, " %-4s func%d", val ? "high" : "low", func); seq_printf(s, " %dmA", msm_regval_to_drive(drive)); @@ -1168,7 +1177,7 @@ static int msm_gpio_irq_set_affinity(struct irq_data *d, if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) return irq_chip_set_affinity_parent(d, dest, force); - return 0; + return -EINVAL; } static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) @@ -1179,7 +1188,7 @@ static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) return irq_chip_set_vcpu_affinity_parent(d, vcpu_info); - return 0; + return -EINVAL; } static void msm_gpio_irq_handler(struct irq_desc *desc) diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c b/drivers/pinctrl/qcom/pinctrl-qcm2290.c index 3f05c0a24b79..aa9325f333fb 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcm2290.c +++ b/drivers/pinctrl/qcom/pinctrl-qcm2290.c @@ -1083,6 +1083,16 @@ static const struct msm_pingroup qcm2290_groups[] = { [133] = SDC_QDSD_PINGROUP(sdc2_data, 0x86000, 9, 0), }; +static const struct msm_gpio_wakeirq_map qcm2290_mpm_map[] = { + { 0, 84 }, { 3, 75 }, { 4, 16 }, { 6, 59 }, { 8, 63 }, { 11, 17 }, + { 13, 18 }, { 14, 51 }, { 17, 20 }, { 18, 52 }, { 19, 53 }, { 24, 6 }, + { 25, 71 }, { 27, 73 }, { 28, 41 }, { 31, 27 }, { 32, 54 }, { 33, 55 }, + { 34, 56 }, { 35, 57 }, { 36, 58 }, { 39, 28 }, { 46, 29 }, { 62, 60 }, + { 63, 61 }, { 64, 62 }, { 69, 33 }, { 70, 34 }, { 72, 72 }, { 75, 35 }, + { 79, 36 }, { 80, 21 }, { 81, 38 }, { 86, 19 }, { 87, 42 }, { 88, 43 }, + { 89, 45 }, { 91, 74 }, { 94, 47 }, { 95, 48 }, { 96, 49 }, { 97, 50 }, +}; + static const struct msm_pinctrl_soc_data qcm2290_pinctrl = { .pins = qcm2290_pins, .npins = ARRAY_SIZE(qcm2290_pins), @@ -1091,6 +1101,8 @@ static const struct msm_pinctrl_soc_data qcm2290_pinctrl = { .groups = qcm2290_groups, .ngroups = ARRAY_SIZE(qcm2290_groups), .ngpios = 127, + .wakeirq_map = qcm2290_mpm_map, + .nwakeirq_map = ARRAY_SIZE(qcm2290_mpm_map), }; static int qcm2290_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/qcom/pinctrl-sc8180x.c b/drivers/pinctrl/qcom/pinctrl-sc8180x.c index 0d9654b4ab60..6bec7f143134 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8180x.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8180x.c @@ -1622,8 +1622,8 @@ static const struct msm_pinctrl_soc_data sc8180x_acpi_pinctrl = { }; /* - * ACPI DSDT has one single memory resource for TLMM, which voilates the - * hardware layout of 3 sepearte tiles. Let's split the memory resource into + * ACPI DSDT has one single memory resource for TLMM, which violates the + * hardware layout of 3 separate tiles. Let's split the memory resource into * 3 named ones, so that msm_pinctrl_probe() can map memory for ACPI in the * same way as for DT probe. */ diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp.c b/drivers/pinctrl/qcom/pinctrl-sc8280xp.c new file mode 100644 index 000000000000..aa2075390f3e --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp.c @@ -0,0 +1,1953 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Ltd. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + }, \ + .nfuncs = 8, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc sc8280xp_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(184, "GPIO_184"), + PINCTRL_PIN(185, "GPIO_185"), + PINCTRL_PIN(186, "GPIO_186"), + PINCTRL_PIN(187, "GPIO_187"), + PINCTRL_PIN(188, "GPIO_188"), + PINCTRL_PIN(189, "GPIO_189"), + PINCTRL_PIN(190, "GPIO_190"), + PINCTRL_PIN(191, "GPIO_191"), + PINCTRL_PIN(192, "GPIO_192"), + PINCTRL_PIN(193, "GPIO_193"), + PINCTRL_PIN(194, "GPIO_194"), + PINCTRL_PIN(195, "GPIO_195"), + PINCTRL_PIN(196, "GPIO_196"), + PINCTRL_PIN(197, "GPIO_197"), + PINCTRL_PIN(198, "GPIO_198"), + PINCTRL_PIN(199, "GPIO_199"), + PINCTRL_PIN(200, "GPIO_200"), + PINCTRL_PIN(201, "GPIO_201"), + PINCTRL_PIN(202, "GPIO_202"), + PINCTRL_PIN(203, "GPIO_203"), + PINCTRL_PIN(204, "GPIO_204"), + PINCTRL_PIN(205, "GPIO_205"), + PINCTRL_PIN(206, "GPIO_206"), + PINCTRL_PIN(207, "GPIO_207"), + PINCTRL_PIN(208, "GPIO_208"), + PINCTRL_PIN(209, "GPIO_209"), + PINCTRL_PIN(210, "GPIO_210"), + PINCTRL_PIN(211, "GPIO_211"), + PINCTRL_PIN(212, "GPIO_212"), + PINCTRL_PIN(213, "GPIO_213"), + PINCTRL_PIN(214, "GPIO_214"), + PINCTRL_PIN(215, "GPIO_215"), + PINCTRL_PIN(216, "GPIO_216"), + PINCTRL_PIN(217, "GPIO_217"), + PINCTRL_PIN(218, "GPIO_218"), + PINCTRL_PIN(219, "GPIO_219"), + PINCTRL_PIN(220, "GPIO_220"), + PINCTRL_PIN(221, "GPIO_221"), + PINCTRL_PIN(222, "GPIO_222"), + PINCTRL_PIN(223, "GPIO_223"), + PINCTRL_PIN(224, "GPIO_224"), + PINCTRL_PIN(225, "GPIO_225"), + PINCTRL_PIN(226, "GPIO_226"), + PINCTRL_PIN(227, "GPIO_227"), + PINCTRL_PIN(228, "UFS_RESET"), + PINCTRL_PIN(229, "UFS1_RESET"), + PINCTRL_PIN(230, "SDC2_CLK"), + PINCTRL_PIN(231, "SDC2_CMD"), + PINCTRL_PIN(232, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); +DECLARE_MSM_GPIO_PINS(181); +DECLARE_MSM_GPIO_PINS(182); +DECLARE_MSM_GPIO_PINS(183); +DECLARE_MSM_GPIO_PINS(184); +DECLARE_MSM_GPIO_PINS(185); +DECLARE_MSM_GPIO_PINS(186); +DECLARE_MSM_GPIO_PINS(187); +DECLARE_MSM_GPIO_PINS(188); +DECLARE_MSM_GPIO_PINS(189); +DECLARE_MSM_GPIO_PINS(190); +DECLARE_MSM_GPIO_PINS(191); +DECLARE_MSM_GPIO_PINS(192); +DECLARE_MSM_GPIO_PINS(193); +DECLARE_MSM_GPIO_PINS(194); +DECLARE_MSM_GPIO_PINS(195); +DECLARE_MSM_GPIO_PINS(196); +DECLARE_MSM_GPIO_PINS(197); +DECLARE_MSM_GPIO_PINS(198); +DECLARE_MSM_GPIO_PINS(199); +DECLARE_MSM_GPIO_PINS(200); +DECLARE_MSM_GPIO_PINS(201); +DECLARE_MSM_GPIO_PINS(202); +DECLARE_MSM_GPIO_PINS(203); +DECLARE_MSM_GPIO_PINS(204); +DECLARE_MSM_GPIO_PINS(205); +DECLARE_MSM_GPIO_PINS(206); +DECLARE_MSM_GPIO_PINS(207); +DECLARE_MSM_GPIO_PINS(208); +DECLARE_MSM_GPIO_PINS(209); +DECLARE_MSM_GPIO_PINS(210); +DECLARE_MSM_GPIO_PINS(211); +DECLARE_MSM_GPIO_PINS(212); +DECLARE_MSM_GPIO_PINS(213); +DECLARE_MSM_GPIO_PINS(214); +DECLARE_MSM_GPIO_PINS(215); +DECLARE_MSM_GPIO_PINS(216); +DECLARE_MSM_GPIO_PINS(217); +DECLARE_MSM_GPIO_PINS(218); +DECLARE_MSM_GPIO_PINS(219); +DECLARE_MSM_GPIO_PINS(220); +DECLARE_MSM_GPIO_PINS(221); +DECLARE_MSM_GPIO_PINS(222); +DECLARE_MSM_GPIO_PINS(223); +DECLARE_MSM_GPIO_PINS(224); +DECLARE_MSM_GPIO_PINS(225); +DECLARE_MSM_GPIO_PINS(226); +DECLARE_MSM_GPIO_PINS(227); + +static const unsigned int ufs_reset_pins[] = { 228 }; +static const unsigned int ufs1_reset_pins[] = { 229 }; +static const unsigned int sdc2_clk_pins[] = { 230 }; +static const unsigned int sdc2_cmd_pins[] = { 231 }; +static const unsigned int sdc2_data_pins[] = { 232 }; + +enum sc8280xp_functions { + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ref, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cci_timer5, + msm_mux_cci_timer6, + msm_mux_cci_timer7, + msm_mux_cci_timer8, + msm_mux_cci_timer9, + msm_mux_cmu_rng, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_ddr_pxi4, + msm_mux_ddr_pxi5, + msm_mux_ddr_pxi6, + msm_mux_ddr_pxi7, + msm_mux_dp2_hot, + msm_mux_dp3_hot, + msm_mux_edp0_lcd, + msm_mux_edp1_lcd, + msm_mux_edp2_lcd, + msm_mux_edp3_lcd, + msm_mux_edp_hot, + msm_mux_egpio, + msm_mux_emac0_dll, + msm_mux_emac0_mcg0, + msm_mux_emac0_mcg1, + msm_mux_emac0_mcg2, + msm_mux_emac0_mcg3, + msm_mux_emac0_phy, + msm_mux_emac0_ptp, + msm_mux_emac1_dll0, + msm_mux_emac1_dll1, + msm_mux_emac1_mcg0, + msm_mux_emac1_mcg1, + msm_mux_emac1_mcg2, + msm_mux_emac1_mcg3, + msm_mux_emac1_phy, + msm_mux_emac1_ptp, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gcc_gp4, + msm_mux_gcc_gp5, + msm_mux_gpio, + msm_mux_hs1_mi2s, + msm_mux_hs2_mi2s, + msm_mux_hs3_mi2s, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_lpass_slimbus, + msm_mux_mdp0_vsync0, + msm_mux_mdp0_vsync1, + msm_mux_mdp0_vsync2, + msm_mux_mdp0_vsync3, + msm_mux_mdp0_vsync4, + msm_mux_mdp0_vsync5, + msm_mux_mdp0_vsync6, + msm_mux_mdp0_vsync7, + msm_mux_mdp0_vsync8, + msm_mux_mdp1_vsync0, + msm_mux_mdp1_vsync1, + msm_mux_mdp1_vsync2, + msm_mux_mdp1_vsync3, + msm_mux_mdp1_vsync4, + msm_mux_mdp1_vsync5, + msm_mux_mdp1_vsync6, + msm_mux_mdp1_vsync7, + msm_mux_mdp1_vsync8, + msm_mux_mdp_vsync, + msm_mux_mi2s0_data0, + msm_mux_mi2s0_data1, + msm_mux_mi2s0_sck, + msm_mux_mi2s0_ws, + msm_mux_mi2s1_data0, + msm_mux_mi2s1_data1, + msm_mux_mi2s1_sck, + msm_mux_mi2s1_ws, + msm_mux_mi2s2_data0, + msm_mux_mi2s2_data1, + msm_mux_mi2s2_sck, + msm_mux_mi2s2_ws, + msm_mux_mi2s_mclk1, + msm_mux_mi2s_mclk2, + msm_mux_pcie2a_clkreq, + msm_mux_pcie2b_clkreq, + msm_mux_pcie3a_clkreq, + msm_mux_pcie3b_clkreq, + msm_mux_pcie4_clkreq, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_clk, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qspi, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup16, + msm_mux_qup17, + msm_mux_qup18, + msm_mux_qup19, + msm_mux_qup2, + msm_mux_qup20, + msm_mux_qup21, + msm_mux_qup22, + msm_mux_qup23, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_rgmii_0, + msm_mux_rgmii_1, + msm_mux_sd_write, + msm_mux_sdc40, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_tb_trig, + msm_mux_tgu, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsense_pwm3, + msm_mux_tsense_pwm4, + msm_mux_usb0_dp, + msm_mux_usb0_phy, + msm_mux_usb0_sbrx, + msm_mux_usb0_sbtx, + msm_mux_usb0_usb4, + msm_mux_usb1_dp, + msm_mux_usb1_phy, + msm_mux_usb1_sbrx, + msm_mux_usb1_sbtx, + msm_mux_usb1_usb4, + msm_mux_usb2phy_ac, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio78", + "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", "gpio85", + "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", "gpio92", + "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", + "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", + "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", + "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", "gpio117", + "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", "gpio123", + "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", "gpio129", + "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", "gpio135", + "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", "gpio141", + "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", "gpio147", + "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", "gpio153", + "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", "gpio159", + "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", "gpio165", + "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", "gpio171", + "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", "gpio177", + "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", "gpio183", + "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", "gpio189", + "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", "gpio195", + "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", "gpio201", + "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", "gpio207", + "gpio208", "gpio209", "gpio210", "gpio211", "gpio212", "gpio213", + "gpio214", "gpio215", "gpio216", "gpio217", "gpio218", "gpio219", + "gpio220", "gpio221", "gpio222", "gpio223", "gpio224", "gpio225", + "gpio226", "gpio227", +}; + +static const char * const atest_char_groups[] = { + "gpio134", "gpio139", "gpio140", "gpio142", "gpio143", +}; + +static const char * const atest_usb_groups[] = { + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio78", + "gpio79", "gpio97", "gpio98", "gpio101", "gpio102", "gpio103", + "gpio104", "gpio105", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio121", "gpio122", "gpio130", "gpio131", "gpio135", + "gpio137", "gpio138", "gpio148", "gpio149", +}; + +static const char * const audio_ref_groups[] = { + "gpio80", +}; + +static const char * const cam_mclk_groups[] = { + "gpio6", "gpio7", "gpio16", "gpio17", "gpio33", "gpio34", "gpio119", + "gpio120", +}; + +static const char * const cci_async_groups[] = { + "gpio15", "gpio119", "gpio120", "gpio160", "gpio161", "gpio167", +}; + +static const char * const cci_i2c_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", "gpio113", "gpio114", + "gpio115", "gpio116", "gpio117", "gpio118", "gpio123", "gpio124", + "gpio145", "gpio146", "gpio164", "gpio165", +}; + +static const char * const cci_timer0_groups[] = { + "gpio119", +}; + +static const char * const cci_timer1_groups[] = { + "gpio120", +}; + +static const char * const cci_timer2_groups[] = { + "gpio14", +}; + +static const char * const cci_timer3_groups[] = { + "gpio15", +}; + +static const char * const cci_timer4_groups[] = { + "gpio161", +}; + +static const char * const cci_timer5_groups[] = { + "gpio139", +}; + +static const char * const cci_timer6_groups[] = { + "gpio162", +}; + +static const char * const cci_timer7_groups[] = { + "gpio163", +}; + +static const char * const cci_timer8_groups[] = { + "gpio167", +}; + +static const char * const cci_timer9_groups[] = { + "gpio160", +}; + +static const char * const cmu_rng_groups[] = { + "gpio123", "gpio124", "gpio126", "gpio136", +}; + +static const char * const cri_trng0_groups[] = { + "gpio187", +}; + +static const char * const cri_trng1_groups[] = { + "gpio188", +}; + +static const char * const cri_trng_groups[] = { + "gpio190", +}; + +static const char * const dbg_out_groups[] = { + "gpio125", +}; + +static const char * const ddr_bist_groups[] = { + "gpio42", "gpio45", "gpio46", "gpio47", +}; + +static const char * const ddr_pxi0_groups[] = { + "gpio121", "gpio126", +}; + +static const char * const ddr_pxi1_groups[] = { + "gpio124", "gpio125", +}; + +static const char * const ddr_pxi2_groups[] = { + "gpio123", "gpio138", +}; + +static const char * const ddr_pxi3_groups[] = { + "gpio120", "gpio137", +}; + +static const char * const ddr_pxi4_groups[] = { + "gpio216", "gpio217", +}; + +static const char * const ddr_pxi5_groups[] = { + "gpio214", "gpio215", +}; + +static const char * const ddr_pxi6_groups[] = { + "gpio79", "gpio218", +}; + +static const char * const ddr_pxi7_groups[] = { + "gpio135", "gpio136", +}; + +static const char * const dp2_hot_groups[] = { + "gpio20", +}; + +static const char * const dp3_hot_groups[] = { + "gpio45", +}; + +static const char * const edp0_lcd_groups[] = { + "gpio26", +}; + +static const char * const edp1_lcd_groups[] = { + "gpio27", +}; + +static const char * const edp2_lcd_groups[] = { + "gpio28", +}; + +static const char * const edp3_lcd_groups[] = { + "gpio29", +}; + +static const char * const edp_hot_groups[] = { + "gpio2", "gpio3", "gpio6", "gpio7", +}; + +static const char * const egpio_groups[] = { + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", + "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", + "gpio207", "gpio208", "gpio209", "gpio210", "gpio211", "gpio212", + "gpio213", "gpio214", "gpio215", "gpio216", "gpio217", "gpio218", + "gpio219", "gpio220", "gpio221", "gpio222", "gpio223", "gpio224", + "gpio225", "gpio226", "gpio227", +}; + +static const char * const emac0_dll_groups[] = { + "gpio216", "gpio217", +}; + +static const char * const emac0_mcg0_groups[] = { + "gpio160", +}; + +static const char * const emac0_mcg1_groups[] = { + "gpio161", +}; + +static const char * const emac0_mcg2_groups[] = { + "gpio162", +}; + +static const char * const emac0_mcg3_groups[] = { + "gpio163", +}; + +static const char * const emac0_phy_groups[] = { + "gpio127", +}; + +static const char * const emac0_ptp_groups[] = { + "gpio130", "gpio130", "gpio131", "gpio131", "gpio156", "gpio156", + "gpio157", "gpio157", "gpio158", "gpio158", "gpio159", "gpio159", +}; + +static const char * const emac1_dll0_groups[] = { + "gpio215", +}; + +static const char * const emac1_dll1_groups[] = { + "gpio218", +}; + +static const char * const emac1_mcg0_groups[] = { + "gpio57", +}; + +static const char * const emac1_mcg1_groups[] = { + "gpio58", +}; + +static const char * const emac1_mcg2_groups[] = { + "gpio68", +}; + +static const char * const emac1_mcg3_groups[] = { + "gpio69", +}; + +static const char * const emac1_phy_groups[] = { + "gpio54", +}; + +static const char * const emac1_ptp_groups[] = { + "gpio55", "gpio55", "gpio56", "gpio56", "gpio93", "gpio93", "gpio94", + "gpio94", "gpio95", "gpio95", "gpio96", "gpio96", +}; + +static const char * const gcc_gp1_groups[] = { + "gpio119", "gpio149", +}; + +static const char * const gcc_gp2_groups[] = { + "gpio114", "gpio120", +}; + +static const char * const gcc_gp3_groups[] = { + "gpio115", "gpio139", +}; + +static const char * const gcc_gp4_groups[] = { + "gpio160", "gpio162", +}; + +static const char * const gcc_gp5_groups[] = { + "gpio167", "gpio168", +}; + +static const char * const hs1_mi2s_groups[] = { + "gpio208", "gpio209", "gpio210", "gpio211", +}; + +static const char * const hs2_mi2s_groups[] = { + "gpio91", "gpio92", "gpio218", "gpio219", +}; + +static const char * const hs3_mi2s_groups[] = { + "gpio224", "gpio225", "gpio226", "gpio227", +}; + +static const char * const ibi_i3c_groups[] = { + "gpio4", "gpio5", "gpio36", "gpio37", "gpio128", "gpio129", "gpio154", + "gpio155", +}; + +static const char * const jitter_bist_groups[] = { + "gpio140", +}; + +static const char * const lpass_slimbus_groups[] = { + "gpio220", "gpio221", +}; + +static const char * const mdp0_vsync0_groups[] = { + "gpio1", +}; + +static const char * const mdp0_vsync1_groups[] = { + "gpio2", +}; + +static const char * const mdp0_vsync2_groups[] = { + "gpio8", +}; + +static const char * const mdp0_vsync3_groups[] = { + "gpio9", +}; + +static const char * const mdp0_vsync4_groups[] = { + "gpio10", +}; + +static const char * const mdp0_vsync5_groups[] = { + "gpio11", +}; + +static const char * const mdp0_vsync6_groups[] = { + "gpio12", +}; + +static const char * const mdp0_vsync7_groups[] = { + "gpio13", +}; + +static const char * const mdp0_vsync8_groups[] = { + "gpio16", +}; + +static const char * const mdp1_vsync0_groups[] = { + "gpio17", +}; + +static const char * const mdp1_vsync1_groups[] = { + "gpio18", +}; + +static const char * const mdp1_vsync2_groups[] = { + "gpio19", +}; + +static const char * const mdp1_vsync3_groups[] = { + "gpio20", +}; + +static const char * const mdp1_vsync4_groups[] = { + "gpio36", +}; + +static const char * const mdp1_vsync5_groups[] = { + "gpio37", +}; + +static const char * const mdp1_vsync6_groups[] = { + "gpio38", +}; + +static const char * const mdp1_vsync7_groups[] = { + "gpio39", +}; + +static const char * const mdp1_vsync8_groups[] = { + "gpio40", +}; + +static const char * const mdp_vsync_groups[] = { + "gpio8", "gpio100", "gpio101", +}; + +static const char * const mi2s0_data0_groups[] = { + "gpio95", +}; + +static const char * const mi2s0_data1_groups[] = { + "gpio96", +}; + +static const char * const mi2s0_sck_groups[] = { + "gpio93", +}; + +static const char * const mi2s0_ws_groups[] = { + "gpio94", +}; + +static const char * const mi2s1_data0_groups[] = { + "gpio222", +}; + +static const char * const mi2s1_data1_groups[] = { + "gpio223", +}; + +static const char * const mi2s1_sck_groups[] = { + "gpio220", +}; + +static const char * const mi2s1_ws_groups[] = { + "gpio221", +}; + +static const char * const mi2s2_data0_groups[] = { + "gpio214", +}; + +static const char * const mi2s2_data1_groups[] = { + "gpio215", +}; + +static const char * const mi2s2_sck_groups[] = { + "gpio212", +}; + +static const char * const mi2s2_ws_groups[] = { + "gpio213", +}; + +static const char * const mi2s_mclk1_groups[] = { + "gpio80", "gpio216", +}; + +static const char * const mi2s_mclk2_groups[] = { + "gpio217", +}; + +static const char * const pcie2a_clkreq_groups[] = { + "gpio142", +}; + +static const char * const pcie2b_clkreq_groups[] = { + "gpio144", +}; + +static const char * const pcie3a_clkreq_groups[] = { + "gpio150", +}; + +static const char * const pcie3b_clkreq_groups[] = { + "gpio152", +}; + +static const char * const pcie4_clkreq_groups[] = { + "gpio140", +}; + +static const char * const phase_flag_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio83", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio132", + "gpio144", "gpio145", "gpio146", "gpio147", "gpio195", "gpio196", + "gpio197", "gpio198", "gpio202", "gpio219", "gpio220", "gpio221", + "gpio222", "gpio223", "gpio224", "gpio225", "gpio226", "gpio227", +}; + +static const char * const pll_bist_groups[] = { + "gpio84", +}; + +static const char * const pll_clk_groups[] = { + "gpio84", "gpio86", +}; + +static const char * const prng_rosc0_groups[] = { + "gpio189", +}; + +static const char * const prng_rosc1_groups[] = { + "gpio191", +}; + +static const char * const prng_rosc2_groups[] = { + "gpio193", +}; + +static const char * const prng_rosc3_groups[] = { + "gpio194", +}; + +static const char * const qdss_cti_groups[] = { + "gpio3", "gpio4", "gpio7", "gpio21", "gpio30", "gpio30", "gpio31", + "gpio31", +}; + +static const char * const qdss_gpio_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", + "gpio17", "gpio80", "gpio96", "gpio115", "gpio116", "gpio117", + "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", "gpio161", + "gpio162", "gpio195", "gpio196", "gpio197", "gpio198", "gpio201", + "gpio202", "gpio206", "gpio207", "gpio212", "gpio213", "gpio214", + "gpio215", "gpio216", "gpio217", "gpio222", "gpio223", +}; + +static const char * const qspi_clk_groups[] = { + "gpio74", +}; + +static const char * const qspi_cs_groups[] = { + "gpio75", "gpio81", +}; + +static const char * const qspi_groups[] = { + "gpio76", "gpio78", "gpio79", +}; + +static const char * const qup0_groups[] = { + "gpio135", "gpio136", "gpio137", "gpio138", +}; + +static const char * const qup10_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25", +}; + +static const char * const qup11_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21", +}; + +static const char * const qup12_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const qup13_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29", +}; + +static const char * const qup14_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const qup15_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char * const qup16_groups[] = { + "gpio70", "gpio71", "gpio72", "gpio73", +}; + +static const char * const qup17_groups[] = { + "gpio61", "gpio62", "gpio63", "gpio64", +}; + +static const char * const qup18_groups[] = { + "gpio66", "gpio67", "gpio68", "gpio69", +}; + +static const char * const qup19_groups[] = { + "gpio55", "gpio56", "gpio57", "gpio58", +}; + +static const char * const qup1_groups[] = { + "gpio158", "gpio159", "gpio160", "gpio161", +}; + +static const char * const qup20_groups[] = { + "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", "gpio92", "gpio110", +}; + +static const char * const qup21_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", +}; + +static const char * const qup22_groups[] = { + "gpio83", "gpio84", "gpio85", "gpio86", +}; + +static const char * const qup23_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62", +}; + +static const char * const qup2_groups[] = { + "gpio121", "gpio122", "gpio123", "gpio124", +}; + +static const char * const qup3_groups[] = { + "gpio135", "gpio136", "gpio137", "gpio138", +}; + +static const char * const qup4_groups[] = { + "gpio111", "gpio112", "gpio171", "gpio172", "gpio173", "gpio174", + "gpio175", +}; + +static const char * const qup5_groups[] = { + "gpio111", "gpio112", "gpio145", "gpio146", +}; + +static const char * const qup6_groups[] = { + "gpio154", "gpio155", "gpio156", "gpio157", +}; + +static const char * const qup7_groups[] = { + "gpio125", "gpio126", "gpio128", "gpio129", +}; + +static const char * const qup8_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46", +}; + +static const char * const qup9_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44", +}; + +static const char * const rgmii_0_groups[] = { + "gpio175", "gpio176", "gpio177", "gpio178", "gpio179", "gpio180", + "gpio181", "gpio182", "gpio183", "gpio184", "gpio185", "gpio186", + "gpio187", "gpio188", +}; + +static const char * const rgmii_1_groups[] = { + "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", + "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", + "gpio109", "gpio110", +}; + +static const char * const sd_write_groups[] = { + "gpio130", +}; + +static const char * const sdc40_groups[] = { + "gpio76", +}; + +static const char * const sdc42_groups[] = { + "gpio78", +}; + +static const char * const sdc43_groups[] = { + "gpio79", +}; + +static const char * const sdc4_clk_groups[] = { + "gpio74", +}; + +static const char * const sdc4_cmd_groups[] = { + "gpio75", +}; + +static const char * const tb_trig_groups[] = { + "gpio153", "gpio157", +}; + +static const char * const tgu_groups[] = { + "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", + "gpio107", "gpio108", +}; + +static const char * const tsense_pwm1_groups[] = { + "gpio70", +}; + +static const char * const tsense_pwm2_groups[] = { + "gpio69", +}; + +static const char * const tsense_pwm3_groups[] = { + "gpio67", +}; + +static const char * const tsense_pwm4_groups[] = { + "gpio65", +}; + +static const char * const usb0_dp_groups[] = { + "gpio21", +}; + +static const char * const usb0_phy_groups[] = { + "gpio166", +}; + +static const char * const usb0_sbrx_groups[] = { + "gpio170", +}; + +static const char * const usb0_sbtx_groups[] = { + "gpio168", "gpio169", +}; + +static const char * const usb0_usb4_groups[] = { + "gpio132", +}; + +static const char * const usb1_dp_groups[] = { + "gpio9", +}; + +static const char * const usb1_phy_groups[] = { + "gpio49", +}; + +static const char * const usb1_sbrx_groups[] = { + "gpio53", +}; + +static const char * const usb1_sbtx_groups[] = { + "gpio51", "gpio52", +}; + +static const char * const usb1_usb4_groups[] = { + "gpio32", +}; + +static const char * const usb2phy_ac_groups[] = { + "gpio24", "gpio25", "gpio133", "gpio134", "gpio148", "gpio149", +}; + +static const char * const vsense_trigger_groups[] = { + "gpio81", +}; + +static const struct msm_function sc8280xp_functions[] = { + FUNCTION(atest_char), + FUNCTION(atest_usb), + FUNCTION(audio_ref), + FUNCTION(cam_mclk), + FUNCTION(cci_async), + FUNCTION(cci_i2c), + FUNCTION(cci_timer0), + FUNCTION(cci_timer1), + FUNCTION(cci_timer2), + FUNCTION(cci_timer3), + FUNCTION(cci_timer4), + FUNCTION(cci_timer5), + FUNCTION(cci_timer6), + FUNCTION(cci_timer7), + FUNCTION(cci_timer8), + FUNCTION(cci_timer9), + FUNCTION(cmu_rng), + FUNCTION(cri_trng), + FUNCTION(cri_trng0), + FUNCTION(cri_trng1), + FUNCTION(dbg_out), + FUNCTION(ddr_bist), + FUNCTION(ddr_pxi0), + FUNCTION(ddr_pxi1), + FUNCTION(ddr_pxi2), + FUNCTION(ddr_pxi3), + FUNCTION(ddr_pxi4), + FUNCTION(ddr_pxi5), + FUNCTION(ddr_pxi6), + FUNCTION(ddr_pxi7), + FUNCTION(dp2_hot), + FUNCTION(dp3_hot), + FUNCTION(edp0_lcd), + FUNCTION(edp1_lcd), + FUNCTION(edp2_lcd), + FUNCTION(edp3_lcd), + FUNCTION(edp_hot), + FUNCTION(egpio), + FUNCTION(emac0_dll), + FUNCTION(emac0_mcg0), + FUNCTION(emac0_mcg1), + FUNCTION(emac0_mcg2), + FUNCTION(emac0_mcg3), + FUNCTION(emac0_phy), + FUNCTION(emac0_ptp), + FUNCTION(emac1_dll0), + FUNCTION(emac1_dll1), + FUNCTION(emac1_mcg0), + FUNCTION(emac1_mcg1), + FUNCTION(emac1_mcg2), + FUNCTION(emac1_mcg3), + FUNCTION(emac1_phy), + FUNCTION(emac1_ptp), + FUNCTION(gcc_gp1), + FUNCTION(gcc_gp2), + FUNCTION(gcc_gp3), + FUNCTION(gcc_gp4), + FUNCTION(gcc_gp5), + FUNCTION(gpio), + FUNCTION(hs1_mi2s), + FUNCTION(hs2_mi2s), + FUNCTION(hs3_mi2s), + FUNCTION(ibi_i3c), + FUNCTION(jitter_bist), + FUNCTION(lpass_slimbus), + FUNCTION(mdp0_vsync0), + FUNCTION(mdp0_vsync1), + FUNCTION(mdp0_vsync2), + FUNCTION(mdp0_vsync3), + FUNCTION(mdp0_vsync4), + FUNCTION(mdp0_vsync5), + FUNCTION(mdp0_vsync6), + FUNCTION(mdp0_vsync7), + FUNCTION(mdp0_vsync8), + FUNCTION(mdp1_vsync0), + FUNCTION(mdp1_vsync1), + FUNCTION(mdp1_vsync2), + FUNCTION(mdp1_vsync3), + FUNCTION(mdp1_vsync4), + FUNCTION(mdp1_vsync5), + FUNCTION(mdp1_vsync6), + FUNCTION(mdp1_vsync7), + FUNCTION(mdp1_vsync8), + FUNCTION(mdp_vsync), + FUNCTION(mi2s0_data0), + FUNCTION(mi2s0_data1), + FUNCTION(mi2s0_sck), + FUNCTION(mi2s0_ws), + FUNCTION(mi2s1_data0), + FUNCTION(mi2s1_data1), + FUNCTION(mi2s1_sck), + FUNCTION(mi2s1_ws), + FUNCTION(mi2s2_data0), + FUNCTION(mi2s2_data1), + FUNCTION(mi2s2_sck), + FUNCTION(mi2s2_ws), + FUNCTION(mi2s_mclk1), + FUNCTION(mi2s_mclk2), + FUNCTION(pcie2a_clkreq), + FUNCTION(pcie2b_clkreq), + FUNCTION(pcie3a_clkreq), + FUNCTION(pcie3b_clkreq), + FUNCTION(pcie4_clkreq), + FUNCTION(phase_flag), + FUNCTION(pll_bist), + FUNCTION(pll_clk), + FUNCTION(prng_rosc0), + FUNCTION(prng_rosc1), + FUNCTION(prng_rosc2), + FUNCTION(prng_rosc3), + FUNCTION(qdss_cti), + FUNCTION(qdss_gpio), + FUNCTION(qspi), + FUNCTION(qspi_clk), + FUNCTION(qspi_cs), + FUNCTION(qup0), + FUNCTION(qup1), + FUNCTION(qup2), + FUNCTION(qup3), + FUNCTION(qup4), + FUNCTION(qup5), + FUNCTION(qup6), + FUNCTION(qup7), + FUNCTION(qup8), + FUNCTION(qup9), + FUNCTION(qup10), + FUNCTION(qup11), + FUNCTION(qup12), + FUNCTION(qup13), + FUNCTION(qup14), + FUNCTION(qup15), + FUNCTION(qup16), + FUNCTION(qup17), + FUNCTION(qup18), + FUNCTION(qup19), + FUNCTION(qup20), + FUNCTION(qup21), + FUNCTION(qup22), + FUNCTION(qup23), + FUNCTION(rgmii_0), + FUNCTION(rgmii_1), + FUNCTION(sd_write), + FUNCTION(sdc40), + FUNCTION(sdc42), + FUNCTION(sdc43), + FUNCTION(sdc4_clk), + FUNCTION(sdc4_cmd), + FUNCTION(tb_trig), + FUNCTION(tgu), + FUNCTION(tsense_pwm1), + FUNCTION(tsense_pwm2), + FUNCTION(tsense_pwm3), + FUNCTION(tsense_pwm4), + FUNCTION(usb0_dp), + FUNCTION(usb0_phy), + FUNCTION(usb0_sbrx), + FUNCTION(usb0_sbtx), + FUNCTION(usb0_usb4), + FUNCTION(usb1_dp), + FUNCTION(usb1_phy), + FUNCTION(usb1_sbrx), + FUNCTION(usb1_sbtx), + FUNCTION(usb1_usb4), + FUNCTION(usb2phy_ac), + FUNCTION(vsense_trigger), +}; + +static const struct msm_pingroup sc8280xp_groups[] = { + [0] = PINGROUP(0, qup12, _, _, _, _, _, _), + [1] = PINGROUP(1, qup12, mdp0_vsync0, _, _, _, _, _), + [2] = PINGROUP(2, edp_hot, qup12, mdp0_vsync1, _, _, _, _), + [3] = PINGROUP(3, edp_hot, qup12, qdss_cti, _, _, _, _), + [4] = PINGROUP(4, qup14, ibi_i3c, qdss_cti, _, _, _, _), + [5] = PINGROUP(5, qup14, ibi_i3c, _, _, _, _, _), + [6] = PINGROUP(6, edp_hot, qup14, cam_mclk, _, _, _, _), + [7] = PINGROUP(7, edp_hot, qup14, qdss_cti, cam_mclk, _, _, _), + [8] = PINGROUP(8, mdp_vsync, mdp0_vsync2, _, _, _, _, _), + [9] = PINGROUP(9, usb1_dp, mdp0_vsync3, _, _, _, _, _), + [10] = PINGROUP(10, cci_i2c, mdp0_vsync4, _, qdss_gpio, _, _, _), + [11] = PINGROUP(11, cci_i2c, mdp0_vsync5, _, qdss_gpio, _, _, _), + [12] = PINGROUP(12, cci_i2c, mdp0_vsync6, _, qdss_gpio, _, _, _), + [13] = PINGROUP(13, cci_i2c, mdp0_vsync7, _, qdss_gpio, _, _, _), + [14] = PINGROUP(14, cci_timer2, qdss_gpio, _, _, _, _, _), + [15] = PINGROUP(15, cci_timer3, cci_async, _, qdss_gpio, _, _, _), + [16] = PINGROUP(16, cam_mclk, mdp0_vsync8, _, qdss_gpio, _, _, _), + [17] = PINGROUP(17, cam_mclk, mdp1_vsync0, _, qdss_gpio, _, _, _), + [18] = PINGROUP(18, qup11, mdp1_vsync1, _, _, _, _, _), + [19] = PINGROUP(19, qup11, mdp1_vsync2, _, _, _, _, _), + [20] = PINGROUP(20, qup11, dp2_hot, mdp1_vsync3, _, _, _, _), + [21] = PINGROUP(21, qup11, usb0_dp, qdss_cti, _, _, _, _), + [22] = PINGROUP(22, qup10, _, _, _, _, _, _), + [23] = PINGROUP(23, qup10, _, _, _, _, _, _), + [24] = PINGROUP(24, qup10, usb2phy_ac, _, _, _, _, _), + [25] = PINGROUP(25, qup10, usb2phy_ac, _, _, _, _, _), + [26] = PINGROUP(26, qup13, edp0_lcd, _, _, _, _, _), + [27] = PINGROUP(27, qup13, edp1_lcd, _, _, _, _, _), + [28] = PINGROUP(28, qup13, edp2_lcd, _, _, _, _, _), + [29] = PINGROUP(29, qup13, edp3_lcd, _, _, _, _, _), + [30] = PINGROUP(30, qdss_cti, qdss_cti, _, _, _, _, _), + [31] = PINGROUP(31, qdss_cti, qdss_cti, _, _, _, _, _), + [32] = PINGROUP(32, usb1_usb4, _, _, _, _, _, _), + [33] = PINGROUP(33, cam_mclk, _, _, _, _, _, _), + [34] = PINGROUP(34, cam_mclk, _, _, _, _, _, _), + [35] = PINGROUP(35, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup15, ibi_i3c, mdp1_vsync4, _, _, _, _), + [37] = PINGROUP(37, qup15, ibi_i3c, mdp1_vsync5, _, _, _, _), + [38] = PINGROUP(38, qup15, mdp1_vsync6, _, _, _, _, _), + [39] = PINGROUP(39, qup15, mdp1_vsync7, _, _, _, _, _), + [40] = PINGROUP(40, mdp1_vsync8, _, _, _, _, _, _), + [41] = PINGROUP(41, qup9, _, _, _, _, _, _), + [42] = PINGROUP(42, qup9, ddr_bist, _, _, _, _, _), + [43] = PINGROUP(43, qup8, qup9, _, _, _, _, _), + [44] = PINGROUP(44, qup8, qup9, _, _, _, _, _), + [45] = PINGROUP(45, qup8, dp3_hot, ddr_bist, _, _, _, _), + [46] = PINGROUP(46, qup8, ddr_bist, _, _, _, _, _), + [47] = PINGROUP(47, ddr_bist, _, _, _, _, _, _), + [48] = PINGROUP(48, _, _, _, _, _, _, _), + [49] = PINGROUP(49, usb1_phy, _, _, _, _, _, _), + [50] = PINGROUP(50, _, _, _, _, _, _, _), + [51] = PINGROUP(51, usb1_sbtx, _, _, _, _, _, _), + [52] = PINGROUP(52, usb1_sbtx, _, _, _, _, _, _), + [53] = PINGROUP(53, usb1_sbrx, _, _, _, _, _, _), + [54] = PINGROUP(54, emac1_phy, _, _, _, _, _, _), + [55] = PINGROUP(55, emac1_ptp, emac1_ptp, qup19, _, _, _, _), + [56] = PINGROUP(56, emac1_ptp, emac1_ptp, qup19, _, _, _, _), + [57] = PINGROUP(57, qup19, emac1_mcg0, _, _, _, _, _), + [58] = PINGROUP(58, qup19, emac1_mcg1, _, _, _, _, _), + [59] = PINGROUP(59, qup23, _, _, _, _, _, _), + [60] = PINGROUP(60, qup23, _, _, _, _, _, _), + [61] = PINGROUP(61, qup23, qup17, _, _, _, _, _), + [62] = PINGROUP(62, qup23, qup17, _, _, _, _, _), + [63] = PINGROUP(63, qup17, _, _, _, _, _, _), + [64] = PINGROUP(64, qup17, _, _, _, _, _, _), + [65] = PINGROUP(65, tsense_pwm4, _, _, _, _, _, _), + [66] = PINGROUP(66, qup18, _, _, _, _, _, _), + [67] = PINGROUP(67, qup18, tsense_pwm3, _, _, _, _, _), + [68] = PINGROUP(68, qup18, emac1_mcg2, _, _, _, _, _), + [69] = PINGROUP(69, qup18, emac1_mcg3, tsense_pwm2, _, _, _, _), + [70] = PINGROUP(70, qup16, tsense_pwm1, _, _, _, _, _), + [71] = PINGROUP(71, qup16, atest_usb, _, _, _, _, _), + [72] = PINGROUP(72, qup16, atest_usb, _, _, _, _, _), + [73] = PINGROUP(73, qup16, atest_usb, _, _, _, _, _), + [74] = PINGROUP(74, qspi_clk, sdc4_clk, atest_usb, _, _, _, _), + [75] = PINGROUP(75, qspi_cs, sdc4_cmd, atest_usb, _, _, _, _), + [76] = PINGROUP(76, qspi, sdc40, atest_usb, _, _, _, _), + [77] = PINGROUP(77, _, _, _, _, _, _, _), + [78] = PINGROUP(78, qspi, sdc42, atest_usb, _, _, _, _), + [79] = PINGROUP(79, qspi, sdc43, atest_usb, ddr_pxi6, _, _, _), + [80] = PINGROUP(80, mi2s_mclk1, audio_ref, phase_flag, _, qdss_gpio, _, _), + [81] = PINGROUP(81, qup21, qspi_cs, phase_flag, _, vsense_trigger, _, _), + [82] = PINGROUP(82, qup21, phase_flag, _, _, _, _, _), + [83] = PINGROUP(83, qup21, qup22, phase_flag, _, _, _, _), + [84] = PINGROUP(84, qup21, qup22, pll_bist, pll_clk, _, _, _), + [85] = PINGROUP(85, qup22, _, _, _, _, _, _), + [86] = PINGROUP(86, qup22, _, pll_clk, _, _, _, _), + [87] = PINGROUP(87, qup20, phase_flag, _, _, _, _, _), + [88] = PINGROUP(88, qup20, phase_flag, _, _, _, _, _), + [89] = PINGROUP(89, qup20, phase_flag, _, _, _, _, _), + [90] = PINGROUP(90, qup20, phase_flag, _, _, _, _, _), + [91] = PINGROUP(91, qup20, hs2_mi2s, phase_flag, _, _, _, _), + [92] = PINGROUP(92, qup20, hs2_mi2s, phase_flag, _, _, _, _), + [93] = PINGROUP(93, mi2s0_sck, emac1_ptp, emac1_ptp, phase_flag, _, _, _), + [94] = PINGROUP(94, mi2s0_ws, emac1_ptp, emac1_ptp, phase_flag, _, _, _), + [95] = PINGROUP(95, mi2s0_data0, emac1_ptp, emac1_ptp, phase_flag, _, _, _), + [96] = PINGROUP(96, mi2s0_data1, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _), + [97] = PINGROUP(97, rgmii_1, atest_usb, _, _, _, _, _), + [98] = PINGROUP(98, rgmii_1, atest_usb, _, _, _, _, _), + [99] = PINGROUP(99, rgmii_1, _, _, _, _, _, _), + [100] = PINGROUP(100, mdp_vsync, rgmii_1, _, _, _, _, _), + [101] = PINGROUP(101, mdp_vsync, rgmii_1, tgu, atest_usb, _, _, _), + [102] = PINGROUP(102, rgmii_1, tgu, atest_usb, _, _, _, _), + [103] = PINGROUP(103, rgmii_1, tgu, atest_usb, _, _, _, _), + [104] = PINGROUP(104, rgmii_1, tgu, atest_usb, _, _, _, _), + [105] = PINGROUP(105, rgmii_1, tgu, atest_usb, _, _, _, _), + [106] = PINGROUP(106, rgmii_1, tgu, _, _, _, _, _), + [107] = PINGROUP(107, rgmii_1, tgu, _, _, _, _, _), + [108] = PINGROUP(108, rgmii_1, tgu, _, _, _, _, _), + [109] = PINGROUP(109, rgmii_1, _, _, _, _, _, _), + [110] = PINGROUP(110, qup20, rgmii_1, atest_usb, _, _, _, _), + [111] = PINGROUP(111, qup4, qup5, atest_usb, _, _, _, _), + [112] = PINGROUP(112, qup4, qup5, atest_usb, _, _, _, _), + [113] = PINGROUP(113, cci_i2c, atest_usb, _, _, _, _, _), + [114] = PINGROUP(114, cci_i2c, gcc_gp2, atest_usb, _, _, _, _), + [115] = PINGROUP(115, cci_i2c, gcc_gp3, qdss_gpio, _, _, _, _), + [116] = PINGROUP(116, cci_i2c, qdss_gpio, _, _, _, _, _), + [117] = PINGROUP(117, cci_i2c, _, qdss_gpio, _, _, _, _), + [118] = PINGROUP(118, cci_i2c, _, qdss_gpio, _, _, _, _), + [119] = PINGROUP(119, cam_mclk, cci_timer0, cci_async, gcc_gp1, qdss_gpio, _, _), + [120] = PINGROUP(120, cam_mclk, cci_timer1, cci_async, gcc_gp2, qdss_gpio, ddr_pxi3, _), + [121] = PINGROUP(121, qup2, qdss_gpio, _, atest_usb, ddr_pxi0, _, _), + [122] = PINGROUP(122, qup2, qdss_gpio, atest_usb, _, _, _, _), + [123] = PINGROUP(123, qup2, cci_i2c, cmu_rng, ddr_pxi2, _, _, _), + [124] = PINGROUP(124, qup2, cci_i2c, cmu_rng, ddr_pxi1, _, _, _), + [125] = PINGROUP(125, qup7, dbg_out, ddr_pxi1, _, _, _, _), + [126] = PINGROUP(126, qup7, cmu_rng, ddr_pxi0, _, _, _, _), + [127] = PINGROUP(127, emac0_phy, _, _, _, _, _, _), + [128] = PINGROUP(128, qup7, ibi_i3c, _, _, _, _, _), + [129] = PINGROUP(129, qup7, ibi_i3c, _, _, _, _, _), + [130] = PINGROUP(130, emac0_ptp, emac0_ptp, sd_write, atest_usb, _, _, _), + [131] = PINGROUP(131, emac0_ptp, emac0_ptp, atest_usb, _, _, _, _), + [132] = PINGROUP(132, usb0_usb4, phase_flag, _, _, _, _, _), + [133] = PINGROUP(133, usb2phy_ac, _, _, _, _, _, _), + [134] = PINGROUP(134, usb2phy_ac, atest_char, _, _, _, _, _), + [135] = PINGROUP(135, qup0, qup3, _, atest_usb, ddr_pxi7, _, _), + [136] = PINGROUP(136, qup0, qup3, cmu_rng, ddr_pxi7, _, _, _), + [137] = PINGROUP(137, qup3, qup0, _, atest_usb, ddr_pxi3, _, _), + [138] = PINGROUP(138, qup3, qup0, _, atest_usb, ddr_pxi2, _, _), + [139] = PINGROUP(139, cci_timer5, gcc_gp3, atest_char, _, _, _, _), + [140] = PINGROUP(140, pcie4_clkreq, jitter_bist, atest_char, _, _, _, _), + [141] = PINGROUP(141, _, _, _, _, _, _, _), + [142] = PINGROUP(142, pcie2a_clkreq, atest_char, _, _, _, _, _), + [143] = PINGROUP(143, _, atest_char, _, _, _, _, _), + [144] = PINGROUP(144, pcie2b_clkreq, phase_flag, _, _, _, _, _), + [145] = PINGROUP(145, qup5, cci_i2c, phase_flag, _, _, _, _), + [146] = PINGROUP(146, qup5, cci_i2c, phase_flag, _, _, _, _), + [147] = PINGROUP(147, _, phase_flag, _, _, _, _, _), + [148] = PINGROUP(148, usb2phy_ac, _, atest_usb, _, _, _, _), + [149] = PINGROUP(149, usb2phy_ac, gcc_gp1, atest_usb, _, _, _, _), + [150] = PINGROUP(150, pcie3a_clkreq, _, _, _, _, _, _), + [151] = PINGROUP(151, _, _, _, _, _, _, _), + [152] = PINGROUP(152, pcie3b_clkreq, _, _, _, _, _, _), + [153] = PINGROUP(153, _, tb_trig, _, _, _, _, _), + [154] = PINGROUP(154, qup6, ibi_i3c, _, _, _, _, _), + [155] = PINGROUP(155, qup6, ibi_i3c, _, _, _, _, _), + [156] = PINGROUP(156, qup6, emac0_ptp, emac0_ptp, _, _, _, _), + [157] = PINGROUP(157, qup6, emac0_ptp, emac0_ptp, tb_trig, _, _, _), + [158] = PINGROUP(158, qup1, emac0_ptp, emac0_ptp, _, _, _, _), + [159] = PINGROUP(159, qup1, emac0_ptp, emac0_ptp, _, _, _, _), + [160] = PINGROUP(160, cci_timer9, qup1, cci_async, emac0_mcg0, gcc_gp4, _, _), + [161] = PINGROUP(161, cci_timer4, cci_async, qup1, emac0_mcg1, qdss_gpio, _, _), + [162] = PINGROUP(162, cci_timer6, emac0_mcg2, gcc_gp4, qdss_gpio, _, _, _), + [163] = PINGROUP(163, cci_timer7, emac0_mcg3, _, _, _, _, _), + [164] = PINGROUP(164, cci_i2c, _, _, _, _, _, _), + [165] = PINGROUP(165, cci_i2c, _, _, _, _, _, _), + [166] = PINGROUP(166, usb0_phy, _, _, _, _, _, _), + [167] = PINGROUP(167, cci_timer8, cci_async, gcc_gp5, _, _, _, _), + [168] = PINGROUP(168, usb0_sbtx, gcc_gp5, _, _, _, _, _), + [169] = PINGROUP(169, usb0_sbtx, _, _, _, _, _, _), + [170] = PINGROUP(170, usb0_sbrx, _, _, _, _, _, _), + [171] = PINGROUP(171, qup4, _, _, _, _, _, _), + [172] = PINGROUP(172, qup4, _, _, _, _, _, _), + [173] = PINGROUP(173, qup4, _, _, _, _, _, _), + [174] = PINGROUP(174, qup4, _, _, _, _, _, _), + [175] = PINGROUP(175, qup4, rgmii_0, _, _, _, _, _), + [176] = PINGROUP(176, rgmii_0, _, _, _, _, _, _), + [177] = PINGROUP(177, rgmii_0, _, _, _, _, _, _), + [178] = PINGROUP(178, rgmii_0, _, _, _, _, _, _), + [179] = PINGROUP(179, rgmii_0, _, _, _, _, _, _), + [180] = PINGROUP(180, rgmii_0, _, _, _, _, _, _), + [181] = PINGROUP(181, rgmii_0, _, _, _, _, _, _), + [182] = PINGROUP(182, rgmii_0, _, _, _, _, _, _), + [183] = PINGROUP(183, rgmii_0, _, _, _, _, _, _), + [184] = PINGROUP(184, rgmii_0, _, _, _, _, _, _), + [185] = PINGROUP(185, rgmii_0, _, _, _, _, _, _), + [186] = PINGROUP(186, rgmii_0, _, _, _, _, _, _), + [187] = PINGROUP(187, rgmii_0, cri_trng0, _, _, _, _, _), + [188] = PINGROUP(188, rgmii_0, cri_trng1, _, _, _, _, _), + [189] = PINGROUP(189, prng_rosc0, _, _, _, _, _, egpio), + [190] = PINGROUP(190, cri_trng, _, _, _, _, _, egpio), + [191] = PINGROUP(191, prng_rosc1, _, _, _, _, _, egpio), + [192] = PINGROUP(192, _, _, _, _, _, _, egpio), + [193] = PINGROUP(193, prng_rosc2, _, _, _, _, _, egpio), + [194] = PINGROUP(194, prng_rosc3, _, _, _, _, _, egpio), + [195] = PINGROUP(195, phase_flag, _, qdss_gpio, _, _, _, egpio), + [196] = PINGROUP(196, phase_flag, _, qdss_gpio, _, _, _, egpio), + [197] = PINGROUP(197, phase_flag, _, qdss_gpio, _, _, _, egpio), + [198] = PINGROUP(198, phase_flag, _, qdss_gpio, _, _, _, egpio), + [199] = PINGROUP(199, _, _, _, _, _, _, egpio), + [200] = PINGROUP(200, _, _, _, _, _, _, egpio), + [201] = PINGROUP(201, qdss_gpio, _, _, _, _, _, egpio), + [202] = PINGROUP(202, phase_flag, _, qdss_gpio, _, _, _, egpio), + [203] = PINGROUP(203, _, _, _, _, _, _, egpio), + [204] = PINGROUP(204, _, _, _, _, _, _, egpio), + [205] = PINGROUP(205, _, _, _, _, _, _, egpio), + [206] = PINGROUP(206, qdss_gpio, _, _, _, _, _, egpio), + [207] = PINGROUP(207, qdss_gpio, _, _, _, _, _, egpio), + [208] = PINGROUP(208, hs1_mi2s, _, _, _, _, _, egpio), + [209] = PINGROUP(209, hs1_mi2s, _, _, _, _, _, egpio), + [210] = PINGROUP(210, hs1_mi2s, _, _, _, _, _, egpio), + [211] = PINGROUP(211, hs1_mi2s, _, _, _, _, _, egpio), + [212] = PINGROUP(212, mi2s2_sck, qdss_gpio, _, _, _, _, egpio), + [213] = PINGROUP(213, mi2s2_ws, qdss_gpio, _, _, _, _, egpio), + [214] = PINGROUP(214, mi2s2_data0, qdss_gpio, ddr_pxi5, _, _, _, egpio), + [215] = PINGROUP(215, mi2s2_data1, qdss_gpio, emac1_dll0, ddr_pxi5, _, _, egpio), + [216] = PINGROUP(216, mi2s_mclk1, qdss_gpio, emac0_dll, ddr_pxi4, _, _, egpio), + [217] = PINGROUP(217, mi2s_mclk2, qdss_gpio, emac0_dll, ddr_pxi4, _, _, egpio), + [218] = PINGROUP(218, hs2_mi2s, emac1_dll1, ddr_pxi6, _, _, _, egpio), + [219] = PINGROUP(219, hs2_mi2s, phase_flag, _, _, _, _, egpio), + [220] = PINGROUP(220, lpass_slimbus, mi2s1_sck, phase_flag, _, _, _, egpio), + [221] = PINGROUP(221, lpass_slimbus, mi2s1_ws, phase_flag, _, _, _, egpio), + [222] = PINGROUP(222, mi2s1_data0, phase_flag, _, qdss_gpio, _, _, egpio), + [223] = PINGROUP(223, mi2s1_data1, phase_flag, _, qdss_gpio, _, _, egpio), + [224] = PINGROUP(224, hs3_mi2s, phase_flag, _, _, _, _, egpio), + [225] = PINGROUP(225, hs3_mi2s, phase_flag, _, _, _, _, egpio), + [226] = PINGROUP(226, hs3_mi2s, phase_flag, _, _, _, _, egpio), + [227] = PINGROUP(227, hs3_mi2s, phase_flag, _, _, _, _, egpio), + [228] = UFS_RESET(ufs_reset, 0xf1004), + [229] = UFS_RESET(ufs1_reset, 0xf3004), + [230] = SDC_QDSD_PINGROUP(sdc2_clk, 0xe8000, 14, 6), + [231] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xe8000, 11, 3), + [232] = SDC_QDSD_PINGROUP(sdc2_data, 0xe8000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sc8280xp_pdc_map[] = { + { 3, 245 }, { 4, 263 }, { 7, 254 }, { 21, 220 }, { 25, 244 }, + { 26, 211 }, { 27, 172 }, { 29, 203 }, { 30, 169 }, { 31, 180 }, + { 32, 181 }, { 33, 182 }, { 36, 206 }, { 39, 246 }, { 40, 183 }, + { 42, 179 }, { 46, 247 }, { 53, 248 }, { 54, 190 }, { 55, 249 }, + { 56, 250 }, { 58, 251 }, { 59, 207 }, { 62, 252 }, { 63, 191 }, + { 64, 192 }, { 65, 193 }, { 69, 253 }, { 73, 255 }, { 84, 256 }, + { 85, 208 }, { 90, 257 }, { 102, 214 }, { 103, 215 }, { 104, 216 }, + { 107, 217 }, { 110, 218 }, { 124, 224 }, { 125, 189 }, + { 126, 200 }, { 127, 225 }, { 128, 262 }, { 129, 201 }, + { 130, 209 }, { 131, 173 }, { 132, 202 }, { 136, 210 }, + { 138, 171 }, { 139, 226 }, { 140, 227 }, { 142, 228 }, + { 144, 229 }, { 145, 230 }, { 146, 231 }, { 148, 232 }, + { 149, 233 }, { 150, 234 }, { 152, 235 }, { 154, 212 }, + { 157, 213 }, { 161, 219 }, { 170, 236 }, { 171, 221 }, + { 174, 222 }, { 175, 237 }, { 176, 223 }, { 177, 170 }, + { 180, 238 }, { 181, 239 }, { 182, 240 }, { 183, 241 }, + { 184, 242 }, { 185, 243 }, { 190, 178 }, { 193, 184 }, + { 196, 185 }, { 198, 186 }, { 200, 174 }, { 201, 175 }, + { 205, 176 }, { 206, 177 }, { 208, 187 }, { 210, 198 }, + { 211, 199 }, { 212, 204 }, { 215, 205 }, { 220, 188 }, + { 221, 194 }, { 223, 195 }, { 225, 196 }, { 227, 197 }, +}; + +static struct msm_pinctrl_soc_data sc8280xp_pinctrl = { + .pins = sc8280xp_pins, + .npins = ARRAY_SIZE(sc8280xp_pins), + .functions = sc8280xp_functions, + .nfunctions = ARRAY_SIZE(sc8280xp_functions), + .groups = sc8280xp_groups, + .ngroups = ARRAY_SIZE(sc8280xp_groups), + .ngpios = 230, + .wakeirq_map = sc8280xp_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sc8280xp_pdc_map), + .egpio_func = 7, +}; + +static int sc8280xp_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sc8280xp_pinctrl); +} + +static const struct of_device_id sc8280xp_pinctrl_of_match[] = { + { .compatible = "qcom,sc8280xp-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, sc8280xp_pinctrl_of_match); + +static struct platform_driver sc8280xp_pinctrl_driver = { + .driver = { + .name = "sc8280xp-tlmm", + .of_match_table = sc8280xp_pinctrl_of_match, + }, + .probe = sc8280xp_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sc8280xp_pinctrl_init(void) +{ + return platform_driver_register(&sc8280xp_pinctrl_driver); +} +arch_initcall(sc8280xp_pinctrl_init); + +static void __exit sc8280xp_pinctrl_exit(void) +{ + platform_driver_unregister(&sc8280xp_pinctrl_driver); +} +module_exit(sc8280xp_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm SC8280XP TLMM pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sm6125.c b/drivers/pinctrl/qcom/pinctrl-sm6125.c index 724fa5a34465..170d4ffbb919 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6125.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6125.c @@ -1,4 +1,4 @@ -//SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) #include <linux/module.h> #include <linux/of.h> diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450.c b/drivers/pinctrl/qcom/pinctrl-sm8450.c index c6fa3dbc14a1..3110d7bf5698 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450.c @@ -46,6 +46,8 @@ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ .oe_bit = 9, \ .in_bit = 0, \ .out_bit = 1, \ @@ -567,6 +569,7 @@ enum sm8450_functions { msm_mux_ddr_pxi2, msm_mux_ddr_pxi3, msm_mux_dp_hot, + msm_mux_egpio, msm_mux_gcc_gp1, msm_mux_gcc_gp2, msm_mux_gcc_gp3, @@ -719,6 +722,17 @@ static const char * const gpio_groups[] = { "gpio207", "gpio208", "gpio209", }; +static const char * const egpio_groups[] = { + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", + "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", + "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", + "gpio207", "gpio208", "gpio209", +}; + static const char * const aon_cam_groups[] = { "gpio108", }; @@ -1285,6 +1299,7 @@ static const struct msm_function sm8450_functions[] = { FUNCTION(ddr_pxi2), FUNCTION(ddr_pxi3), FUNCTION(dp_hot), + FUNCTION(egpio), FUNCTION(gcc_gp1), FUNCTION(gcc_gp2), FUNCTION(gcc_gp3), @@ -1571,51 +1586,51 @@ static const struct msm_pingroup sm8450_groups[] = { [162] = PINGROUP(162, qlink2_request, _, _, _, _, _, _, _, _), [163] = PINGROUP(163, qlink2_enable, _, _, _, _, _, _, _, _), [164] = PINGROUP(164, qlink2_wmss, _, _, _, _, _, _, _, _), - [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _), - [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _), - [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _), - [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _), - [169] = PINGROUP(169, _, _, _, _, _, _, _, _, _), - [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _), - [171] = PINGROUP(171, _, _, _, _, _, _, _, _, _), - [172] = PINGROUP(172, _, _, _, _, _, _, _, _, _), - [173] = PINGROUP(173, _, _, _, _, _, _, _, _, _), - [174] = PINGROUP(174, _, _, _, _, _, _, _, _, _), - [175] = PINGROUP(175, _, _, _, _, _, _, _, _, _), - [176] = PINGROUP(176, _, _, _, _, _, _, _, _, _), - [177] = PINGROUP(177, _, _, _, _, _, _, _, _, _), - [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _), - [179] = PINGROUP(179, _, _, _, _, _, _, _, _, _), - [180] = PINGROUP(180, _, _, _, _, _, _, _, _, _), - [181] = PINGROUP(181, _, _, _, _, _, _, _, _, _), - [182] = PINGROUP(182, _, _, _, _, _, _, _, _, _), - [183] = PINGROUP(183, _, _, _, _, _, _, _, _, _), - [184] = PINGROUP(184, _, _, _, _, _, _, _, _, _), - [185] = PINGROUP(185, _, _, _, _, _, _, _, _, _), - [186] = PINGROUP(186, _, _, _, _, _, _, _, _, _), - [187] = PINGROUP(187, _, _, _, _, _, _, _, _, _), - [188] = PINGROUP(188, _, qdss_gpio, _, _, _, _, _, _, _), - [189] = PINGROUP(189, _, qdss_gpio, _, _, _, _, _, _, _), - [190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, _), - [191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, _), - [192] = PINGROUP(192, _, qdss_gpio, _, _, _, _, _, _, _), - [193] = PINGROUP(193, _, qdss_gpio, _, _, _, _, _, _, _), - [194] = PINGROUP(194, _, qdss_gpio, _, _, _, _, _, _, _), - [195] = PINGROUP(195, _, qdss_gpio, _, _, _, _, _, _, _), - [196] = PINGROUP(196, _, qdss_gpio, _, _, _, _, _, _, _), - [197] = PINGROUP(197, _, qdss_gpio, _, _, _, _, _, _, _), - [198] = PINGROUP(198, _, qdss_gpio, _, _, _, _, _, _, _), - [199] = PINGROUP(199, _, qdss_gpio, _, _, _, _, _, _, _), - [200] = PINGROUP(200, _, qdss_gpio, _, _, _, _, _, _, _), - [201] = PINGROUP(201, _, qdss_gpio, _, _, _, _, _, _, _), - [202] = PINGROUP(202, qdss_gpio, _, _, _, _, _, _, _, _), - [203] = PINGROUP(203, qdss_gpio, _, _, _, _, _, _, _, _), - [204] = PINGROUP(204, qdss_gpio, _, _, _, _, _, _, _, _), - [205] = PINGROUP(205, qdss_gpio, _, _, _, _, _, _, _, _), - [206] = PINGROUP(206, qup5, _, _, _, _, _, _, _, _), - [207] = PINGROUP(207, qup5, _, _, _, _, _, _, _, _), - [208] = PINGROUP(208, cci_i2c, _, _, _, _, _, _, _, _), - [209] = PINGROUP(209, cci_i2c, _, _, _, _, _, _, _, _), + [165] = PINGROUP(165, _, _, _, _, _, _, _, _, egpio), + [166] = PINGROUP(166, _, _, _, _, _, _, _, _, egpio), + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, egpio), + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, egpio), + [169] = PINGROUP(169, _, _, _, _, _, _, _, _, egpio), + [170] = PINGROUP(170, _, _, _, _, _, _, _, _, egpio), + [171] = PINGROUP(171, _, _, _, _, _, _, _, _, egpio), + [172] = PINGROUP(172, _, _, _, _, _, _, _, _, egpio), + [173] = PINGROUP(173, _, _, _, _, _, _, _, _, egpio), + [174] = PINGROUP(174, _, _, _, _, _, _, _, _, egpio), + [175] = PINGROUP(175, _, _, _, _, _, _, _, _, egpio), + [176] = PINGROUP(176, _, _, _, _, _, _, _, _, egpio), + [177] = PINGROUP(177, _, _, _, _, _, _, _, _, egpio), + [178] = PINGROUP(178, _, _, _, _, _, _, _, _, egpio), + [179] = PINGROUP(179, _, _, _, _, _, _, _, _, egpio), + [180] = PINGROUP(180, _, _, _, _, _, _, _, _, egpio), + [181] = PINGROUP(181, _, _, _, _, _, _, _, _, egpio), + [182] = PINGROUP(182, _, _, _, _, _, _, _, _, egpio), + [183] = PINGROUP(183, _, _, _, _, _, _, _, _, egpio), + [184] = PINGROUP(184, _, _, _, _, _, _, _, _, egpio), + [185] = PINGROUP(185, _, _, _, _, _, _, _, _, egpio), + [186] = PINGROUP(186, _, _, _, _, _, _, _, _, egpio), + [187] = PINGROUP(187, _, _, _, _, _, _, _, _, egpio), + [188] = PINGROUP(188, _, qdss_gpio, _, _, _, _, _, _, egpio), + [189] = PINGROUP(189, _, qdss_gpio, _, _, _, _, _, _, egpio), + [190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, egpio), + [191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, egpio), + [192] = PINGROUP(192, _, qdss_gpio, _, _, _, _, _, _, egpio), + [193] = PINGROUP(193, _, qdss_gpio, _, _, _, _, _, _, egpio), + [194] = PINGROUP(194, _, qdss_gpio, _, _, _, _, _, _, egpio), + [195] = PINGROUP(195, _, qdss_gpio, _, _, _, _, _, _, egpio), + [196] = PINGROUP(196, _, qdss_gpio, _, _, _, _, _, _, egpio), + [197] = PINGROUP(197, _, qdss_gpio, _, _, _, _, _, _, egpio), + [198] = PINGROUP(198, _, qdss_gpio, _, _, _, _, _, _, egpio), + [199] = PINGROUP(199, _, qdss_gpio, _, _, _, _, _, _, egpio), + [200] = PINGROUP(200, _, qdss_gpio, _, _, _, _, _, _, egpio), + [201] = PINGROUP(201, _, qdss_gpio, _, _, _, _, _, _, egpio), + [202] = PINGROUP(202, qdss_gpio, _, _, _, _, _, _, _, egpio), + [203] = PINGROUP(203, qdss_gpio, _, _, _, _, _, _, _, egpio), + [204] = PINGROUP(204, qdss_gpio, _, _, _, _, _, _, _, egpio), + [205] = PINGROUP(205, qdss_gpio, _, _, _, _, _, _, _, egpio), + [206] = PINGROUP(206, qup5, _, _, _, _, _, _, _, egpio), + [207] = PINGROUP(207, qup5, _, _, _, _, _, _, _, egpio), + [208] = PINGROUP(208, cci_i2c, _, _, _, _, _, _, _, egpio), + [209] = PINGROUP(209, cci_i2c, _, _, _, _, _, _, _, egpio), [210] = UFS_RESET(ufs_reset, 0xde000), [211] = SDC_QDSD_PINGROUP(sdc2_clk, 0xd6000, 14, 6), [212] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xd6000, 11, 3), @@ -1651,6 +1666,7 @@ static const struct msm_pinctrl_soc_data sm8450_tlmm = { .ngpios = 211, .wakeirq_map = sm8450_pdc_map, .nwakeirq_map = ARRAY_SIZE(sm8450_pdc_map), + .egpio_func = 9, }; static int sm8450_tlmm_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index f2eac3b05d67..4fbf8d3938ef 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1164,6 +1164,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm8350-gpio", .data = (void *) 10 }, { .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 }, { .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 }, + { .compatible = "qcom,pm8450-gpio", .data = (void *) 4 }, { .compatible = "qcom,pm8916-gpio", .data = (void *) 4 }, { .compatible = "qcom,pm8941-gpio", .data = (void *) 36 }, /* pm8950 has 8 GPIOs with holes on 3 */ diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index b80723928b7e..6937157f50b3 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -961,6 +961,7 @@ static int pmic_mpp_remove(struct platform_device *pdev) static const struct of_device_id pmic_mpp_of_match[] = { { .compatible = "qcom,pm8019-mpp", .data = (void *) 6 }, + { .compatible = "qcom,pm8226-mpp", .data = (void *) 8 }, { .compatible = "qcom,pm8841-mpp", .data = (void *) 4 }, { .compatible = "qcom,pm8916-mpp", .data = (void *) 4 }, { .compatible = "qcom,pm8941-mpp", .data = (void *) 8 }, diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 9a72999084b3..6b38720c56e3 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -37,7 +37,9 @@ config PINCTRL_RENESAS select PINCTRL_PFC_R8A77990 if ARCH_R8A77990 select PINCTRL_PFC_R8A77995 if ARCH_R8A77995 select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0 + select PINCTRL_PFC_R8A779F0 if ARCH_R8A779F0 select PINCTRL_RZG2L if ARCH_R9A07G044 + select PINCTRL_RZG2L if ARCH_R9A07G054 select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203 select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264 select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269 @@ -132,6 +134,10 @@ config PINCTRL_PFC_R8A77961 bool "pin control support for R-Car M3-W+" if COMPILE_TEST select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A779F0 + bool "pin control support for R-Car S4-8" if COMPILE_TEST + select PINCTRL_SH_PFC + config PINCTRL_PFC_R8A7792 bool "pin control support for R-Car V2H" if COMPILE_TEST select PINCTRL_SH_PFC @@ -178,14 +184,15 @@ config PINCTRL_RZA2 This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. config PINCTRL_RZG2L - bool "pin control support for RZ/G2L" if COMPILE_TEST + bool "pin control support for RZ/{G2L,V2L}" if COMPILE_TEST depends on OF select GPIOLIB select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF help - This selects GPIO and pinctrl driver for Renesas RZ/G2L platforms. + This selects GPIO and pinctrl driver for Renesas RZ/{G2L,V2L} + platforms. config PINCTRL_PFC_R8A77470 bool "pin control support for RZ/G1C" if COMPILE_TEST diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index 7d9238a9ef57..5d936c154a6f 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o +obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index 0d4ea2e22a53..d0d4714731c1 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -636,6 +636,12 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a779a0_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A779F0 + { + .compatible = "renesas,pfc-r8a779f0", + .data = &r8a779f0_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_SH73A0 { .compatible = "renesas,pfc-sh73a0", @@ -741,10 +747,13 @@ static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; } #ifdef DEBUG #define SH_PFC_MAX_REGS 300 -#define SH_PFC_MAX_ENUMS 3000 +#define SH_PFC_MAX_ENUMS 5000 static unsigned int sh_pfc_errors __initdata; static unsigned int sh_pfc_warnings __initdata; +static bool sh_pfc_bias_done __initdata; +static bool sh_pfc_drive_done __initdata; +static bool sh_pfc_power_done __initdata; static struct { u32 reg; u32 bits; @@ -758,6 +767,15 @@ static u32 sh_pfc_num_enums __initdata; pr_err("%s: " fmt, drvname, ##__VA_ARGS__); \ sh_pfc_errors++; \ } while (0) + +#define sh_pfc_err_once(type, fmt, ...) \ + do { \ + if (!sh_pfc_ ## type ## _done) { \ + sh_pfc_ ## type ## _done = true; \ + sh_pfc_err(fmt, ##__VA_ARGS__); \ + } \ + } while (0) + #define sh_pfc_warn(fmt, ...) \ do { \ pr_warn("%s: " fmt, drvname, ##__VA_ARGS__); \ @@ -777,10 +795,7 @@ static bool __init is0s(const u16 *enum_ids, unsigned int n) static bool __init same_name(const char *a, const char *b) { - if (!a || !b) - return false; - - return !strcmp(a, b); + return a && b && !strcmp(a, b); } static void __init sh_pfc_check_reg(const char *drvname, u32 reg, u32 bits) @@ -839,21 +854,22 @@ static void __init sh_pfc_check_reg_enums(const char *drvname, u32 reg, } } -static void __init sh_pfc_check_pin(const struct sh_pfc_soc_info *info, - u32 reg, unsigned int pin) +static const struct sh_pfc_pin __init *sh_pfc_find_pin( + const struct sh_pfc_soc_info *info, u32 reg, unsigned int pin) { const char *drvname = info->name; unsigned int i; if (pin == SH_PFC_PIN_NONE) - return; + return NULL; for (i = 0; i < info->nr_pins; i++) { if (pin == info->pins[i].pin) - return; + return &info->pins[i]; } sh_pfc_err("reg 0x%x: pin %u not found\n", reg, pin); + return NULL; } static void __init sh_pfc_check_cfg_reg(const char *drvname, @@ -865,7 +881,8 @@ static void __init sh_pfc_check_cfg_reg(const char *drvname, GENMASK(cfg_reg->reg_width - 1, 0)); if (cfg_reg->field_width) { - n = cfg_reg->reg_width / cfg_reg->field_width; + fw = cfg_reg->field_width; + n = (cfg_reg->reg_width / fw) << fw; /* Skip field checks (done at build time) */ goto check_enum_ids; } @@ -893,6 +910,8 @@ check_enum_ids: static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info, const struct pinmux_drive_reg *drive) { + const char *drvname = info->name; + const struct sh_pfc_pin *pin; unsigned int i; for (i = 0; i < ARRAY_SIZE(drive->fields); i++) { @@ -905,13 +924,18 @@ static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info, GENMASK(field->offset + field->size - 1, field->offset)); - sh_pfc_check_pin(info, drive->reg, field->pin); + pin = sh_pfc_find_pin(info, drive->reg, field->pin); + if (pin && !(pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH)) + sh_pfc_err("drive_reg 0x%x: field %u: pin %s lacks SH_PFC_PIN_CFG_DRIVE_STRENGTH flag\n", + drive->reg, i, pin->name); } } static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info, const struct pinmux_bias_reg *bias) { + const char *drvname = info->name; + const struct sh_pfc_pin *pin; unsigned int i; u32 bits; @@ -923,12 +947,66 @@ static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info, sh_pfc_check_reg(info->name, bias->puen, bits); if (bias->pud) sh_pfc_check_reg(info->name, bias->pud, bits); - for (i = 0; i < ARRAY_SIZE(bias->pins); i++) - sh_pfc_check_pin(info, bias->puen, bias->pins[i]); + for (i = 0; i < ARRAY_SIZE(bias->pins); i++) { + pin = sh_pfc_find_pin(info, bias->puen, bias->pins[i]); + if (!pin) + continue; + + if (bias->puen && bias->pud) { + /* + * Pull-enable and pull-up/down control registers + * As some SoCs have pins that support only pull-up + * or pull-down, we just check for one of them + */ + if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN)) + sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks one or more SH_PFC_PIN_CFG_PULL_* flags\n", + bias->puen, i, pin->name); + } else if (bias->puen) { + /* Pull-up control register only */ + if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP)) + sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_UP flag\n", + bias->puen, i, pin->name); + } else if (bias->pud) { + /* Pull-down control register only */ + if (!(pin->configs & SH_PFC_PIN_CFG_PULL_DOWN)) + sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_DOWN flag\n", + bias->pud, i, pin->name); + } + } +} + +static void __init sh_pfc_compare_groups(const char *drvname, + const struct sh_pfc_pin_group *a, + const struct sh_pfc_pin_group *b) +{ + unsigned int i; + size_t len; + + if (same_name(a->name, b->name)) + sh_pfc_err("group %s: name conflict\n", a->name); + + if (a->nr_pins > b->nr_pins) + swap(a, b); + + len = a->nr_pins * sizeof(a->pins[0]); + for (i = 0; i <= b->nr_pins - a->nr_pins; i++) { + if (a->pins == b->pins + i || a->mux == b->mux + i || + memcmp(a->pins, b->pins + i, len) || + memcmp(a->mux, b->mux + i, len)) + continue; + + if (a->nr_pins == b->nr_pins) + sh_pfc_warn("group %s can be an alias for %s\n", + a->name, b->name); + else + sh_pfc_warn("group %s is a subset of %s\n", a->name, + b->name); + } } static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) { + const struct pinmux_drive_reg *drive_regs = info->drive_regs; const struct pinmux_bias_reg *bias_regs = info->bias_regs; const char *drvname = info->name; unsigned int *refcnts; @@ -937,10 +1015,14 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) pr_info("sh_pfc: Checking %s\n", drvname); sh_pfc_num_regs = 0; sh_pfc_num_enums = 0; + sh_pfc_bias_done = false; + sh_pfc_drive_done = false; + sh_pfc_power_done = false; /* Check pins */ for (i = 0; i < info->nr_pins; i++) { const struct sh_pfc_pin *pin = &info->pins[i]; + unsigned int x; if (!pin->name) { sh_pfc_err("empty pin %u\n", i); @@ -962,6 +1044,65 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) pin->name, pin2->name, pin->enum_id); } + + if (pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) { + if (!info->ops || !info->ops->get_bias || + !info->ops->set_bias) + sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_* flag set but .[gs]et_bias() not implemented\n"); + + if (!bias_regs && + (!info->ops || !info->ops->pin_to_portcr)) + sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_UP flag set but no bias_regs defined and .pin_to_portcr() not implemented\n"); + } + + if ((pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) && bias_regs) { + const struct pinmux_bias_reg *bias_reg = + rcar_pin_to_bias_reg(info, pin->pin, &x); + + if (!bias_reg || + ((pin->configs & SH_PFC_PIN_CFG_PULL_UP) && + !bias_reg->puen)) + sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_UP flag set but pin not in bias_regs\n", + pin->name); + + if (!bias_reg || + ((pin->configs & SH_PFC_PIN_CFG_PULL_DOWN) && + !bias_reg->pud)) + sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_DOWN flag set but pin not in bias_regs\n", + pin->name); + } + + if (pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH) { + if (!drive_regs) { + sh_pfc_err_once(drive, "SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but drive_regs missing\n"); + } else { + for (j = 0; drive_regs[j / 8].reg; j++) { + if (!drive_regs[j / 8].fields[j % 8].pin && + !drive_regs[j / 8].fields[j % 8].offset && + !drive_regs[j / 8].fields[j % 8].size) + continue; + + if (drive_regs[j / 8].fields[j % 8].pin == pin->pin) + break; + } + + if (!drive_regs[j / 8].reg) + sh_pfc_err("pin %s: SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but not in drive_regs\n", + pin->name); + } + } + + if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE) { + if (!info->ops || !info->ops->pin_to_pocctrl) + sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE flag set but .pin_to_pocctrl() not implemented\n"); + else if (info->ops->pin_to_pocctrl(pin->pin, &x) < 0) + sh_pfc_err("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE set but invalid pin_to_pocctrl()\n", + pin->name); + } else if (info->ops && info->ops->pin_to_pocctrl && + info->ops->pin_to_pocctrl(pin->pin, &x) >= 0) { + sh_pfc_warn("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE not set but valid pin_to_pocctrl()\n", + pin->name); + } } /* Check groups and functions */ @@ -1003,11 +1144,9 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) sh_pfc_err("empty group %u\n", i); continue; } - for (j = 0; j < i; j++) { - if (same_name(group->name, info->groups[j].name)) - sh_pfc_err("group %s: name conflict\n", - group->name); - } + for (j = 0; j < i; j++) + sh_pfc_compare_groups(drvname, group, &info->groups[j]); + if (!refcnts[i]) sh_pfc_err("orphan group %s\n", group->name); else if (refcnts[i] > 1) @@ -1022,13 +1161,53 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]); /* Check drive strength registers */ - for (i = 0; info->drive_regs && info->drive_regs[i].reg; i++) - sh_pfc_check_drive_reg(info, &info->drive_regs[i]); + for (i = 0; drive_regs && drive_regs[i].reg; i++) + sh_pfc_check_drive_reg(info, &drive_regs[i]); + + for (i = 0; drive_regs && drive_regs[i / 8].reg; i++) { + if (!drive_regs[i / 8].fields[i % 8].pin && + !drive_regs[i / 8].fields[i % 8].offset && + !drive_regs[i / 8].fields[i % 8].size) + continue; + + for (j = 0; j < i; j++) { + if (drive_regs[i / 8].fields[i % 8].pin == + drive_regs[j / 8].fields[j % 8].pin && + drive_regs[j / 8].fields[j % 8].offset && + drive_regs[j / 8].fields[j % 8].size) { + sh_pfc_err("drive_reg 0x%x:%u/0x%x:%u: pin conflict\n", + drive_regs[i / 8].reg, i % 8, + drive_regs[j / 8].reg, j % 8); + } + } + } /* Check bias registers */ for (i = 0; bias_regs && (bias_regs[i].puen || bias_regs[i].pud); i++) sh_pfc_check_bias_reg(info, &bias_regs[i]); + for (i = 0; bias_regs && + (bias_regs[i / 32].puen || bias_regs[i / 32].pud); i++) { + if (bias_regs[i / 32].pins[i % 32] == SH_PFC_PIN_NONE) + continue; + + for (j = 0; j < i; j++) { + if (bias_regs[i / 32].pins[i % 32] != + bias_regs[j / 32].pins[j % 32]) + continue; + + if (bias_regs[i / 32].puen && bias_regs[j / 32].puen) + sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n", + bias_regs[i / 32].puen, i % 32, + bias_regs[j / 32].puen, j % 32); + if (bias_regs[i / 32].pud && bias_regs[j / 32].pud) + sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n", + bias_regs[i / 32].pud, i % 32, + bias_regs[j / 32].pud, j % 32); + } + + } + /* Check ioctrl registers */ for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++) sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg, U32_MAX); diff --git a/drivers/pinctrl/renesas/pfc-emev2.c b/drivers/pinctrl/renesas/pfc-emev2.c index 6c66fc335d2f..2326d348447d 100644 --- a/drivers/pinctrl/renesas/pfc-emev2.c +++ b/drivers/pinctrl/renesas/pfc-emev2.c @@ -749,23 +749,14 @@ static const unsigned int cf_ctrl_mux[] = { CF_CDB2_MARK, }; -static const unsigned int cf_data8_pins[] = { - /* CF_D[0:7] */ - 77, 78, 79, 80, - 81, 82, 83, 84, -}; -static const unsigned int cf_data8_mux[] = { - CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK, - CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK, -}; -static const unsigned int cf_data16_pins[] = { +static const unsigned int cf_data_pins[] = { /* CF_D[0:15] */ 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, }; -static const unsigned int cf_data16_mux[] = { +static const unsigned int cf_data_mux[] = { CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK, CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK, CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK, @@ -895,26 +886,12 @@ static const unsigned int sdi0_ctrl_mux[] = { SDI0_CKO_MARK, SDI0_CKI_MARK, SDI0_CMD_MARK, }; -static const unsigned int sdi0_data1_pins[] = { - /* SDI0_DATA[0] */ - 53, -}; -static const unsigned int sdi0_data1_mux[] = { - SDI0_DATA0_MARK, -}; -static const unsigned int sdi0_data4_pins[] = { - /* SDI0_DATA[0:3] */ - 53, 54, 55, 56, -}; -static const unsigned int sdi0_data4_mux[] = { - SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK, -}; -static const unsigned int sdi0_data8_pins[] = { +static const unsigned int sdi0_data_pins[] = { /* SDI0_DATA[0:7] */ 53, 54, 55, 56, 57, 58, 59, 60 }; -static const unsigned int sdi0_data8_mux[] = { +static const unsigned int sdi0_data_mux[] = { SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK, SDI0_DATA4_MARK, SDI0_DATA5_MARK, SDI0_DATA6_MARK, SDI0_DATA7_MARK, }; @@ -928,18 +905,11 @@ static const unsigned int sdi1_ctrl_mux[] = { SDI1_CKO_MARK, SDI1_CKI_MARK, SDI1_CMD_MARK, }; -static const unsigned int sdi1_data1_pins[] = { - /* SDI1_DATA[0] */ - 64, -}; -static const unsigned int sdi1_data1_mux[] = { - SDI1_DATA0_MARK, -}; -static const unsigned int sdi1_data4_pins[] = { +static const unsigned int sdi1_data_pins[] = { /* SDI1_DATA[0:3] */ 64, 65, 66, 67, }; -static const unsigned int sdi1_data4_mux[] = { +static const unsigned int sdi1_data_mux[] = { SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK, }; @@ -952,18 +922,11 @@ static const unsigned int sdi2_ctrl_mux[] = { SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK, }; -static const unsigned int sdi2_data1_pins[] = { - /* SDI2_DATA[0] */ - 89, -}; -static const unsigned int sdi2_data1_mux[] = { - SDI2_DATA0_MARK, -}; -static const unsigned int sdi2_data4_pins[] = { +static const unsigned int sdi2_data_pins[] = { /* SDI2_DATA[0:3] */ 89, 90, 91, 92, }; -static const unsigned int sdi2_data4_mux[] = { +static const unsigned int sdi2_data_mux[] = { SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK, SDI2_DATA3_MARK, }; @@ -1131,8 +1094,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(cam), SH_PFC_PIN_GROUP(cf_ctrl), - SH_PFC_PIN_GROUP(cf_data8), - SH_PFC_PIN_GROUP(cf_data16), + BUS_DATA_PIN_GROUP(cf_data, 8), + BUS_DATA_PIN_GROUP(cf_data, 16), SH_PFC_PIN_GROUP(dtv_a), SH_PFC_PIN_GROUP(dtv_b), @@ -1161,17 +1124,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sd_cki), SH_PFC_PIN_GROUP(sdi0_ctrl), - SH_PFC_PIN_GROUP(sdi0_data1), - SH_PFC_PIN_GROUP(sdi0_data4), - SH_PFC_PIN_GROUP(sdi0_data8), + BUS_DATA_PIN_GROUP(sdi0_data, 1), + BUS_DATA_PIN_GROUP(sdi0_data, 4), + BUS_DATA_PIN_GROUP(sdi0_data, 8), SH_PFC_PIN_GROUP(sdi1_ctrl), - SH_PFC_PIN_GROUP(sdi1_data1), - SH_PFC_PIN_GROUP(sdi1_data4), + BUS_DATA_PIN_GROUP(sdi1_data, 1), + BUS_DATA_PIN_GROUP(sdi1_data, 4), SH_PFC_PIN_GROUP(sdi2_ctrl), - SH_PFC_PIN_GROUP(sdi2_data1), - SH_PFC_PIN_GROUP(sdi2_data4), + BUS_DATA_PIN_GROUP(sdi2_data, 1), + BUS_DATA_PIN_GROUP(sdi2_data, 4), SH_PFC_PIN_GROUP(tp33), diff --git a/drivers/pinctrl/renesas/pfc-r8a73a4.c b/drivers/pinctrl/renesas/pfc-r8a73a4.c index b26ff9d6ead4..ba3a1857f80a 100644 --- a/drivers/pinctrl/renesas/pfc-r8a73a4.c +++ b/drivers/pinctrl/renesas/pfc-r8a73a4.c @@ -1449,25 +1449,11 @@ IRQC_PINS_MUX(327, 55); IRQC_PINS_MUX(328, 56); IRQC_PINS_MUX(329, 57); /* - MMCIF0 ----------------------------------------------------------------- */ -static const unsigned int mmc0_data1_pins[] = { - /* D[0] */ - 164, -}; -static const unsigned int mmc0_data1_mux[] = { - MMCD0_0_MARK, -}; -static const unsigned int mmc0_data4_pins[] = { - /* D[0:3] */ - 164, 165, 166, 167, -}; -static const unsigned int mmc0_data4_mux[] = { - MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, -}; -static const unsigned int mmc0_data8_pins[] = { +static const unsigned int mmc0_data_pins[] = { /* D[0:7] */ 164, 165, 166, 167, 168, 169, 170, 171, }; -static const unsigned int mmc0_data8_mux[] = { +static const unsigned int mmc0_data_mux[] = { MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK, }; @@ -1479,25 +1465,11 @@ static const unsigned int mmc0_ctrl_mux[] = { MMCCMD0_MARK, MMCCLK0_MARK, }; /* - MMCIF1 ----------------------------------------------------------------- */ -static const unsigned int mmc1_data1_pins[] = { - /* D[0] */ - 199, -}; -static const unsigned int mmc1_data1_mux[] = { - MMCD1_0_MARK, -}; -static const unsigned int mmc1_data4_pins[] = { - /* D[0:3] */ - 199, 198, 197, 196, -}; -static const unsigned int mmc1_data4_mux[] = { - MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, -}; -static const unsigned int mmc1_data8_pins[] = { +static const unsigned int mmc1_data_pins[] = { /* D[0:7] */ 199, 198, 197, 196, 195, 194, 193, 192, }; -static const unsigned int mmc1_data8_mux[] = { +static const unsigned int mmc1_data_mux[] = { MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK, }; @@ -1704,18 +1676,11 @@ static const unsigned int scifb3_ctrl_b_mux[] = { SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK, }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - 302, -}; -static const unsigned int sdhi0_data1_mux[] = { - SDHID0_0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ 302, 303, 304, 305, }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -1740,18 +1705,11 @@ static const unsigned int sdhi0_wp_mux[] = { SDHIWP0_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - 289, -}; -static const unsigned int sdhi1_data1_mux[] = { - SDHID1_0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ 289, 290, 291, 292, }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK, }; static const unsigned int sdhi1_ctrl_pins[] = { @@ -1762,18 +1720,11 @@ static const unsigned int sdhi1_ctrl_mux[] = { SDHICLK1_MARK, SDHICMD1_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - 295, -}; -static const unsigned int sdhi2_data1_mux[] = { - SDHID2_0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:3] */ 295, 296, 297, 298, }; -static const unsigned int sdhi2_data4_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { @@ -1843,13 +1794,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(irqc_irq55), SH_PFC_PIN_GROUP(irqc_irq56), SH_PFC_PIN_GROUP(irqc_irq57), - SH_PFC_PIN_GROUP(mmc0_data1), - SH_PFC_PIN_GROUP(mmc0_data4), - SH_PFC_PIN_GROUP(mmc0_data8), + BUS_DATA_PIN_GROUP(mmc0_data, 1), + BUS_DATA_PIN_GROUP(mmc0_data, 4), + BUS_DATA_PIN_GROUP(mmc0_data, 8), SH_PFC_PIN_GROUP(mmc0_ctrl), - SH_PFC_PIN_GROUP(mmc1_data1), - SH_PFC_PIN_GROUP(mmc1_data4), - SH_PFC_PIN_GROUP(mmc1_data8), + BUS_DATA_PIN_GROUP(mmc1_data, 1), + BUS_DATA_PIN_GROUP(mmc1_data, 4), + BUS_DATA_PIN_GROUP(mmc1_data, 8), SH_PFC_PIN_GROUP(mmc1_ctrl), SH_PFC_PIN_GROUP(scifa0_data), SH_PFC_PIN_GROUP(scifa0_clk), @@ -1878,16 +1829,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scifb3_data_b), SH_PFC_PIN_GROUP(scifb3_clk_b), SH_PFC_PIN_GROUP(scifb3_ctrl_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), SH_PFC_PIN_GROUP(sdhi2_ctrl), }; @@ -2655,9 +2606,9 @@ static const unsigned int r8a73a4_portcr_offsets[] = { 0x00002000, 0x00003000, 0x00003000, }; -static void __iomem *r8a73a4_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin) +static int r8a73a4_pin_to_portcr(unsigned int pin) { - return pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin; + return r8a73a4_portcr_offsets[pin >> 5] + pin; } static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = { diff --git a/drivers/pinctrl/renesas/pfc-r8a7740.c b/drivers/pinctrl/renesas/pfc-r8a7740.c index 4eac3899d69b..e8b9fb74a802 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7740.c +++ b/drivers/pinctrl/renesas/pfc-r8a7740.c @@ -1638,33 +1638,14 @@ static const struct sh_pfc_pin pinmux_pins[] = { }; /* - BSC -------------------------------------------------------------------- */ -static const unsigned int bsc_data8_pins[] = { - /* D[0:7] */ - 157, 156, 155, 154, 153, 152, 151, 150, -}; -static const unsigned int bsc_data8_mux[] = { - D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, - D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, -}; -static const unsigned int bsc_data16_pins[] = { - /* D[0:15] */ - 157, 156, 155, 154, 153, 152, 151, 150, - 149, 148, 147, 146, 145, 144, 143, 142, -}; -static const unsigned int bsc_data16_mux[] = { - D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, - D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, - D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, - D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, -}; -static const unsigned int bsc_data32_pins[] = { +static const unsigned int bsc_data_pins[] = { /* D[0:31] */ 157, 156, 155, 154, 153, 152, 151, 150, 149, 148, 147, 146, 145, 144, 143, 142, 171, 170, 169, 168, 167, 166, 173, 172, 165, 164, 163, 162, 161, 160, 159, 158, }; -static const unsigned int bsc_data32_mux[] = { +static const unsigned int bsc_data_mux[] = { D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, @@ -1723,25 +1704,11 @@ static const unsigned int bsc_cs6a_pins[] = { static const unsigned int bsc_cs6a_mux[] = { CS6A_MARK, }; -static const unsigned int bsc_rd_we8_pins[] = { - /* RD, WE[0] */ - 115, 113, -}; -static const unsigned int bsc_rd_we8_mux[] = { - RD_FSC_MARK, WE0_FWE_MARK, -}; -static const unsigned int bsc_rd_we16_pins[] = { - /* RD, WE[0:1] */ - 115, 113, 112, -}; -static const unsigned int bsc_rd_we16_mux[] = { - RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, -}; -static const unsigned int bsc_rd_we32_pins[] = { +static const unsigned int bsc_rd_we_pins[] = { /* RD, WE[0:3] */ 115, 113, 112, 108, 107, }; -static const unsigned int bsc_rd_we32_mux[] = { +static const unsigned int bsc_rd_we_mux[] = { RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK, }; static const unsigned int bsc_bs_pins[] = { @@ -2064,58 +2031,6 @@ IRQC_PINS_MUX(31, 0, 41); IRQC_PINS_MUX(31, 1, 167); /* - LCD0 ------------------------------------------------------------------- */ -static const unsigned int lcd0_data8_pins[] = { - /* D[0:7] */ - 58, 57, 56, 55, 54, 53, 52, 51, -}; -static const unsigned int lcd0_data8_mux[] = { - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, - LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, -}; -static const unsigned int lcd0_data9_pins[] = { - /* D[0:8] */ - 58, 57, 56, 55, 54, 53, 52, 51, - 50, -}; -static const unsigned int lcd0_data9_mux[] = { - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, - LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, - LCD0_D8_MARK, -}; -static const unsigned int lcd0_data12_pins[] = { - /* D[0:11] */ - 58, 57, 56, 55, 54, 53, 52, 51, - 50, 49, 48, 47, -}; -static const unsigned int lcd0_data12_mux[] = { - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, - LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, - LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, -}; -static const unsigned int lcd0_data16_pins[] = { - /* D[0:15] */ - 58, 57, 56, 55, 54, 53, 52, 51, - 50, 49, 48, 47, 46, 45, 44, 43, -}; -static const unsigned int lcd0_data16_mux[] = { - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, - LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, - LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, - LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, -}; -static const unsigned int lcd0_data18_pins[] = { - /* D[0:17] */ - 58, 57, 56, 55, 54, 53, 52, 51, - 50, 49, 48, 47, 46, 45, 44, 43, - 42, 41, -}; -static const unsigned int lcd0_data18_mux[] = { - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, - LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, - LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, - LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, - LCD0_D16_MARK, LCD0_D17_MARK, -}; static const unsigned int lcd0_data24_0_pins[] = { /* D[0:23] */ 58, 57, 56, 55, 54, 53, 52, 51, @@ -2182,65 +2097,13 @@ static const unsigned int lcd0_sys_mux[] = { LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK, }; /* - LCD1 ------------------------------------------------------------------- */ -static const unsigned int lcd1_data8_pins[] = { - /* D[0:7] */ - 4, 3, 2, 1, 0, 91, 92, 23, -}; -static const unsigned int lcd1_data8_mux[] = { - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, - LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, -}; -static const unsigned int lcd1_data9_pins[] = { - /* D[0:8] */ - 4, 3, 2, 1, 0, 91, 92, 23, - 93, -}; -static const unsigned int lcd1_data9_mux[] = { - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, - LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, - LCD1_D8_MARK, -}; -static const unsigned int lcd1_data12_pins[] = { - /* D[0:11] */ - 4, 3, 2, 1, 0, 91, 92, 23, - 93, 94, 21, 201, -}; -static const unsigned int lcd1_data12_mux[] = { - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, - LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, - LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, -}; -static const unsigned int lcd1_data16_pins[] = { - /* D[0:15] */ - 4, 3, 2, 1, 0, 91, 92, 23, - 93, 94, 21, 201, 200, 199, 196, 195, -}; -static const unsigned int lcd1_data16_mux[] = { - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, - LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, - LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, - LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, -}; -static const unsigned int lcd1_data18_pins[] = { - /* D[0:17] */ - 4, 3, 2, 1, 0, 91, 92, 23, - 93, 94, 21, 201, 200, 199, 196, 195, - 194, 193, -}; -static const unsigned int lcd1_data18_mux[] = { - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, - LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, - LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, - LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, - LCD1_D16_MARK, LCD1_D17_MARK, -}; -static const unsigned int lcd1_data24_pins[] = { +static const unsigned int lcd1_data_pins[] = { /* D[0:23] */ 4, 3, 2, 1, 0, 91, 92, 23, 93, 94, 21, 201, 200, 199, 196, 195, 194, 193, 198, 197, 75, 74, 15, 14, }; -static const unsigned int lcd1_data24_mux[] = { +static const unsigned int lcd1_data_mux[] = { LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, @@ -2277,25 +2140,11 @@ static const unsigned int lcd1_sys_mux[] = { LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK, }; /* - MMCIF ------------------------------------------------------------------ */ -static const unsigned int mmc0_data1_0_pins[] = { - /* D[0] */ - 68, -}; -static const unsigned int mmc0_data1_0_mux[] = { - MMC0_D0_PORT68_MARK, -}; -static const unsigned int mmc0_data4_0_pins[] = { - /* D[0:3] */ - 68, 69, 70, 71, -}; -static const unsigned int mmc0_data4_0_mux[] = { - MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK, -}; -static const unsigned int mmc0_data8_0_pins[] = { +static const unsigned int mmc0_data_0_pins[] = { /* D[0:7] */ 68, 69, 70, 71, 72, 73, 74, 75, }; -static const unsigned int mmc0_data8_0_mux[] = { +static const unsigned int mmc0_data_0_mux[] = { MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, }; @@ -2307,25 +2156,11 @@ static const unsigned int mmc0_ctrl_0_mux[] = { MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK, }; -static const unsigned int mmc0_data1_1_pins[] = { - /* D[0] */ - 149, -}; -static const unsigned int mmc0_data1_1_mux[] = { - MMC1_D0_PORT149_MARK, -}; -static const unsigned int mmc0_data4_1_pins[] = { - /* D[0:3] */ - 149, 148, 147, 146, -}; -static const unsigned int mmc0_data4_1_mux[] = { - MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK, -}; -static const unsigned int mmc0_data8_1_pins[] = { +static const unsigned int mmc0_data_1_pins[] = { /* D[0:7] */ 149, 148, 147, 146, 145, 144, 143, 142, }; -static const unsigned int mmc0_data8_1_mux[] = { +static const unsigned int mmc0_data_1_mux[] = { MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, }; @@ -2591,18 +2426,11 @@ static const unsigned int scifb_ctrl_1_mux[] = { SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK, }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - 77, -}; -static const unsigned int sdhi0_data1_mux[] = { - SDHI0_D0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ 77, 78, 79, 80, }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -2627,18 +2455,11 @@ static const unsigned int sdhi0_wp_mux[] = { SDHI0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - 68, -}; -static const unsigned int sdhi1_data1_mux[] = { - SDHI1_D0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ 68, 69, 70, 71, }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK, }; static const unsigned int sdhi1_ctrl_pins[] = { @@ -2663,18 +2484,11 @@ static const unsigned int sdhi1_wp_mux[] = { SDHI1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - 205, -}; -static const unsigned int sdhi2_data1_mux[] = { - SDHI2_D0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:3] */ 205, 206, 207, 208, }; -static const unsigned int sdhi2_data4_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { @@ -2750,9 +2564,9 @@ static const unsigned int tpu0_to3_mux[] = { }; static const struct sh_pfc_pin_group pinmux_groups[] = { - SH_PFC_PIN_GROUP(bsc_data8), - SH_PFC_PIN_GROUP(bsc_data16), - SH_PFC_PIN_GROUP(bsc_data32), + BUS_DATA_PIN_GROUP(bsc_data, 8), + BUS_DATA_PIN_GROUP(bsc_data, 16), + BUS_DATA_PIN_GROUP(bsc_data, 32), SH_PFC_PIN_GROUP(bsc_cs0), SH_PFC_PIN_GROUP(bsc_cs2), SH_PFC_PIN_GROUP(bsc_cs4), @@ -2760,9 +2574,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(bsc_cs5a_1), SH_PFC_PIN_GROUP(bsc_cs5b), SH_PFC_PIN_GROUP(bsc_cs6a), - SH_PFC_PIN_GROUP(bsc_rd_we8), - SH_PFC_PIN_GROUP(bsc_rd_we16), - SH_PFC_PIN_GROUP(bsc_rd_we32), + SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we8, bsc_rd_we, 0, 2), + SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we16, bsc_rd_we, 0, 3), + SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we32, bsc_rd_we, 0, 5), SH_PFC_PIN_GROUP(bsc_bs), SH_PFC_PIN_GROUP(bsc_rdwr), SH_PFC_PIN_GROUP(ceu0_data_0_7), @@ -2847,11 +2661,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_irq30_1), SH_PFC_PIN_GROUP(intc_irq31_0), SH_PFC_PIN_GROUP(intc_irq31_1), - SH_PFC_PIN_GROUP(lcd0_data8), - SH_PFC_PIN_GROUP(lcd0_data9), - SH_PFC_PIN_GROUP(lcd0_data12), - SH_PFC_PIN_GROUP(lcd0_data16), - SH_PFC_PIN_GROUP(lcd0_data18), + SH_PFC_PIN_GROUP_SUBSET(lcd0_data8, lcd0_data24_0, 0, 8), + SH_PFC_PIN_GROUP_SUBSET(lcd0_data9, lcd0_data24_0, 0, 9), + SH_PFC_PIN_GROUP_SUBSET(lcd0_data12, lcd0_data24_0, 0, 12), + SH_PFC_PIN_GROUP_SUBSET(lcd0_data16, lcd0_data24_0, 0, 16), + SH_PFC_PIN_GROUP_SUBSET(lcd0_data18, lcd0_data24_0, 0, 18), SH_PFC_PIN_GROUP(lcd0_data24_0), SH_PFC_PIN_GROUP(lcd0_data24_1), SH_PFC_PIN_GROUP(lcd0_display), @@ -2859,23 +2673,23 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(lcd0_lclk_1), SH_PFC_PIN_GROUP(lcd0_sync), SH_PFC_PIN_GROUP(lcd0_sys), - SH_PFC_PIN_GROUP(lcd1_data8), - SH_PFC_PIN_GROUP(lcd1_data9), - SH_PFC_PIN_GROUP(lcd1_data12), - SH_PFC_PIN_GROUP(lcd1_data16), - SH_PFC_PIN_GROUP(lcd1_data18), - SH_PFC_PIN_GROUP(lcd1_data24), + BUS_DATA_PIN_GROUP(lcd1_data, 8), + BUS_DATA_PIN_GROUP(lcd1_data, 9), + BUS_DATA_PIN_GROUP(lcd1_data, 12), + BUS_DATA_PIN_GROUP(lcd1_data, 16), + BUS_DATA_PIN_GROUP(lcd1_data, 18), + BUS_DATA_PIN_GROUP(lcd1_data, 24), SH_PFC_PIN_GROUP(lcd1_display), SH_PFC_PIN_GROUP(lcd1_lclk), SH_PFC_PIN_GROUP(lcd1_sync), SH_PFC_PIN_GROUP(lcd1_sys), - SH_PFC_PIN_GROUP(mmc0_data1_0), - SH_PFC_PIN_GROUP(mmc0_data4_0), - SH_PFC_PIN_GROUP(mmc0_data8_0), + BUS_DATA_PIN_GROUP(mmc0_data, 1, _0), + BUS_DATA_PIN_GROUP(mmc0_data, 4, _0), + BUS_DATA_PIN_GROUP(mmc0_data, 8, _0), SH_PFC_PIN_GROUP(mmc0_ctrl_0), - SH_PFC_PIN_GROUP(mmc0_data1_1), - SH_PFC_PIN_GROUP(mmc0_data4_1), - SH_PFC_PIN_GROUP(mmc0_data8_1), + BUS_DATA_PIN_GROUP(mmc0_data, 1, _1), + BUS_DATA_PIN_GROUP(mmc0_data, 4, _1), + BUS_DATA_PIN_GROUP(mmc0_data, 8, _1), SH_PFC_PIN_GROUP(mmc0_ctrl_1), SH_PFC_PIN_GROUP(scifa0_data), SH_PFC_PIN_GROUP(scifa0_clk), @@ -2912,18 +2726,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scifb_data_1), SH_PFC_PIN_GROUP(scifb_clk_1), SH_PFC_PIN_GROUP(scifb_ctrl_1), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd_0), SH_PFC_PIN_GROUP(sdhi2_wp_0), @@ -3681,7 +3495,7 @@ static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = { { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 }, }; -static void __iomem *r8a7740_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin) +static int r8a7740_pin_to_portcr(unsigned int pin) { unsigned int i; @@ -3690,10 +3504,10 @@ static void __iomem *r8a7740_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin) &r8a7740_portcr_offsets[i]; if (pin <= group->end_pin) - return pfc->windows->virt + group->offset + pin; + return group->offset + pin; } - return NULL; + return -1; } static const struct sh_pfc_soc_operations r8a7740_pfc_ops = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77470.c b/drivers/pinctrl/renesas/pfc-r8a77470.c index e6e5487691c1..ee6e8fabab24 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77470.c +++ b/drivers/pinctrl/renesas/pfc-r8a77470.c @@ -1595,30 +1595,14 @@ static const unsigned int i2c4_e_mux[] = { SCL4_E_MARK, SDA4_E_MARK, }; /* - MMC -------------------------------------------------------------------- */ -static const unsigned int mmc_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(0, 15), -}; -static const unsigned int mmc_data1_mux[] = { - MMC0_D0_SDHI1_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16), - RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18), -}; -static const unsigned int mmc_data4_mux[] = { - MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK, - MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, -}; -static const unsigned int mmc_data8_pins[] = { +static const unsigned int mmc_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK, MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, MMC0_D4_MARK, MMC0_D5_MARK, @@ -1639,19 +1623,12 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { +static const unsigned int qspi0_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20), }; -static const unsigned int qspi0_data4_mux[] = { +static const unsigned int qspi0_data_mux[] = { QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK, }; @@ -1662,19 +1639,12 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { +static const unsigned int qspi1_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), }; -static const unsigned int qspi1_data4_mux[] = { +static const unsigned int qspi1_data_mux[] = { QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK, }; @@ -1917,19 +1887,12 @@ static const unsigned int scif_clk_b_mux[] = { SCIF_CLK_B_MARK, }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(0, 7), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -1954,29 +1917,6 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(0, 15), -}; -static const unsigned int sdhi1_data1_mux[] = { - MMC0_D0_SDHI1_D0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16), - RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18), -}; -static const unsigned int sdhi1_data4_mux[] = { - MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK, - MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, -}; -static const unsigned int sdhi1_ctrl_pins[] = { - /* CLK, CMD */ - RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), -}; -static const unsigned int sdhi1_ctrl_mux[] = { - MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK, -}; static const unsigned int sdhi1_cd_pins[] = { /* CD */ RCAR_GP_PIN(0, 19), @@ -1992,19 +1932,12 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 16), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DAT0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19), }; -static const unsigned int sdhi2_data4_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { @@ -2047,43 +1980,39 @@ static const unsigned int usb1_mux[] = { USB1_OVC_MARK, }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data vin0_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), - RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), - RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), - RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), - /* G */ - RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), - RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8), - RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), - /* R */ - RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), - RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), - RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), - RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19), - }, +static const unsigned int vin0_data_pins[] = { + /* B */ + RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), + RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), + RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), + RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), + /* G */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8), + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), + /* R */ + RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), + RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19), }; -static const union vin_data vin0_data_mux = { - .data24 = { - /* B */ - VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, - VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, - VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, - VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, - /* G */ - VI0_G0_MARK, VI0_G1_MARK, - VI0_G2_MARK, VI0_G3_MARK, - VI0_G4_MARK, VI0_G5_MARK, - VI0_G6_MARK, VI0_G7_MARK, - /* R */ - VI0_R0_MARK, VI0_R1_MARK, - VI0_R2_MARK, VI0_R3_MARK, - VI0_R4_MARK, VI0_R5_MARK, - VI0_R6_MARK, VI0_R7_MARK, - }, +static const unsigned int vin0_data_mux[] = { + /* B */ + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G0_MARK, VI0_G1_MARK, + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R0_MARK, VI0_R1_MARK, + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, }; static const unsigned int vin0_data18_pins[] = { /* B */ @@ -2140,25 +2069,21 @@ static const unsigned int vin0_clk_mux[] = { VI0_CLK_MARK, }; /* - VIN1 ------------------------------------------------------------------- */ -static const union vin_data vin1_data_pins = { - .data12 = { - RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), - RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), - RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), - RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), - RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), - RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), - }, +static const unsigned int vin1_data_pins[] = { + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), + RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), }; -static const union vin_data vin1_data_mux = { - .data12 = { - VI1_DATA0_MARK, VI1_DATA1_MARK, - VI1_DATA2_MARK, VI1_DATA3_MARK, - VI1_DATA4_MARK, VI1_DATA5_MARK, - VI1_DATA6_MARK, VI1_DATA7_MARK, - VI1_DATA8_MARK, VI1_DATA9_MARK, - VI1_DATA10_MARK, VI1_DATA11_MARK, - }, +static const unsigned int vin1_data_mux[] = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, + VI1_DATA8_MARK, VI1_DATA9_MARK, + VI1_DATA10_MARK, VI1_DATA11_MARK, }; static const unsigned int vin1_sync_pins[] = { RCAR_GP_PIN(3, 11), /* HSYNC */ @@ -2243,16 +2168,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c4_c), SH_PFC_PIN_GROUP(i2c4_d), SH_PFC_PIN_GROUP(i2c4_e), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_data_b), SH_PFC_PIN_GROUP(scif0_data_c), @@ -2286,37 +2211,37 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_data_f), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), - SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP_SUBSET(sdhi1_data1, mmc_data, 0, 1), + SH_PFC_PIN_GROUP_SUBSET(sdhi1_data4, mmc_data, 0, 4), + SH_PFC_PIN_GROUP_ALIAS(sdhi1_ctrl, mmc_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), + BUS_DATA_PIN_GROUP(vin0_data, 24), + BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 16), + BUS_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 8), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 12), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 8), + BUS_DATA_PIN_GROUP(vin1_data, 12), + BUS_DATA_PIN_GROUP(vin1_data, 10), + BUS_DATA_PIN_GROUP(vin1_data, 8), SH_PFC_PIN_GROUP(vin1_sync), SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), @@ -3420,8 +3345,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, - u32 *pocctrl) +static int r8a77470_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -3683,7 +3607,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ } }; -static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a77470_pfc_ops = { .pin_to_pocctrl = r8a77470_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -3692,7 +3616,7 @@ static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = { #ifdef CONFIG_PINCTRL_PFC_R8A77470 const struct sh_pfc_soc_info r8a77470_pinmux_info = { .name = "r8a77470_pfc", - .ops = &r8a77470_pinmux_ops, + .ops = &r8a77470_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a7778.c b/drivers/pinctrl/renesas/pfc-r8a7778.c index d641e408f1bd..a24672ca3c01 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7778.c +++ b/drivers/pinctrl/renesas/pfc-r8a7778.c @@ -1427,25 +1427,17 @@ I2C_PFC_MUX(i2c3_c, SDA3_C, SCL3_C); /* - MMC macro -------------------------------------------------------------- */ #define MMC_PFC_PINS(name, args...) SH_PFC_PINS(name, args) #define MMC_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd) -#define MMC_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0) -#define MMC_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3) #define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \ SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7) /* - MMC -------------------------------------------------------------------- */ MMC_PFC_PINS(mmc_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); MMC_PFC_CTRL(mmc_ctrl, MMC_CLK, MMC_CMD); -MMC_PFC_PINS(mmc_data1, RCAR_GP_PIN(1, 7)); -MMC_PFC_DAT1(mmc_data1, MMC_D0); -MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), - RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6)); -MMC_PFC_DAT4(mmc_data4, MMC_D0, MMC_D1, - MMC_D2, MMC_D3); -MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), +MMC_PFC_PINS(mmc_data, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0), RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31)); -MMC_PFC_DAT8(mmc_data8, MMC_D0, MMC_D1, +MMC_PFC_DAT8(mmc_data, MMC_D0, MMC_D1, MMC_D2, MMC_D3, MMC_D4, MMC_D5, MMC_D6, MMC_D7); @@ -1530,7 +1522,6 @@ SCIF_PFC_DAT(scif5_data_b, TX5_B, RX5_B); /* - SDHI macro ------------------------------------------------------------- */ #define SDHI_PFC_PINS(name, args...) SH_PFC_PINS(name, args) -#define SDHI_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0) #define SDHI_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3) #define SDHI_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd) #define SDHI_PFC_CDPN(name, cd) SH_PFC_MUX1(name, cd) @@ -1541,11 +1532,9 @@ SDHI_PFC_PINS(sdhi0_cd, RCAR_GP_PIN(3, 17)); SDHI_PFC_CDPN(sdhi0_cd, SD0_CD); SDHI_PFC_PINS(sdhi0_ctrl, RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12)); SDHI_PFC_CTRL(sdhi0_ctrl, SD0_CLK, SD0_CMD); -SDHI_PFC_PINS(sdhi0_data1, RCAR_GP_PIN(3, 13)); -SDHI_PFC_DAT1(sdhi0_data1, SD0_DAT0); -SDHI_PFC_PINS(sdhi0_data4, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), +SDHI_PFC_PINS(sdhi0_data, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16)); -SDHI_PFC_DAT4(sdhi0_data4, SD0_DAT0, SD0_DAT1, +SDHI_PFC_DAT4(sdhi0_data, SD0_DAT0, SD0_DAT1, SD0_DAT2, SD0_DAT3); SDHI_PFC_PINS(sdhi0_wp, RCAR_GP_PIN(3, 18)); SDHI_PFC_WPPN(sdhi0_wp, SD0_WP); @@ -1559,17 +1548,13 @@ SDHI_PFC_PINS(sdhi1_ctrl_a, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); SDHI_PFC_CTRL(sdhi1_ctrl_a, SD1_CLK_A, SD1_CMD_A); SDHI_PFC_PINS(sdhi1_ctrl_b, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16)); SDHI_PFC_CTRL(sdhi1_ctrl_b, SD1_CLK_B, SD1_CMD_B); -SDHI_PFC_PINS(sdhi1_data1_a, RCAR_GP_PIN(1, 7)); -SDHI_PFC_DAT1(sdhi1_data1_a, SD1_DAT0_A); -SDHI_PFC_PINS(sdhi1_data1_b, RCAR_GP_PIN(1, 18)); -SDHI_PFC_DAT1(sdhi1_data1_b, SD1_DAT0_B); -SDHI_PFC_PINS(sdhi1_data4_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), +SDHI_PFC_PINS(sdhi1_data_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6)); -SDHI_PFC_DAT4(sdhi1_data4_a, SD1_DAT0_A, SD1_DAT1_A, +SDHI_PFC_DAT4(sdhi1_data_a, SD1_DAT0_A, SD1_DAT1_A, SD1_DAT2_A, SD1_DAT3_A); -SDHI_PFC_PINS(sdhi1_data4_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), +SDHI_PFC_PINS(sdhi1_data_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); -SDHI_PFC_DAT4(sdhi1_data4_b, SD1_DAT0_B, SD1_DAT1_B, +SDHI_PFC_DAT4(sdhi1_data_b, SD1_DAT0_B, SD1_DAT1_B, SD1_DAT2_B, SD1_DAT3_B); SDHI_PFC_PINS(sdhi1_wp_a, RCAR_GP_PIN(0, 31)); SDHI_PFC_WPPN(sdhi1_wp_a, SD1_WP_A); @@ -1585,17 +1570,13 @@ SDHI_PFC_PINS(sdhi2_ctrl_a, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); SDHI_PFC_CTRL(sdhi2_ctrl_a, SD2_CLK_A, SD2_CMD_A); SDHI_PFC_PINS(sdhi2_ctrl_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6)); SDHI_PFC_CTRL(sdhi2_ctrl_b, SD2_CLK_B, SD2_CMD_B); -SDHI_PFC_PINS(sdhi2_data1_a, RCAR_GP_PIN(4, 19)); -SDHI_PFC_DAT1(sdhi2_data1_a, SD2_DAT0_A); -SDHI_PFC_PINS(sdhi2_data1_b, RCAR_GP_PIN(4, 7)); -SDHI_PFC_DAT1(sdhi2_data1_b, SD2_DAT0_B); -SDHI_PFC_PINS(sdhi2_data4_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), +SDHI_PFC_PINS(sdhi2_data_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22)); -SDHI_PFC_DAT4(sdhi2_data4_a, SD2_DAT0_A, SD2_DAT1_A, +SDHI_PFC_DAT4(sdhi2_data_a, SD2_DAT0_A, SD2_DAT1_A, SD2_DAT2_A, SD2_DAT3_A); -SDHI_PFC_PINS(sdhi2_data4_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), +SDHI_PFC_PINS(sdhi2_data_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26)); -SDHI_PFC_DAT4(sdhi2_data4_b, SD2_DAT0_B, SD2_DAT1_B, +SDHI_PFC_DAT4(sdhi2_data_b, SD2_DAT0_B, SD2_DAT1_B, SD2_DAT2_B, SD2_DAT3_B); SDHI_PFC_PINS(sdhi2_wp_a, RCAR_GP_PIN(4, 24)); SDHI_PFC_WPPN(sdhi2_wp_a, SD2_WP_A); @@ -1744,9 +1725,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c3_b), SH_PFC_PIN_GROUP(i2c3_c), SH_PFC_PIN_GROUP(mmc_ctrl), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(scif_clk), SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_data_b), @@ -1781,27 +1762,27 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_data_b), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_ctrl), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_wp), SH_PFC_PIN_GROUP(sdhi1_cd_a), SH_PFC_PIN_GROUP(sdhi1_cd_b), SH_PFC_PIN_GROUP(sdhi1_ctrl_a), SH_PFC_PIN_GROUP(sdhi1_ctrl_b), - SH_PFC_PIN_GROUP(sdhi1_data1_a), - SH_PFC_PIN_GROUP(sdhi1_data1_b), - SH_PFC_PIN_GROUP(sdhi1_data4_a), - SH_PFC_PIN_GROUP(sdhi1_data4_b), + BUS_DATA_PIN_GROUP(sdhi1_data, 1, _a), + BUS_DATA_PIN_GROUP(sdhi1_data, 1, _b), + BUS_DATA_PIN_GROUP(sdhi1_data, 4, _a), + BUS_DATA_PIN_GROUP(sdhi1_data, 4, _b), SH_PFC_PIN_GROUP(sdhi1_wp_a), SH_PFC_PIN_GROUP(sdhi1_wp_b), SH_PFC_PIN_GROUP(sdhi2_cd_a), SH_PFC_PIN_GROUP(sdhi2_cd_b), SH_PFC_PIN_GROUP(sdhi2_ctrl_a), SH_PFC_PIN_GROUP(sdhi2_ctrl_b), - SH_PFC_PIN_GROUP(sdhi2_data1_a), - SH_PFC_PIN_GROUP(sdhi2_data1_b), - SH_PFC_PIN_GROUP(sdhi2_data4_a), - SH_PFC_PIN_GROUP(sdhi2_data4_b), + BUS_DATA_PIN_GROUP(sdhi2_data, 1, _a), + BUS_DATA_PIN_GROUP(sdhi2_data, 1, _b), + BUS_DATA_PIN_GROUP(sdhi2_data, 4, _a), + BUS_DATA_PIN_GROUP(sdhi2_data, 4, _b), SH_PFC_PIN_GROUP(sdhi2_wp_a), SH_PFC_PIN_GROUP(sdhi2_wp_b), SH_PFC_PIN_GROUP(ssi012_ctrl), diff --git a/drivers/pinctrl/renesas/pfc-r8a7779.c b/drivers/pinctrl/renesas/pfc-r8a7779.c index 3e47cdc1411d..296b5fb0f349 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7779.c +++ b/drivers/pinctrl/renesas/pfc-r8a7779.c @@ -1928,28 +1928,13 @@ static const unsigned int lbsc_ex_cs5_mux[] = { EX_CS5_MARK, }; /* - MMCIF ------------------------------------------------------------------ */ -static const unsigned int mmc0_data1_pins[] = { - /* D[0] */ - RCAR_GP_PIN(0, 19), -}; -static const unsigned int mmc0_data1_mux[] = { - MMC0_D0_MARK, -}; -static const unsigned int mmc0_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), - RCAR_GP_PIN(0, 2), -}; -static const unsigned int mmc0_data4_mux[] = { - MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, -}; -static const unsigned int mmc0_data8_pins[] = { +static const unsigned int mmc0_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16), }; -static const unsigned int mmc0_data8_mux[] = { +static const unsigned int mmc0_data_mux[] = { MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, }; @@ -1960,28 +1945,13 @@ static const unsigned int mmc0_ctrl_pins[] = { static const unsigned int mmc0_ctrl_mux[] = { MMC0_CMD_MARK, MMC0_CLK_MARK, }; -static const unsigned int mmc1_data1_pins[] = { - /* D[0] */ - RCAR_GP_PIN(2, 8), -}; -static const unsigned int mmc1_data1_mux[] = { - MMC1_D0_MARK, -}; -static const unsigned int mmc1_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), - RCAR_GP_PIN(2, 11), -}; -static const unsigned int mmc1_data4_mux[] = { - MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, -}; -static const unsigned int mmc1_data8_pins[] = { +static const unsigned int mmc1_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), }; -static const unsigned int mmc1_data8_mux[] = { +static const unsigned int mmc1_data_mux[] = { MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, }; @@ -2386,19 +2356,12 @@ static const unsigned int scif_clk_d_mux[] = { SCIF_CLK_D_MARK, }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 21), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -2423,19 +2386,12 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(0, 19), -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 2), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; static const unsigned int sdhi1_ctrl_pins[] = { @@ -2460,19 +2416,12 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 1), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DAT0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), }; -static const unsigned int sdhi2_data4_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { @@ -2497,19 +2446,12 @@ static const unsigned int sdhi2_wp_mux[] = { SD2_WP_MARK, }; /* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(1, 18), -}; -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; -static const unsigned int sdhi3_data4_pins[] = { +static const unsigned int sdhi3_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21), }; -static const unsigned int sdhi3_data4_mux[] = { +static const unsigned int sdhi3_data_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, }; static const unsigned int sdhi3_ctrl_pins[] = { @@ -2749,13 +2691,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(lbsc_ex_cs3), SH_PFC_PIN_GROUP(lbsc_ex_cs4), SH_PFC_PIN_GROUP(lbsc_ex_cs5), - SH_PFC_PIN_GROUP(mmc0_data1), - SH_PFC_PIN_GROUP(mmc0_data4), - SH_PFC_PIN_GROUP(mmc0_data8), + BUS_DATA_PIN_GROUP(mmc0_data, 1), + BUS_DATA_PIN_GROUP(mmc0_data, 4), + BUS_DATA_PIN_GROUP(mmc0_data, 8), SH_PFC_PIN_GROUP(mmc0_ctrl), - SH_PFC_PIN_GROUP(mmc1_data1), - SH_PFC_PIN_GROUP(mmc1_data4), - SH_PFC_PIN_GROUP(mmc1_data8), + BUS_DATA_PIN_GROUP(mmc1_data, 1), + BUS_DATA_PIN_GROUP(mmc1_data, 4), + BUS_DATA_PIN_GROUP(mmc1_data, 8), SH_PFC_PIN_GROUP(mmc1_ctrl), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), @@ -2812,23 +2754,23 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif_clk_b), SH_PFC_PIN_GROUP(scif_clk_c), SH_PFC_PIN_GROUP(scif_clk_d), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), + BUS_DATA_PIN_GROUP(sdhi3_data, 1), + BUS_DATA_PIN_GROUP(sdhi3_data, 4), SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), @@ -3133,10 +3075,6 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(lbsc), SH_PFC_FUNCTION(mmc0), SH_PFC_FUNCTION(mmc1), - SH_PFC_FUNCTION(sdhi0), - SH_PFC_FUNCTION(sdhi1), - SH_PFC_FUNCTION(sdhi2), - SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), @@ -3144,6 +3082,10 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb2), diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c index 08c0a23edf68..9db9e61d96bc 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7790.c +++ b/drivers/pinctrl/renesas/pfc-r8a7790.c @@ -194,24 +194,24 @@ enum { FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, - FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK, + FN_WE0_N, FN_IECLK, FN_CAN_CLK, FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, - FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, + FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, FN_SSI_WS78_B, /* IPSR6 */ - FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, + FN_DACK0, FN_IRQ0, FN_SSI_SCK6_B, FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1, - FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C, + FN_SSI_WS6_B, FN_SSI_SDATA8_C, FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, - FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, + FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, FN_ETH_CRS_DV, FN_STP_ISCLK_0_B, FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, @@ -568,23 +568,23 @@ enum { CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, - INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, + WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK, WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK, VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK, - IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK, + IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK, MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK, VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK, SSI_WS78_B_MARK, - DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, + DACK0_MARK, IRQ0_MARK, SSI_SCK6_B_MARK, VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK, - INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, + SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, - MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, + MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK, TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK, @@ -1094,7 +1094,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1), PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5), PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1), - PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N), PINMUX_IPSR_GPSR(IP5_20_18, WE0_N), PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0), PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0), @@ -1111,7 +1110,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2), PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0), PINMUX_IPSR_GPSR(IP5_26_24, IRQ3), - PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N), PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0), PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1), PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1), @@ -1125,7 +1123,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP6_2_0, DACK0), PINMUX_IPSR_GPSR(IP6_2_0, IRQ0), - PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N), PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), @@ -1137,7 +1134,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), PINMUX_IPSR_GPSR(IP6_8_6, DACK1), PINMUX_IPSR_GPSR(IP6_8_6, IRQ1), - PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N), PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N), @@ -1146,7 +1142,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), PINMUX_IPSR_GPSR(IP6_13_11, DACK2), PINMUX_IPSR_GPSR(IP6_13_11, IRQ2), - PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N), PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), @@ -2410,29 +2405,14 @@ static const unsigned int mlb_3pin_mux[] = { #endif /* CONFIG_PINCTRL_PFC_R8A7790 */ /* - MMCIF0 ----------------------------------------------------------------- */ -static const unsigned int mmc0_data1_pins[] = { - /* D[0] */ - RCAR_GP_PIN(3, 18), -}; -static const unsigned int mmc0_data1_mux[] = { - MMC0_D0_MARK, -}; -static const unsigned int mmc0_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), - RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), -}; -static const unsigned int mmc0_data4_mux[] = { - MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, -}; -static const unsigned int mmc0_data8_pins[] = { +static const unsigned int mmc0_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), }; -static const unsigned int mmc0_data8_mux[] = { +static const unsigned int mmc0_data_mux[] = { MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, }; @@ -2444,29 +2424,14 @@ static const unsigned int mmc0_ctrl_mux[] = { MMC0_CLK_MARK, MMC0_CMD_MARK, }; /* - MMCIF1 ----------------------------------------------------------------- */ -static const unsigned int mmc1_data1_pins[] = { - /* D[0] */ - RCAR_GP_PIN(3, 26), -}; -static const unsigned int mmc1_data1_mux[] = { - MMC1_D0_MARK, -}; -static const unsigned int mmc1_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), - RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), -}; -static const unsigned int mmc1_data4_mux[] = { - MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, -}; -static const unsigned int mmc1_data8_pins[] = { +static const unsigned int mmc1_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), }; -static const unsigned int mmc1_data8_mux[] = { +static const unsigned int mmc1_data_mux[] = { MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, }; @@ -2813,19 +2778,12 @@ static const unsigned int qspi_ctrl_pins[] = { static const unsigned int qspi_ctrl_mux[] = { SPCLK_MARK, SSL_MARK, }; -static const unsigned int qspi_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), -}; -static const unsigned int qspi_data2_mux[] = { - MOSI_IO0_MARK, MISO_IO1_MARK, -}; -static const unsigned int qspi_data4_pins[] = { +static const unsigned int qspi_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), }; -static const unsigned int qspi_data4_mux[] = { +static const unsigned int qspi_data_mux[] = { MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, }; /* - SCIF0 ------------------------------------------------------------------ */ @@ -3322,18 +3280,11 @@ static const unsigned int scif_clk_b_mux[] = { SCIF_CLK_B_MARK, }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -3358,18 +3309,11 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 10), -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; static const unsigned int sdhi1_ctrl_pins[] = { @@ -3394,18 +3338,11 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 18), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DAT0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), }; -static const unsigned int sdhi2_data4_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { @@ -3430,18 +3367,11 @@ static const unsigned int sdhi2_wp_mux[] = { SD2_WP_MARK, }; /* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 26), -}; -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; -static const unsigned int sdhi3_data4_pins[] = { +static const unsigned int sdhi3_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), }; -static const unsigned int sdhi3_data4_mux[] = { +static const unsigned int sdhi3_data_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, }; static const unsigned int sdhi3_ctrl_pins[] = { @@ -3679,18 +3609,11 @@ static const unsigned int tpu0_to3_mux[] = { }; /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { - /* PWEN, OVC/VBUS */ - RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), + /* OVC/VBUS, PWEN */ + RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 18), }; static const unsigned int usb0_mux[] = { - USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, -}; -static const unsigned int usb0_ovc_vbus_pins[] = { - /* OVC/VBUS */ - RCAR_GP_PIN(5, 19), -}; -static const unsigned int usb0_ovc_vbus_mux[] = { - USB0_OVC_VBUS_MARK, + USB0_OVC_VBUS_MARK, USB0_PWEN_MARK, }; /* - USB1 ------------------------------------------------------------------- */ static const unsigned int usb1_pins[] = { @@ -3700,13 +3623,6 @@ static const unsigned int usb1_pins[] = { static const unsigned int usb1_mux[] = { USB1_PWEN_MARK, USB1_OVC_MARK, }; -static const unsigned int usb1_pwen_pins[] = { - /* PWEN */ - RCAR_GP_PIN(5, 20), -}; -static const unsigned int usb1_pwen_mux[] = { - USB1_PWEN_MARK, -}; /* - USB2 ------------------------------------------------------------------- */ static const unsigned int usb2_pins[] = { /* PWEN, OVC */ @@ -3716,43 +3632,39 @@ static const unsigned int usb2_mux[] = { USB2_PWEN_MARK, USB2_OVC_MARK, }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data vin0_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), - RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), - RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), - RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), - /* G */ - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), - RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - /* R */ - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), - RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), - }, +static const unsigned int vin0_data_pins[] = { + /* B */ + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), + /* G */ + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + /* R */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), + RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), }; -static const union vin_data vin0_data_mux = { - .data24 = { - /* B */ - VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, - VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, - VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, - VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, - /* G */ - VI0_G0_MARK, VI0_G1_MARK, - VI0_G2_MARK, VI0_G3_MARK, - VI0_G4_MARK, VI0_G5_MARK, - VI0_G6_MARK, VI0_G7_MARK, - /* R */ - VI0_R0_MARK, VI0_R1_MARK, - VI0_R2_MARK, VI0_R3_MARK, - VI0_R4_MARK, VI0_R5_MARK, - VI0_R6_MARK, VI0_R7_MARK, - }, +static const unsigned int vin0_data_mux[] = { + /* B */ + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G0_MARK, VI0_G1_MARK, + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R0_MARK, VI0_R1_MARK, + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, }; static const unsigned int vin0_data18_pins[] = { /* B */ @@ -3809,43 +3721,39 @@ static const unsigned int vin0_clk_mux[] = { VI0_CLK_MARK, }; /* - VIN1 ------------------------------------------------------------------- */ -static const union vin_data vin1_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), - RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), - RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), - RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), - /* G */ - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), - RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), - RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), - /* R */ - RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), - RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), - RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), - RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), - }, +static const unsigned int vin1_data_pins[] = { + /* B */ + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), + RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), + /* G */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), }; -static const union vin_data vin1_data_mux = { - .data24 = { - /* B */ - VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, - VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, - VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, - VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, - /* G */ - VI1_G0_MARK, VI1_G1_MARK, - VI1_G2_MARK, VI1_G3_MARK, - VI1_G4_MARK, VI1_G5_MARK, - VI1_G6_MARK, VI1_G7_MARK, - /* R */ - VI1_R0_MARK, VI1_R1_MARK, - VI1_R2_MARK, VI1_R3_MARK, - VI1_R4_MARK, VI1_R5_MARK, - VI1_R6_MARK, VI1_R7_MARK, - }, +static const unsigned int vin1_data_mux[] = { + /* B */ + VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, + VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, + VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, + VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, + /* G */ + VI1_G0_MARK, VI1_G1_MARK, + VI1_G2_MARK, VI1_G3_MARK, + VI1_G4_MARK, VI1_G5_MARK, + VI1_G6_MARK, VI1_G7_MARK, + /* R */ + VI1_R0_MARK, VI1_R1_MARK, + VI1_R2_MARK, VI1_R3_MARK, + VI1_R4_MARK, VI1_R5_MARK, + VI1_R6_MARK, VI1_R7_MARK, }; static const unsigned int vin1_data18_pins[] = { /* B */ @@ -3875,43 +3783,39 @@ static const unsigned int vin1_data18_mux[] = { VI1_R4_MARK, VI1_R5_MARK, VI1_R6_MARK, VI1_R7_MARK, }; -static const union vin_data vin1_data_b_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), - RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), - RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), - RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), - /* G */ - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), - RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), - RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), - /* R */ - RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), - RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), - RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), - RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), - }, +static const unsigned int vin1_data_b_pins[] = { + /* B */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), + /* G */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), }; -static const union vin_data vin1_data_b_mux = { - .data24 = { - /* B */ - VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK, - VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK, - VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK, - VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK, - /* G */ - VI1_G0_B_MARK, VI1_G1_B_MARK, - VI1_G2_B_MARK, VI1_G3_B_MARK, - VI1_G4_B_MARK, VI1_G5_B_MARK, - VI1_G6_B_MARK, VI1_G7_B_MARK, - /* R */ - VI1_R0_B_MARK, VI1_R1_B_MARK, - VI1_R2_B_MARK, VI1_R3_B_MARK, - VI1_R4_B_MARK, VI1_R5_B_MARK, - VI1_R6_B_MARK, VI1_R7_B_MARK, - }, +static const unsigned int vin1_data_b_mux[] = { + /* B */ + VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK, + VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK, + VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK, + VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK, + /* G */ + VI1_G0_B_MARK, VI1_G1_B_MARK, + VI1_G2_B_MARK, VI1_G3_B_MARK, + VI1_G4_B_MARK, VI1_G5_B_MARK, + VI1_G6_B_MARK, VI1_G7_B_MARK, + /* R */ + VI1_R0_B_MARK, VI1_R1_B_MARK, + VI1_R2_B_MARK, VI1_R3_B_MARK, + VI1_R4_B_MARK, VI1_R5_B_MARK, + VI1_R6_B_MARK, VI1_R7_B_MARK, }; static const unsigned int vin1_data18_b_pins[] = { /* B */ @@ -3994,83 +3898,67 @@ static const unsigned int vin1_clk_b_mux[] = { VI1_CLK_B_MARK, }; /* - VIN2 ----------------------------------------------------------------- */ -static const union vin_data vin2_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), - RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), - /* G */ - RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), - RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - /* R */ - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), - RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), - }, -}; -static const union vin_data vin2_data_mux = { - .data24 = { - /* B */ - VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, - VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, - VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, - VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, - /* G */ - VI2_G0_MARK, VI2_G1_MARK, - VI2_G2_MARK, VI2_G3_MARK, - VI2_G4_MARK, VI2_G5_MARK, - VI2_G6_MARK, VI2_G7_MARK, - /* R */ - VI2_R0_MARK, VI2_R1_MARK, - VI2_R2_MARK, VI2_R3_MARK, - VI2_R4_MARK, VI2_R5_MARK, - VI2_R6_MARK, VI2_R7_MARK, - }, -}; -static const unsigned int vin2_data18_pins[] = { +static const unsigned int vin2_data_pins[] = { /* B */ + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), /* G */ + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), /* R */ + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), }; -static const unsigned int vin2_data18_mux[] = { +static const unsigned int vin2_data_mux[] = { /* B */ + VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, /* G */ + VI2_G0_MARK, VI2_G1_MARK, VI2_G2_MARK, VI2_G3_MARK, VI2_G4_MARK, VI2_G5_MARK, VI2_G6_MARK, VI2_G7_MARK, /* R */ + VI2_R0_MARK, VI2_R1_MARK, VI2_R2_MARK, VI2_R3_MARK, VI2_R4_MARK, VI2_R5_MARK, VI2_R6_MARK, VI2_R7_MARK, }; -static const unsigned int vin2_g8_pins[] = { - RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), +static const unsigned int vin2_data18_pins[] = { + /* B */ + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + /* G */ RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), }; -static const unsigned int vin2_g8_mux[] = { - VI2_G0_MARK, VI2_G1_MARK, +static const unsigned int vin2_data18_mux[] = { + /* B */ + VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, + VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, + VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, + /* G */ VI2_G2_MARK, VI2_G3_MARK, VI2_G4_MARK, VI2_G5_MARK, VI2_G6_MARK, VI2_G7_MARK, + /* R */ + VI2_R2_MARK, VI2_R3_MARK, + VI2_R4_MARK, VI2_R5_MARK, + VI2_R6_MARK, VI2_R7_MARK, }; static const unsigned int vin2_sync_pins[] = { RCAR_GP_PIN(1, 16), /* HSYNC */ @@ -4223,13 +4111,13 @@ static const struct { SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), SH_PFC_PIN_GROUP(intc_irq3), - SH_PFC_PIN_GROUP(mmc0_data1), - SH_PFC_PIN_GROUP(mmc0_data4), - SH_PFC_PIN_GROUP(mmc0_data8), + BUS_DATA_PIN_GROUP(mmc0_data, 1), + BUS_DATA_PIN_GROUP(mmc0_data, 4), + BUS_DATA_PIN_GROUP(mmc0_data, 8), SH_PFC_PIN_GROUP(mmc0_ctrl), - SH_PFC_PIN_GROUP(mmc1_data1), - SH_PFC_PIN_GROUP(mmc1_data4), - SH_PFC_PIN_GROUP(mmc1_data8), + BUS_DATA_PIN_GROUP(mmc1_data, 1), + BUS_DATA_PIN_GROUP(mmc1_data, 4), + BUS_DATA_PIN_GROUP(mmc1_data, 8), SH_PFC_PIN_GROUP(mmc1_ctrl), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), @@ -4279,8 +4167,8 @@ static const struct { SH_PFC_PIN_GROUP(pwm5), SH_PFC_PIN_GROUP(pwm6), SH_PFC_PIN_GROUP(qspi_ctrl), - SH_PFC_PIN_GROUP(qspi_data2), - SH_PFC_PIN_GROUP(qspi_data4), + BUS_DATA_PIN_GROUP(qspi_data, 2), + BUS_DATA_PIN_GROUP(qspi_data, 4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -4350,23 +4238,23 @@ static const struct { SH_PFC_PIN_GROUP(scifb2_data_c), SH_PFC_PIN_GROUP(scif_clk), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), + BUS_DATA_PIN_GROUP(sdhi3_data, 1), + BUS_DATA_PIN_GROUP(sdhi3_data, 4), SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), @@ -4401,38 +4289,38 @@ static const struct { SH_PFC_PIN_GROUP(tpu0_to2), SH_PFC_PIN_GROUP(tpu0_to3), SH_PFC_PIN_GROUP(usb0), - SH_PFC_PIN_GROUP(usb0_ovc_vbus), + SH_PFC_PIN_GROUP_SUBSET(usb0_ovc_vbus, usb0, 0, 1), SH_PFC_PIN_GROUP(usb1), - SH_PFC_PIN_GROUP(usb1_pwen), + SH_PFC_PIN_GROUP_SUBSET(usb1_pwen, usb1, 0, 1), SH_PFC_PIN_GROUP(usb2), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), + BUS_DATA_PIN_GROUP(vin0_data, 24), + BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), - VIN_DATA_PIN_GROUP(vin0_data, 4), + BUS_DATA_PIN_GROUP(vin0_data, 16), + BUS_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 4), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 24), - VIN_DATA_PIN_GROUP(vin1_data, 20), + BUS_DATA_PIN_GROUP(vin1_data, 24), + BUS_DATA_PIN_GROUP(vin1_data, 20), SH_PFC_PIN_GROUP(vin1_data18), - VIN_DATA_PIN_GROUP(vin1_data, 16), - VIN_DATA_PIN_GROUP(vin1_data, 12), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 8), - VIN_DATA_PIN_GROUP(vin1_data, 4), - VIN_DATA_PIN_GROUP(vin1_data, 24, _b), - VIN_DATA_PIN_GROUP(vin1_data, 20, _b), + BUS_DATA_PIN_GROUP(vin1_data, 16), + BUS_DATA_PIN_GROUP(vin1_data, 12), + BUS_DATA_PIN_GROUP(vin1_data, 10), + BUS_DATA_PIN_GROUP(vin1_data, 8), + BUS_DATA_PIN_GROUP(vin1_data, 4), + BUS_DATA_PIN_GROUP(vin1_data, 24, _b), + BUS_DATA_PIN_GROUP(vin1_data, 20, _b), SH_PFC_PIN_GROUP(vin1_data18_b), - VIN_DATA_PIN_GROUP(vin1_data, 16, _b), - VIN_DATA_PIN_GROUP(vin1_data, 12, _b), - VIN_DATA_PIN_GROUP(vin1_data, 10, _b), - VIN_DATA_PIN_GROUP(vin1_data, 8, _b), - VIN_DATA_PIN_GROUP(vin1_data, 4, _b), + BUS_DATA_PIN_GROUP(vin1_data, 16, _b), + BUS_DATA_PIN_GROUP(vin1_data, 12, _b), + BUS_DATA_PIN_GROUP(vin1_data, 10, _b), + BUS_DATA_PIN_GROUP(vin1_data, 8, _b), + BUS_DATA_PIN_GROUP(vin1_data, 4, _b), SH_PFC_PIN_GROUP(vin1_sync), SH_PFC_PIN_GROUP(vin1_sync_b), SH_PFC_PIN_GROUP(vin1_field), @@ -4441,12 +4329,12 @@ static const struct { SH_PFC_PIN_GROUP(vin1_clkenb_b), SH_PFC_PIN_GROUP(vin1_clk), SH_PFC_PIN_GROUP(vin1_clk_b), - VIN_DATA_PIN_GROUP(vin2_data, 24), + BUS_DATA_PIN_GROUP(vin2_data, 24), SH_PFC_PIN_GROUP(vin2_data18), - VIN_DATA_PIN_GROUP(vin2_data, 16), - VIN_DATA_PIN_GROUP(vin2_data, 8), - VIN_DATA_PIN_GROUP(vin2_data, 4), - SH_PFC_PIN_GROUP(vin2_g8), + BUS_DATA_PIN_GROUP(vin2_data, 16), + BUS_DATA_PIN_GROUP(vin2_data, 8), + BUS_DATA_PIN_GROUP(vin2_data, 4), + SH_PFC_PIN_GROUP_SUBSET(vin2_g8, vin2_data, 8, 8), SH_PFC_PIN_GROUP(vin2_sync), SH_PFC_PIN_GROUP(vin2_field), SH_PFC_PIN_GROUP(vin2_clkenb), @@ -4964,10 +4852,10 @@ static const struct { .common = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), - SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(du2), @@ -5415,9 +5303,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0, /* IP5_26_24 [3] */ - FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, - FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, - FN_MSIOF0_SCK_B, 0, + FN_EX_WAIT0, FN_IRQ3, 0, FN_VI3_CLK, FN_SCIFA0_RTS_N_B, + FN_HRX0_B, FN_MSIOF0_SCK_B, 0, /* IP5_23_21 [3] */ FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C, @@ -5426,7 +5313,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0, /* IP5_17_15 [3] */ FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, - FN_INTC_IRQ4_N, 0, 0, + 0, 0, 0, /* IP5_14_13 [2] */ FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0, /* IP5_12_10 [3] */ @@ -5467,19 +5354,18 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, FN_I2C2_SCL_E, 0, /* IP6_13_11 [3] */ - FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, - FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, + FN_DACK2, FN_IRQ2, 0, FN_SSI_SDATA6_B, FN_HRTS0_N_B, + FN_MSIOF0_RXD_B, 0, 0, /* IP6_10_9 [2] */ FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B, /* IP6_8_6 [3] */ - FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B, - FN_SSI_SDATA8_C, 0, 0, 0, + FN_DACK1, FN_IRQ1, 0, FN_SSI_WS6_B, FN_SSI_SDATA8_C, 0, 0, 0, /* IP6_5_3 [3] */ FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, /* IP6_2_0 [3] */ - FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, - FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, )) + FN_DACK0, FN_IRQ0, 0, FN_SSI_SCK6_B, FN_VI1_VSYNC_N, + FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3), @@ -5987,7 +5873,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a7790_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31)) return -EINVAL; @@ -6289,7 +6175,7 @@ static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc) return 0; } -static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a7790_pfc_ops = { .init = r8a7790_pinmux_soc_init, .pin_to_pocctrl = r8a7790_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, @@ -6299,7 +6185,7 @@ static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = { #ifdef CONFIG_PINCTRL_PFC_R8A7742 const struct sh_pfc_soc_info r8a7742_pinmux_info = { .name = "r8a77420_pfc", - .ops = &r8a7790_pinmux_ops, + .ops = &r8a7790_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -6322,7 +6208,7 @@ const struct sh_pfc_soc_info r8a7742_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A7790 const struct sh_pfc_soc_info r8a7790_pinmux_info = { .name = "r8a77900_pfc", - .ops = &r8a7790_pinmux_ops, + .ops = &r8a7790_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c index fe4ccab6b0b8..076a8b7d71de 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7791.c +++ b/drivers/pinctrl/renesas/pfc-r8a7791.c @@ -234,11 +234,11 @@ enum { FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, FN_SCIFA2_RXD, FN_FMIN_E, FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, - FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, - FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, - FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, - FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, - FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N, + FN_IRQ0, FN_SCIFB1_RXD_D, + FN_IRQ1, FN_SCIFB1_SCK_C, + FN_IRQ2, FN_SCIFB1_TXD_D, + FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, + FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E, FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E, FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D, @@ -606,12 +606,12 @@ enum { AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK, SCIFA2_RXD_MARK, FMIN_E_MARK, AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK, - IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK, - IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK, - IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK, - IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK, + IRQ0_MARK, SCIFB1_RXD_D_MARK, + IRQ1_MARK, SCIFB1_SCK_C_MARK, + IRQ2_MARK, SCIFB1_TXD_D_MARK, + IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK, - MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK, + MSIOF2_RXD_E_MARK, IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK, IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK, I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK, @@ -1140,22 +1140,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0), PINMUX_IPSR_GPSR(IP6_9_8, IRQ0), PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3), - PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N), PINMUX_IPSR_GPSR(IP6_11_10, IRQ1), PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2), - PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N), PINMUX_IPSR_GPSR(IP6_13_12, IRQ2), PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3), - PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N), PINMUX_IPSR_GPSR(IP6_15_14, IRQ3), PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2), PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4), - PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N), PINMUX_IPSR_GPSR(IP6_18_16, IRQ4), PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2), PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2), PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4), - PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N), PINMUX_IPSR_GPSR(IP6_20_19, IRQ5), PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2), PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4), @@ -2303,13 +2298,6 @@ static const unsigned int hscif1_data_d_pins[] = { static const unsigned int hscif1_data_d_mux[] = { HRX1_D_MARK, HTX1_D_MARK, }; -static const unsigned int hscif1_data_e_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), -}; -static const unsigned int hscif1_data_e_mux[] = { - HRX1_C_MARK, HTX1_C_MARK, -}; static const unsigned int hscif1_clk_e_pins[] = { /* SCK */ RCAR_GP_PIN(2, 6), @@ -2604,40 +2592,25 @@ static const unsigned int mlb_3pin_mux[] = { #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ /* - MMCIF ------------------------------------------------------------------ */ -static const unsigned int mmc_data1_pins[] = { - /* D[0] */ - RCAR_GP_PIN(6, 18), -}; -static const unsigned int mmc_data1_mux[] = { - MMC_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), - RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), -}; -static const unsigned int mmc_data4_mux[] = { - MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, -}; -static const unsigned int mmc_data8_pins[] = { +static const unsigned int mmc_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, }; -static const unsigned int mmc_data8_b_pins[] = { +static const unsigned int mmc_data_b_pins[] = { /* D[0:7] */ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), }; -static const unsigned int mmc_data8_b_mux[] = { +static const unsigned int mmc_data_b_mux[] = { MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK, }; @@ -3225,19 +3198,12 @@ static const unsigned int qspi_ctrl_pins[] = { static const unsigned int qspi_ctrl_mux[] = { SPCLK_MARK, SSL_MARK, }; -static const unsigned int qspi_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), -}; -static const unsigned int qspi_data2_mux[] = { - MOSI_IO0_MARK, MISO_IO1_MARK, -}; -static const unsigned int qspi_data4_pins[] = { +static const unsigned int qspi_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), }; -static const unsigned int qspi_data4_mux[] = { +static const unsigned int qspi_data_mux[] = { MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, }; @@ -3248,19 +3214,12 @@ static const unsigned int qspi_ctrl_b_pins[] = { static const unsigned int qspi_ctrl_b_mux[] = { SPCLK_B_MARK, SSL_B_MARK, }; -static const unsigned int qspi_data2_b_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), -}; -static const unsigned int qspi_data2_b_mux[] = { - MOSI_IO0_B_MARK, MISO_IO1_B_MARK, -}; -static const unsigned int qspi_data4_b_pins[] = { +static const unsigned int qspi_data_b_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4), }; -static const unsigned int qspi_data4_b_mux[] = { +static const unsigned int qspi_data_b_mux[] = { MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK, }; /* - SCIF0 ------------------------------------------------------------------ */ @@ -3821,19 +3780,12 @@ static const unsigned int scif_clk_b_mux[] = { }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 2), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DATA0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -3858,19 +3810,12 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 10), -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DATA0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK, }; static const unsigned int sdhi1_ctrl_pins[] = { @@ -3895,19 +3840,12 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 18), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DATA0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), }; -static const unsigned int sdhi2_data4_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { @@ -4230,43 +4168,39 @@ static const unsigned int usb1_mux[] = { USB1_OVC_MARK, }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data vin0_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6), - RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), - RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), - RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), - /* G */ - RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), - RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), - RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), - RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), - /* R */ - RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22), - RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), - RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), - RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), - }, +static const unsigned int vin0_data_pins[] = { + /* B */ + RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6), + RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), + /* G */ + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), + RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), + RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), + /* R */ + RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22), + RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), + RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), }; -static const union vin_data vin0_data_mux = { - .data24 = { - /* B */ - VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, - VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, - VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, - VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, - /* G */ - VI0_G0_MARK, VI0_G1_MARK, - VI0_G2_MARK, VI0_G3_MARK, - VI0_G4_MARK, VI0_G5_MARK, - VI0_G6_MARK, VI0_G7_MARK, - /* R */ - VI0_R0_MARK, VI0_R1_MARK, - VI0_R2_MARK, VI0_R3_MARK, - VI0_R4_MARK, VI0_R5_MARK, - VI0_R6_MARK, VI0_R7_MARK, - }, +static const unsigned int vin0_data_mux[] = { + /* B */ + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G0_MARK, VI0_G1_MARK, + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R0_MARK, VI0_R1_MARK, + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, }; static const unsigned int vin0_data18_pins[] = { /* B */ @@ -4361,43 +4295,39 @@ static const unsigned int vin1_clk_pins[] = { static const unsigned int vin1_clk_mux[] = { VI1_CLK_MARK, }; -static const union vin_data vin1_data_b_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), - RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), - RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), - RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), - /* G */ - RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), - RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), - RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), - RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22), - /* R */ - RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), - RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), - RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), - RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), - }, +static const unsigned int vin1_data_b_pins[] = { + /* B */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), + /* G */ + RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), + RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), + RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22), + /* R */ + RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), }; -static const union vin_data vin1_data_b_mux = { - .data24 = { - /* B */ - VI1_DATA0_B_MARK, VI1_DATA1_B_MARK, - VI1_DATA2_B_MARK, VI1_DATA3_B_MARK, - VI1_DATA4_B_MARK, VI1_DATA5_B_MARK, - VI1_DATA6_B_MARK, VI1_DATA7_B_MARK, - /* G */ - VI1_G0_B_MARK, VI1_G1_B_MARK, - VI1_G2_B_MARK, VI1_G3_B_MARK, - VI1_G4_B_MARK, VI1_G5_B_MARK, - VI1_G6_B_MARK, VI1_G7_B_MARK, - /* R */ - VI1_R0_B_MARK, VI1_R1_B_MARK, - VI1_R2_B_MARK, VI1_R3_B_MARK, - VI1_R4_B_MARK, VI1_R5_B_MARK, - VI1_R6_B_MARK, VI1_R7_B_MARK, - }, +static const unsigned int vin1_data_b_mux[] = { + /* B */ + VI1_DATA0_B_MARK, VI1_DATA1_B_MARK, + VI1_DATA2_B_MARK, VI1_DATA3_B_MARK, + VI1_DATA4_B_MARK, VI1_DATA5_B_MARK, + VI1_DATA6_B_MARK, VI1_DATA7_B_MARK, + /* G */ + VI1_G0_B_MARK, VI1_G1_B_MARK, + VI1_G2_B_MARK, VI1_G3_B_MARK, + VI1_G4_B_MARK, VI1_G5_B_MARK, + VI1_G6_B_MARK, VI1_G7_B_MARK, + /* R */ + VI1_R0_B_MARK, VI1_R1_B_MARK, + VI1_R2_B_MARK, VI1_R3_B_MARK, + VI1_R4_B_MARK, VI1_R5_B_MARK, + VI1_R6_B_MARK, VI1_R7_B_MARK, }; static const unsigned int vin1_data18_b_pins[] = { /* B */ @@ -4556,7 +4486,7 @@ static const struct { SH_PFC_PIN_GROUP(hscif1_clk_c), SH_PFC_PIN_GROUP(hscif1_ctrl_c), SH_PFC_PIN_GROUP(hscif1_data_d), - SH_PFC_PIN_GROUP(hscif1_data_e), + SH_PFC_PIN_GROUP_ALIAS(hscif1_data_e, hscif1_data_c), SH_PFC_PIN_GROUP(hscif1_clk_e), SH_PFC_PIN_GROUP(hscif1_ctrl_e), SH_PFC_PIN_GROUP(hscif2_data), @@ -4596,10 +4526,10 @@ static const struct { SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), SH_PFC_PIN_GROUP(intc_irq3), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), - SH_PFC_PIN_GROUP(mmc_data8_b), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), + BUS_DATA_PIN_GROUP(mmc_data, 8, _b), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), @@ -4683,11 +4613,11 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6), SH_PFC_PIN_GROUP(qspi_ctrl), - SH_PFC_PIN_GROUP(qspi_data2), - SH_PFC_PIN_GROUP(qspi_data4), + BUS_DATA_PIN_GROUP(qspi_data, 2), + BUS_DATA_PIN_GROUP(qspi_data, 4), SH_PFC_PIN_GROUP(qspi_ctrl_b), - SH_PFC_PIN_GROUP(qspi_data2_b), - SH_PFC_PIN_GROUP(qspi_data4_b), + BUS_DATA_PIN_GROUP(qspi_data, 2, _b), + BUS_DATA_PIN_GROUP(qspi_data, 4, _b), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_data_b), SH_PFC_PIN_GROUP(scif0_data_c), @@ -4765,18 +4695,18 @@ static const struct { SH_PFC_PIN_GROUP(scifb2_data_d), SH_PFC_PIN_GROUP(scif_clk), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), @@ -4814,13 +4744,13 @@ static const struct { SH_PFC_PIN_GROUP(tpu_to3), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), + BUS_DATA_PIN_GROUP(vin0_data, 24), + BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 16), + BUS_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 8), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), @@ -4830,13 +4760,13 @@ static const struct { SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), SH_PFC_PIN_GROUP(vin1_clk), - VIN_DATA_PIN_GROUP(vin1_data, 24, _b), - VIN_DATA_PIN_GROUP(vin1_data, 20, _b), + BUS_DATA_PIN_GROUP(vin1_data, 24, _b), + BUS_DATA_PIN_GROUP(vin1_data, 20, _b), SH_PFC_PIN_GROUP(vin1_data18_b), - VIN_DATA_PIN_GROUP(vin1_data, 16, _b), - VIN_DATA_PIN_GROUP(vin1_data, 12, _b), - VIN_DATA_PIN_GROUP(vin1_data, 10, _b), - VIN_DATA_PIN_GROUP(vin1_data, 8, _b), + BUS_DATA_PIN_GROUP(vin1_data, 16, _b), + BUS_DATA_PIN_GROUP(vin1_data, 12, _b), + BUS_DATA_PIN_GROUP(vin1_data, 10, _b), + BUS_DATA_PIN_GROUP(vin1_data, 8, _b), SH_PFC_PIN_GROUP(vin1_sync_b), SH_PFC_PIN_GROUP(vin1_field_b), SH_PFC_PIN_GROUP(vin1_clkenb_b), @@ -6033,15 +5963,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E, /* IP6_18_16 [3] */ FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, - FN_INTC_IRQ4_N, 0, 0, 0, + 0, 0, 0, 0, /* IP6_15_14 [2] */ - FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, + FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, 0, /* IP6_13_12 [2] */ - FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0, + FN_IRQ2, FN_SCIFB1_TXD_D, 0, 0, /* IP6_11_10 [2] */ - FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0, + FN_IRQ1, FN_SCIFB1_SCK_C, 0, 0, /* IP6_9_8 [2] */ - FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0, + FN_IRQ0, FN_SCIFB1_RXD_D, 0, 0, /* IP6_7_6 [2] */ FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, /* IP6_5_3 [3] */ @@ -6672,7 +6602,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a7791_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23)) return -EINVAL; @@ -6994,7 +6924,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a7791_pfc_ops = { .pin_to_pocctrl = r8a7791_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -7003,7 +6933,7 @@ static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = { #ifdef CONFIG_PINCTRL_PFC_R8A7743 const struct sh_pfc_soc_info r8a7743_pinmux_info = { .name = "r8a77430_pfc", - .ops = &r8a7791_pinmux_ops, + .ops = &r8a7791_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -7026,7 +6956,7 @@ const struct sh_pfc_soc_info r8a7743_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A7744 const struct sh_pfc_soc_info r8a7744_pinmux_info = { .name = "r8a77440_pfc", - .ops = &r8a7791_pinmux_ops, + .ops = &r8a7791_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -7049,7 +6979,7 @@ const struct sh_pfc_soc_info r8a7744_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A7791 const struct sh_pfc_soc_info r8a7791_pinmux_info = { .name = "r8a77910_pfc", - .ops = &r8a7791_pinmux_ops, + .ops = &r8a7791_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -7074,7 +7004,7 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A7793 const struct sh_pfc_soc_info r8a7793_pinmux_info = { .name = "r8a77930_pfc", - .ops = &r8a7791_pinmux_ops, + .ops = &r8a7791_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c index 3ab56dc768de..3e101f630148 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7792.c +++ b/drivers/pinctrl/renesas/pfc-r8a7792.c @@ -1116,19 +1116,12 @@ static const unsigned int qspi_ctrl_pins[] = { static const unsigned int qspi_ctrl_mux[] = { SPCLK_MARK, SSL_MARK, }; -static const unsigned int qspi_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), -}; -static const unsigned int qspi_data2_mux[] = { - MOSI_IO0_MARK, MISO_IO1_MARK, -}; -static const unsigned int qspi_data4_pins[] = { +static const unsigned int qspi_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), }; -static const unsigned int qspi_data4_mux[] = { +static const unsigned int qspi_data_mux[] = { MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, }; /* - SCIF0 ------------------------------------------------------------------ */ @@ -1206,19 +1199,12 @@ static const unsigned int scif3_clk_mux[] = { SCK3_MARK, }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* DAT0 */ - RCAR_GP_PIN(11, 7), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* DAT[0-3] */ RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8), RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -1243,43 +1229,39 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data vin0_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), - RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), - RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), - RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), - /* G */ - RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13), - RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), - RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2), - RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4), - /* R */ - RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6), - RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8), - RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10), - RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12), - }, +static const unsigned int vin0_data_pins[] = { + /* B */ + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), + RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), + RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), + /* G */ + RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13), + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), + RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2), + RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4), + /* R */ + RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6), + RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8), + RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10), + RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12), }; -static const union vin_data vin0_data_mux = { - .data24 = { - /* B */ - VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, - VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK, - VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK, - VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, - /* G */ - VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK, - VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK, - VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK, - VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK, - /* R */ - VI0_D16_R0_MARK, VI0_D17_R1_MARK, - VI0_D18_R2_MARK, VI0_D19_R3_MARK, - VI0_D20_R4_MARK, VI0_D21_R5_MARK, - VI0_D22_R6_MARK, VI0_D23_R7_MARK, - }, +static const unsigned int vin0_data_mux[] = { + /* B */ + VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, + VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK, + VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK, + VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, + /* G */ + VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK, + VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK, + VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK, + VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK, + /* R */ + VI0_D16_R0_MARK, VI0_D17_R1_MARK, + VI0_D18_R2_MARK, VI0_D19_R3_MARK, + VI0_D20_R4_MARK, VI0_D21_R5_MARK, + VI0_D22_R6_MARK, VI0_D23_R7_MARK, }; static const unsigned int vin0_data18_pins[] = { /* B */ @@ -1335,43 +1317,39 @@ static const unsigned int vin0_clk_mux[] = { VI0_CLK_MARK, }; /* - VIN1 ------------------------------------------------------------------- */ -static const union vin_data vin1_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), - RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), - RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), - RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), - /* G */ - RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), - RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), - RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6), - RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8), - /* R */ - RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6), - RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8), - RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10), - RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12), - }, +static const unsigned int vin1_data_pins[] = { + /* B */ + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), + RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), + /* G */ + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), + RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6), + RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8), + /* R */ + RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6), + RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8), + RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10), + RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12), }; -static const union vin_data vin1_data_mux = { - .data24 = { - /* B */ - VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, - VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK, - VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK, - VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, - /* G */ - VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK, - VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK, - VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK, - VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK, - /* R */ - VI1_D16_R0_MARK, VI1_D17_R1_MARK, - VI1_D18_R2_MARK, VI1_D19_R3_MARK, - VI1_D20_R4_MARK, VI1_D21_R5_MARK, - VI1_D22_R6_MARK, VI1_D23_R7_MARK, - }, +static const unsigned int vin1_data_mux[] = { + /* B */ + VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, + VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK, + VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK, + VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, + /* G */ + VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK, + VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK, + VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK, + VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK, + /* R */ + VI1_D16_R0_MARK, VI1_D17_R1_MARK, + VI1_D18_R2_MARK, VI1_D19_R3_MARK, + VI1_D20_R4_MARK, VI1_D21_R5_MARK, + VI1_D22_R6_MARK, VI1_D23_R7_MARK, }; static const unsigned int vin1_data18_pins[] = { /* B */ @@ -1401,43 +1379,39 @@ static const unsigned int vin1_data18_mux[] = { VI1_D20_R4_MARK, VI1_D21_R5_MARK, VI1_D22_R6_MARK, VI1_D23_R7_MARK, }; -static const union vin_data vin1_data_b_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), - RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), - RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), - RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), - /* G */ - RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), - RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), - RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2), - RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4), - /* R */ - RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6), - RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8), - RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10), - RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12), - }, +static const unsigned int vin1_data_b_pins[] = { + /* B */ + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), + RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), + /* G */ + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), + RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2), + RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4), + /* R */ + RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6), + RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8), + RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10), + RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12), }; -static const union vin_data vin1_data_b_mux = { - .data24 = { - /* B */ - VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, - VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK, - VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK, - VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, - /* G */ - VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK, - VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK, - VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK, - VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK, - /* R */ - VI1_D16_R0_MARK, VI1_D17_R1_MARK, - VI1_D18_R2_MARK, VI1_D19_R3_MARK, - VI1_D20_R4_MARK, VI1_D21_R5_MARK, - VI1_D22_R6_MARK, VI1_D23_R7_MARK, - }, +static const unsigned int vin1_data_b_mux[] = { + /* B */ + VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, + VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK, + VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK, + VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, + /* G */ + VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK, + VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK, + VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK, + VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK, + /* R */ + VI1_D16_R0_MARK, VI1_D17_R1_MARK, + VI1_D18_R2_MARK, VI1_D19_R3_MARK, + VI1_D20_R4_MARK, VI1_D21_R5_MARK, + VI1_D22_R6_MARK, VI1_D23_R7_MARK, }; static const unsigned int vin1_data18_b_pins[] = { /* B */ @@ -1493,29 +1467,25 @@ static const unsigned int vin1_clk_mux[] = { VI1_CLK_MARK, }; /* - VIN2 ------------------------------------------------------------------- */ -static const union vin_data16 vin2_data_pins = { - .data16 = { - RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), - RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), - RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), - RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), - RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), - RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), - RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10), - RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12), - }, +static const unsigned int vin2_data_pins[] = { + RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), + RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), + RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), + RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), + RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), + RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10), + RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12), }; -static const union vin_data16 vin2_data_mux = { - .data16 = { - VI2_D0_C0_MARK, VI2_D1_C1_MARK, - VI2_D2_C2_MARK, VI2_D3_C3_MARK, - VI2_D4_C4_MARK, VI2_D5_C5_MARK, - VI2_D6_C6_MARK, VI2_D7_C7_MARK, - VI2_D8_Y0_MARK, VI2_D9_Y1_MARK, - VI2_D10_Y2_MARK, VI2_D11_Y3_MARK, - VI2_D12_Y4_MARK, VI2_D13_Y5_MARK, - VI2_D14_Y6_MARK, VI2_D15_Y7_MARK, - }, +static const unsigned int vin2_data_mux[] = { + VI2_D0_C0_MARK, VI2_D1_C1_MARK, + VI2_D2_C2_MARK, VI2_D3_C3_MARK, + VI2_D4_C4_MARK, VI2_D5_C5_MARK, + VI2_D6_C6_MARK, VI2_D7_C7_MARK, + VI2_D8_Y0_MARK, VI2_D9_Y1_MARK, + VI2_D10_Y2_MARK, VI2_D11_Y3_MARK, + VI2_D12_Y4_MARK, VI2_D13_Y5_MARK, + VI2_D14_Y6_MARK, VI2_D15_Y7_MARK, }; static const unsigned int vin2_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -1543,29 +1513,25 @@ static const unsigned int vin2_clk_mux[] = { VI2_CLK_MARK, }; /* - VIN3 ------------------------------------------------------------------- */ -static const union vin_data16 vin3_data_pins = { - .data16 = { - RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5), - RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7), - RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), - RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11), - RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13), - RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), - RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14), - RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16), - }, -}; -static const union vin_data16 vin3_data_mux = { - .data16 = { - VI3_D0_C0_MARK, VI3_D1_C1_MARK, - VI3_D2_C2_MARK, VI3_D3_C3_MARK, - VI3_D4_C4_MARK, VI3_D5_C5_MARK, - VI3_D6_C6_MARK, VI3_D7_C7_MARK, - VI3_D8_Y0_MARK, VI3_D9_Y1_MARK, - VI3_D10_Y2_MARK, VI3_D11_Y3_MARK, - VI3_D12_Y4_MARK, VI3_D13_Y5_MARK, - VI3_D14_Y6_MARK, VI3_D15_Y7_MARK, - }, +static const unsigned int vin3_data_pins[] = { + RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5), + RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7), + RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), + RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11), + RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13), + RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), + RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14), + RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16), +}; +static const unsigned int vin3_data_mux[] = { + VI3_D0_C0_MARK, VI3_D1_C1_MARK, + VI3_D2_C2_MARK, VI3_D3_C3_MARK, + VI3_D4_C4_MARK, VI3_D5_C5_MARK, + VI3_D6_C6_MARK, VI3_D7_C7_MARK, + VI3_D8_Y0_MARK, VI3_D9_Y1_MARK, + VI3_D10_Y2_MARK, VI3_D11_Y3_MARK, + VI3_D12_Y4_MARK, VI3_D13_Y5_MARK, + VI3_D14_Y6_MARK, VI3_D15_Y7_MARK, }; static const unsigned int vin3_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -1593,25 +1559,21 @@ static const unsigned int vin3_clk_mux[] = { VI3_CLK_MARK, }; /* - VIN4 ------------------------------------------------------------------- */ -static const union vin_data12 vin4_data_pins = { - .data12 = { - RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5), - RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7), - RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9), - RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11), - RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13), - RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15), - }, -}; -static const union vin_data12 vin4_data_mux = { - .data12 = { - VI4_D0_C0_MARK, VI4_D1_C1_MARK, - VI4_D2_C2_MARK, VI4_D3_C3_MARK, - VI4_D4_C4_MARK, VI4_D5_C5_MARK, - VI4_D6_C6_MARK, VI4_D7_C7_MARK, - VI4_D8_Y0_MARK, VI4_D9_Y1_MARK, - VI4_D10_Y2_MARK, VI4_D11_Y3_MARK, - }, +static const unsigned int vin4_data_pins[] = { + RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5), + RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7), + RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9), + RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11), + RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13), + RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15), +}; +static const unsigned int vin4_data_mux[] = { + VI4_D0_C0_MARK, VI4_D1_C1_MARK, + VI4_D2_C2_MARK, VI4_D3_C3_MARK, + VI4_D4_C4_MARK, VI4_D5_C5_MARK, + VI4_D6_C6_MARK, VI4_D7_C7_MARK, + VI4_D8_Y0_MARK, VI4_D9_Y1_MARK, + VI4_D10_Y2_MARK, VI4_D11_Y3_MARK, }; static const unsigned int vin4_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -1639,25 +1601,21 @@ static const unsigned int vin4_clk_mux[] = { VI4_CLK_MARK, }; /* - VIN5 ------------------------------------------------------------------- */ -static const union vin_data12 vin5_data_pins = { - .data12 = { - RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5), - RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7), - RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9), - RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11), - RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13), - RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15), - }, -}; -static const union vin_data12 vin5_data_mux = { - .data12 = { - VI5_D0_C0_MARK, VI5_D1_C1_MARK, - VI5_D2_C2_MARK, VI5_D3_C3_MARK, - VI5_D4_C4_MARK, VI5_D5_C5_MARK, - VI5_D6_C6_MARK, VI5_D7_C7_MARK, - VI5_D8_Y0_MARK, VI5_D9_Y1_MARK, - VI5_D10_Y2_MARK, VI5_D11_Y3_MARK, - }, +static const unsigned int vin5_data_pins[] = { + RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5), + RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7), + RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9), + RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11), + RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13), + RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15), +}; +static const unsigned int vin5_data_mux[] = { + VI5_D0_C0_MARK, VI5_D1_C1_MARK, + VI5_D2_C2_MARK, VI5_D3_C3_MARK, + VI5_D4_C4_MARK, VI5_D5_C5_MARK, + VI5_D6_C6_MARK, VI5_D7_C7_MARK, + VI5_D8_Y0_MARK, VI5_D9_Y1_MARK, + VI5_D10_Y2_MARK, VI5_D11_Y3_MARK, }; static const unsigned int vin5_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -1728,8 +1686,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof1_rx), SH_PFC_PIN_GROUP(msiof1_tx), SH_PFC_PIN_GROUP(qspi_ctrl), - SH_PFC_PIN_GROUP(qspi_data2), - SH_PFC_PIN_GROUP(qspi_data4), + BUS_DATA_PIN_GROUP(qspi_data, 2), + BUS_DATA_PIN_GROUP(qspi_data, 4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -1740,63 +1698,63 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif2_clk), SH_PFC_PIN_GROUP(scif3_data), SH_PFC_PIN_GROUP(scif3_clk), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), + BUS_DATA_PIN_GROUP(vin0_data, 24), + BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 16), + BUS_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 8), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 24), - VIN_DATA_PIN_GROUP(vin1_data, 20), + BUS_DATA_PIN_GROUP(vin1_data, 24), + BUS_DATA_PIN_GROUP(vin1_data, 20), SH_PFC_PIN_GROUP(vin1_data18), - VIN_DATA_PIN_GROUP(vin1_data, 16), - VIN_DATA_PIN_GROUP(vin1_data, 12), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 8), - VIN_DATA_PIN_GROUP(vin1_data, 24, _b), - VIN_DATA_PIN_GROUP(vin1_data, 20, _b), + BUS_DATA_PIN_GROUP(vin1_data, 16), + BUS_DATA_PIN_GROUP(vin1_data, 12), + BUS_DATA_PIN_GROUP(vin1_data, 10), + BUS_DATA_PIN_GROUP(vin1_data, 8), + BUS_DATA_PIN_GROUP(vin1_data, 24, _b), + BUS_DATA_PIN_GROUP(vin1_data, 20, _b), SH_PFC_PIN_GROUP(vin1_data18_b), - VIN_DATA_PIN_GROUP(vin1_data, 16, _b), + BUS_DATA_PIN_GROUP(vin1_data, 16, _b), SH_PFC_PIN_GROUP(vin1_sync), SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), SH_PFC_PIN_GROUP(vin1_clk), - VIN_DATA_PIN_GROUP(vin2_data, 16), - VIN_DATA_PIN_GROUP(vin2_data, 12), - VIN_DATA_PIN_GROUP(vin2_data, 10), - VIN_DATA_PIN_GROUP(vin2_data, 8), + BUS_DATA_PIN_GROUP(vin2_data, 16), + BUS_DATA_PIN_GROUP(vin2_data, 12), + BUS_DATA_PIN_GROUP(vin2_data, 10), + BUS_DATA_PIN_GROUP(vin2_data, 8), SH_PFC_PIN_GROUP(vin2_sync), SH_PFC_PIN_GROUP(vin2_field), SH_PFC_PIN_GROUP(vin2_clkenb), SH_PFC_PIN_GROUP(vin2_clk), - VIN_DATA_PIN_GROUP(vin3_data, 16), - VIN_DATA_PIN_GROUP(vin3_data, 12), - VIN_DATA_PIN_GROUP(vin3_data, 10), - VIN_DATA_PIN_GROUP(vin3_data, 8), + BUS_DATA_PIN_GROUP(vin3_data, 16), + BUS_DATA_PIN_GROUP(vin3_data, 12), + BUS_DATA_PIN_GROUP(vin3_data, 10), + BUS_DATA_PIN_GROUP(vin3_data, 8), SH_PFC_PIN_GROUP(vin3_sync), SH_PFC_PIN_GROUP(vin3_field), SH_PFC_PIN_GROUP(vin3_clkenb), SH_PFC_PIN_GROUP(vin3_clk), - VIN_DATA_PIN_GROUP(vin4_data, 12), - VIN_DATA_PIN_GROUP(vin4_data, 10), - VIN_DATA_PIN_GROUP(vin4_data, 8), + BUS_DATA_PIN_GROUP(vin4_data, 12), + BUS_DATA_PIN_GROUP(vin4_data, 10), + BUS_DATA_PIN_GROUP(vin4_data, 8), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(vin4_clk), - VIN_DATA_PIN_GROUP(vin5_data, 12), - VIN_DATA_PIN_GROUP(vin5_data, 10), - VIN_DATA_PIN_GROUP(vin5_data, 8), + BUS_DATA_PIN_GROUP(vin5_data, 12), + BUS_DATA_PIN_GROUP(vin5_data, 10), + BUS_DATA_PIN_GROUP(vin5_data, 8), SH_PFC_PIN_GROUP(vin5_sync), SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), @@ -3281,14 +3239,14 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ } }; -static const struct sh_pfc_soc_operations r8a7792_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a7792_pfc_ops = { .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a7792_pinmux_info = { .name = "r8a77920_pfc", - .ops = &r8a7792_pinmux_ops, + .ops = &r8a7792_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c index fbb5b3b68f34..d1b0e6517382 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7794.c +++ b/drivers/pinctrl/renesas/pfc-r8a7794.c @@ -2388,29 +2388,14 @@ static const unsigned int intc_irq9_mux[] = { IRQ9_MARK, }; /* - MMCIF ------------------------------------------------------------------ */ -static const unsigned int mmc_data1_pins[] = { - /* D[0] */ - RCAR_GP_PIN(6, 18), -}; -static const unsigned int mmc_data1_mux[] = { - MMC_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), - RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), -}; -static const unsigned int mmc_data4_mux[] = { - MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, -}; -static const unsigned int mmc_data8_pins[] = { +static const unsigned int mmc_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, }; @@ -2745,19 +2730,12 @@ static const unsigned int qspi_ctrl_pins[] = { static const unsigned int qspi_ctrl_mux[] = { SPCLK_MARK, SSL_MARK, }; -static const unsigned int qspi_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), -}; -static const unsigned int qspi_data2_mux[] = { - MOSI_IO0_MARK, MISO_IO1_MARK, -}; -static const unsigned int qspi_data4_pins[] = { +static const unsigned int qspi_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), }; -static const unsigned int qspi_data4_mux[] = { +static const unsigned int qspi_data_mux[] = { MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, }; /* - SCIF0 ------------------------------------------------------------------ */ @@ -3232,19 +3210,12 @@ static const unsigned int scif_clk_b_mux[] = { SCIF_CLK_B_MARK, }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 2), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DATA0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -3269,19 +3240,12 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 10), -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DATA0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK, }; static const unsigned int sdhi1_ctrl_pins[] = { @@ -3306,19 +3270,12 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 18), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DATA0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), }; -static const unsigned int sdhi2_data4_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { @@ -3673,43 +3630,39 @@ static const unsigned int usb1_mux[] = { USB1_OVC_MARK, }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data vin0_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), - RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), - RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), - RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), - /* G */ - RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), - RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), - RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), - RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), - /* R */ - RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), - RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), - RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), - RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), - }, +static const unsigned int vin0_data_pins[] = { + /* B */ + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), + RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), + /* G */ + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), + RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), + RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), + /* R */ + RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), + RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), + RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), }; -static const union vin_data vin0_data_mux = { - .data24 = { - /* B */ - VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, - VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, - VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, - VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, - /* G */ - VI0_G0_MARK, VI0_G1_MARK, - VI0_G2_MARK, VI0_G3_MARK, - VI0_G4_MARK, VI0_G5_MARK, - VI0_G6_MARK, VI0_G7_MARK, - /* R */ - VI0_R0_MARK, VI0_R1_MARK, - VI0_R2_MARK, VI0_R3_MARK, - VI0_R4_MARK, VI0_R5_MARK, - VI0_R6_MARK, VI0_R7_MARK, - }, +static const unsigned int vin0_data_mux[] = { + /* B */ + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G0_MARK, VI0_G1_MARK, + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R0_MARK, VI0_R1_MARK, + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, }; static const unsigned int vin0_data18_pins[] = { /* B */ @@ -3766,25 +3719,21 @@ static const unsigned int vin0_clk_mux[] = { VI0_CLK_MARK, }; /* - VIN1 ------------------------------------------------------------------- */ -static const union vin_data12 vin1_data_pins = { - .data12 = { - RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), - RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), - RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), - RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), - RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), - }, +static const unsigned int vin1_data_pins[] = { + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), + RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), + RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), }; -static const union vin_data12 vin1_data_mux = { - .data12 = { - VI1_DATA0_MARK, VI1_DATA1_MARK, - VI1_DATA2_MARK, VI1_DATA3_MARK, - VI1_DATA4_MARK, VI1_DATA5_MARK, - VI1_DATA6_MARK, VI1_DATA7_MARK, - VI1_DATA8_MARK, VI1_DATA9_MARK, - VI1_DATA10_MARK, VI1_DATA11_MARK, - }, +static const unsigned int vin1_data_mux[] = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, + VI1_DATA8_MARK, VI1_DATA9_MARK, + VI1_DATA10_MARK, VI1_DATA11_MARK, }; static const unsigned int vin1_sync_pins[] = { RCAR_GP_PIN(5, 22), /* HSYNC */ @@ -3923,9 +3872,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_irq7), SH_PFC_PIN_GROUP(intc_irq8), SH_PFC_PIN_GROUP(intc_irq9), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), @@ -3975,8 +3924,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm6), SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(qspi_ctrl), - SH_PFC_PIN_GROUP(qspi_data2), - SH_PFC_PIN_GROUP(qspi_data4), + BUS_DATA_PIN_GROUP(qspi_data, 2), + BUS_DATA_PIN_GROUP(qspi_data, 4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_data_b), SH_PFC_PIN_GROUP(scif0_data_c), @@ -4042,18 +3991,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scifb2_ctrl), SH_PFC_PIN_GROUP(scif_clk), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), @@ -4105,20 +4054,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tpu_to3_c), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), + BUS_DATA_PIN_GROUP(vin0_data, 24), + BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 16), + BUS_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 8), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 12), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 8), + BUS_DATA_PIN_GROUP(vin1_data, 12), + BUS_DATA_PIN_GROUP(vin1_data, 10), + BUS_DATA_PIN_GROUP(vin1_data, 8), SH_PFC_PIN_GROUP(vin1_sync), SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), @@ -5621,8 +5570,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a7794_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { + if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23)) + return -EINVAL; + *pocctrl = 0xe606006c; switch (pin & 0x1f) { @@ -5932,7 +5884,7 @@ static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc) return 0; } -static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a7794_pfc_ops = { .init = r8a7794_pinmux_soc_init, .pin_to_pocctrl = r8a7794_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, @@ -5942,7 +5894,7 @@ static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = { #ifdef CONFIG_PINCTRL_PFC_R8A7745 const struct sh_pfc_soc_info r8a7745_pinmux_info = { .name = "r8a77450_pfc", - .ops = &r8a7794_pinmux_ops, + .ops = &r8a7794_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -5965,7 +5917,7 @@ const struct sh_pfc_soc_info r8a7745_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A7794 const struct sh_pfc_soc_info r8a7794_pinmux_info = { .name = "r8a77940_pfc", - .ops = &r8a7794_pinmux_ops, + .ops = &r8a7794_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a77950.c b/drivers/pinctrl/renesas/pfc-r8a77950.c index c86064900c6e..63c9f6d6468b 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77950.c +++ b/drivers/pinctrl/renesas/pfc-r8a77950.c @@ -3140,18 +3140,11 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ - PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { +static const unsigned int qspi0_data_pins[] = { /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, PIN_QSPI0_IO2, PIN_QSPI0_IO3, }; -static const unsigned int qspi0_data4_mux[] = { +static const unsigned int qspi0_data_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK, }; @@ -3163,18 +3156,11 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ - PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { +static const unsigned int qspi1_data_pins[] = { /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, PIN_QSPI1_IO2, PIN_QSPI1_IO3, }; -static const unsigned int qspi1_data4_mux[] = { +static const unsigned int qspi1_data_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK, }; @@ -3395,19 +3381,12 @@ static const unsigned int scif_clk_b_mux[] = { }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; @@ -3433,19 +3412,12 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 8), -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; @@ -3471,30 +3443,14 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 2), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DAT0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), -}; -static const unsigned int sdhi2_data4_mux[] = { - SD2_DAT0_MARK, SD2_DAT1_MARK, - SD2_DAT2_MARK, SD2_DAT3_MARK, -}; -static const unsigned int sdhi2_data8_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi2_data8_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, SD2_DAT4_MARK, SD2_DAT5_MARK, @@ -3543,30 +3499,14 @@ static const unsigned int sdhi2_ds_mux[] = { SD2_DS_MARK, }; /* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 9), -}; -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; -static const unsigned int sdhi3_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), - RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), -}; -static const unsigned int sdhi3_data4_mux[] = { - SD3_DAT0_MARK, SD3_DAT1_MARK, - SD3_DAT2_MARK, SD3_DAT3_MARK, -}; -static const unsigned int sdhi3_data8_pins[] = { +static const unsigned int sdhi3_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), }; -static const unsigned int sdhi3_data8_mux[] = { +static const unsigned int sdhi3_data_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, SD3_DAT4_MARK, SD3_DAT5_MARK, @@ -4103,11 +4043,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), SH_PFC_PIN_GROUP(sata0_devslp_a), SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif0_data), @@ -4137,28 +4077,28 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_clk), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_data8), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), + BUS_DATA_PIN_GROUP(sdhi2_data, 8), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd_a), SH_PFC_PIN_GROUP(sdhi2_wp_a), SH_PFC_PIN_GROUP(sdhi2_cd_b), SH_PFC_PIN_GROUP(sdhi2_wp_b), SH_PFC_PIN_GROUP(sdhi2_ds), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_data8), + BUS_DATA_PIN_GROUP(sdhi3_data, 1), + BUS_DATA_PIN_GROUP(sdhi3_data, 4), + BUS_DATA_PIN_GROUP(sdhi3_data, 8), SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), @@ -5574,8 +5514,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a77950_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, - u32 *pocctrl) +static int r8a77950_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -5832,7 +5771,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a77950_pfc_ops = { .pin_to_pocctrl = r8a77950_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -5840,7 +5779,7 @@ static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = { const struct sh_pfc_soc_info r8a77950_pinmux_info = { .name = "r8a77950_pfc", - .ops = &r8a77950_pinmux_ops, + .ops = &r8a77950_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c index ee9ce5f8eb86..9d6eef4e9d18 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77951.c +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c @@ -3268,20 +3268,13 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ - PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { +static const unsigned int qspi0_data_pins[] = { /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, /* QSPI0_IO2, QSPI0_IO3 */ PIN_QSPI0_IO2, PIN_QSPI0_IO3, }; -static const unsigned int qspi0_data4_mux[] = { +static const unsigned int qspi0_data_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK, }; @@ -3293,20 +3286,13 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ - PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { +static const unsigned int qspi1_data_pins[] = { /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, /* QSPI1_IO2, QSPI1_IO3 */ PIN_QSPI1_IO2, PIN_QSPI1_IO3, }; -static const unsigned int qspi1_data4_mux[] = { +static const unsigned int qspi1_data_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK, }; @@ -3541,19 +3527,12 @@ static const unsigned int scif_clk_b_mux[] = { }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; @@ -3579,19 +3558,12 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 8), -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; @@ -3617,30 +3589,14 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 2), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DAT0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), -}; -static const unsigned int sdhi2_data4_mux[] = { - SD2_DAT0_MARK, SD2_DAT1_MARK, - SD2_DAT2_MARK, SD2_DAT3_MARK, -}; -static const unsigned int sdhi2_data8_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi2_data8_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, SD2_DAT4_MARK, SD2_DAT5_MARK, @@ -3689,30 +3645,14 @@ static const unsigned int sdhi2_ds_mux[] = { SD2_DS_MARK, }; /* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 9), -}; -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; -static const unsigned int sdhi3_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), - RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), -}; -static const unsigned int sdhi3_data4_mux[] = { - SD3_DAT0_MARK, SD3_DAT1_MARK, - SD3_DAT2_MARK, SD3_DAT3_MARK, -}; -static const unsigned int sdhi3_data8_pins[] = { +static const unsigned int sdhi3_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), }; -static const unsigned int sdhi3_data8_mux[] = { +static const unsigned int sdhi3_data_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, SD3_DAT4_MARK, SD3_DAT5_MARK, @@ -4071,81 +4011,61 @@ static const unsigned int vin4_data18_b_mux[] = { VI4_DATA20_MARK, VI4_DATA21_MARK, VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_a_pins = { - .data24 = { - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), - RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - }, -}; -static const union vin_data vin4_data_a_mux = { - .data24 = { - VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, - VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, - VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, - VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, -}; -static const union vin_data vin4_data_b_pins = { - .data24 = { - RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), - RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), - RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - }, +static const unsigned int vin4_data_a_pins[] = { + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), }; -static const union vin_data vin4_data_b_mux = { - .data24 = { - VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, - VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, - VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, - VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, +static const unsigned int vin4_data_a_mux[] = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const unsigned int vin4_g8_pins[] = { - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +static const unsigned int vin4_data_b_pins[] = { + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), }; -static const unsigned int vin4_g8_mux[] = { +static const unsigned int vin4_data_b_mux[] = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, VI4_DATA8_MARK, VI4_DATA9_MARK, VI4_DATA10_MARK, VI4_DATA11_MARK, VI4_DATA12_MARK, VI4_DATA13_MARK, VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const unsigned int vin4_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -4177,37 +4097,21 @@ static const unsigned int vin4_clk_mux[] = { }; /* - VIN5 ------------------------------------------------------------------- */ -static const union vin_data16 vin5_data_pins = { - .data16 = { - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - }, -}; -static const union vin_data16 vin5_data_mux = { - .data16 = { - VI5_DATA0_MARK, VI5_DATA1_MARK, - VI5_DATA2_MARK, VI5_DATA3_MARK, - VI5_DATA4_MARK, VI5_DATA5_MARK, - VI5_DATA6_MARK, VI5_DATA7_MARK, - VI5_DATA8_MARK, VI5_DATA9_MARK, - VI5_DATA10_MARK, VI5_DATA11_MARK, - VI5_DATA12_MARK, VI5_DATA13_MARK, - VI5_DATA14_MARK, VI5_DATA15_MARK, - }, -}; -static const unsigned int vin5_high8_pins[] = { +static const unsigned int vin5_data_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), }; -static const unsigned int vin5_high8_mux[] = { +static const unsigned int vin5_data_mux[] = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, VI5_DATA8_MARK, VI5_DATA9_MARK, VI5_DATA10_MARK, VI5_DATA11_MARK, VI5_DATA12_MARK, VI5_DATA13_MARK, @@ -4449,11 +4353,11 @@ static const struct { SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), SH_PFC_PIN_GROUP(sata0_devslp_a), SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif0_data), @@ -4485,28 +4389,28 @@ static const struct { SH_PFC_PIN_GROUP(scif5_clk_b), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_data8), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), + BUS_DATA_PIN_GROUP(sdhi2_data, 8), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd_a), SH_PFC_PIN_GROUP(sdhi2_wp_a), SH_PFC_PIN_GROUP(sdhi2_cd_b), SH_PFC_PIN_GROUP(sdhi2_wp_b), SH_PFC_PIN_GROUP(sdhi2_ds), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_data8), + BUS_DATA_PIN_GROUP(sdhi3_data, 1), + BUS_DATA_PIN_GROUP(sdhi3_data, 4), + BUS_DATA_PIN_GROUP(sdhi3_data, 8), SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), @@ -4549,30 +4453,30 @@ static const struct { SH_PFC_PIN_GROUP(usb2), SH_PFC_PIN_GROUP(usb2_ch3), SH_PFC_PIN_GROUP(usb30), - VIN_DATA_PIN_GROUP(vin4_data, 8, _a), - VIN_DATA_PIN_GROUP(vin4_data, 10, _a), - VIN_DATA_PIN_GROUP(vin4_data, 12, _a), - VIN_DATA_PIN_GROUP(vin4_data, 16, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _a), + BUS_DATA_PIN_GROUP(vin4_data, 10, _a), + BUS_DATA_PIN_GROUP(vin4_data, 12, _a), + BUS_DATA_PIN_GROUP(vin4_data, 16, _a), SH_PFC_PIN_GROUP(vin4_data18_a), - VIN_DATA_PIN_GROUP(vin4_data, 20, _a), - VIN_DATA_PIN_GROUP(vin4_data, 24, _a), - VIN_DATA_PIN_GROUP(vin4_data, 8, _b), - VIN_DATA_PIN_GROUP(vin4_data, 10, _b), - VIN_DATA_PIN_GROUP(vin4_data, 12, _b), - VIN_DATA_PIN_GROUP(vin4_data, 16, _b), + BUS_DATA_PIN_GROUP(vin4_data, 20, _a), + BUS_DATA_PIN_GROUP(vin4_data, 24, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _b), + BUS_DATA_PIN_GROUP(vin4_data, 10, _b), + BUS_DATA_PIN_GROUP(vin4_data, 12, _b), + BUS_DATA_PIN_GROUP(vin4_data, 16, _b), SH_PFC_PIN_GROUP(vin4_data18_b), - VIN_DATA_PIN_GROUP(vin4_data, 20, _b), - VIN_DATA_PIN_GROUP(vin4_data, 24, _b), - SH_PFC_PIN_GROUP(vin4_g8), + BUS_DATA_PIN_GROUP(vin4_data, 20, _b), + BUS_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(vin4_clk), - VIN_DATA_PIN_GROUP(vin5_data, 8), - VIN_DATA_PIN_GROUP(vin5_data, 10), - VIN_DATA_PIN_GROUP(vin5_data, 12), - VIN_DATA_PIN_GROUP(vin5_data, 16), - SH_PFC_PIN_GROUP(vin5_high8), + BUS_DATA_PIN_GROUP(vin5_data, 8), + BUS_DATA_PIN_GROUP(vin5_data, 10), + BUS_DATA_PIN_GROUP(vin5_data, 12), + BUS_DATA_PIN_GROUP(vin5_data, 16), + SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8), SH_PFC_PIN_GROUP(vin5_sync), SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), @@ -6058,8 +5962,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc, - unsigned int pin, u32 *pocctrl) +static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -6316,7 +6219,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a77951_pfc_ops = { .pin_to_pocctrl = r8a77951_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -6325,7 +6228,7 @@ static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = { #ifdef CONFIG_PINCTRL_PFC_R8A774E1 const struct sh_pfc_soc_info r8a774e1_pinmux_info = { .name = "r8a774e1_pfc", - .ops = &r8a77951_pinmux_ops, + .ops = &r8a77951_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -6350,7 +6253,7 @@ const struct sh_pfc_soc_info r8a774e1_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A77951 const struct sh_pfc_soc_info r8a77951_pinmux_info = { .name = "r8a77951_pfc", - .ops = &r8a77951_pinmux_ops, + .ops = &r8a77951_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index de3df502f971..75ea36829a70 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -3274,20 +3274,13 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ - PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { +static const unsigned int qspi0_data_pins[] = { /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, /* QSPI0_IO2, QSPI0_IO3 */ PIN_QSPI0_IO2, PIN_QSPI0_IO3, }; -static const unsigned int qspi0_data4_mux[] = { +static const unsigned int qspi0_data_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK, }; @@ -3299,20 +3292,13 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ - PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { +static const unsigned int qspi1_data_pins[] = { /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, /* QSPI1_IO2, QSPI1_IO3 */ PIN_QSPI1_IO2, PIN_QSPI1_IO3, }; -static const unsigned int qspi1_data4_mux[] = { +static const unsigned int qspi1_data_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK, }; @@ -3532,19 +3518,12 @@ static const unsigned int scif_clk_b_mux[] = { }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; @@ -3570,19 +3549,12 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 8), -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; @@ -3608,30 +3580,14 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 2), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DAT0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), -}; -static const unsigned int sdhi2_data4_mux[] = { - SD2_DAT0_MARK, SD2_DAT1_MARK, - SD2_DAT2_MARK, SD2_DAT3_MARK, -}; -static const unsigned int sdhi2_data8_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi2_data8_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, SD2_DAT4_MARK, SD2_DAT5_MARK, @@ -3680,30 +3636,14 @@ static const unsigned int sdhi2_ds_mux[] = { SD2_DS_MARK, }; /* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 9), -}; -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; -static const unsigned int sdhi3_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), - RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), -}; -static const unsigned int sdhi3_data4_mux[] = { - SD3_DAT0_MARK, SD3_DAT1_MARK, - SD3_DAT2_MARK, SD3_DAT3_MARK, -}; -static const unsigned int sdhi3_data8_pins[] = { +static const unsigned int sdhi3_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), }; -static const unsigned int sdhi3_data8_mux[] = { +static const unsigned int sdhi3_data_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, SD3_DAT4_MARK, SD3_DAT5_MARK, @@ -4046,81 +3986,61 @@ static const unsigned int vin4_data18_b_mux[] = { VI4_DATA20_MARK, VI4_DATA21_MARK, VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_a_pins = { - .data24 = { - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), - RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - }, -}; -static const union vin_data vin4_data_a_mux = { - .data24 = { - VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, - VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, - VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, - VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, -}; -static const union vin_data vin4_data_b_pins = { - .data24 = { - RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), - RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), - RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - }, +static const unsigned int vin4_data_a_pins[] = { + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), }; -static const union vin_data vin4_data_b_mux = { - .data24 = { - VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, - VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, - VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, - VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, +static const unsigned int vin4_data_a_mux[] = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const unsigned int vin4_g8_pins[] = { - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +static const unsigned int vin4_data_b_pins[] = { + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), }; -static const unsigned int vin4_g8_mux[] = { +static const unsigned int vin4_data_b_mux[] = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, VI4_DATA8_MARK, VI4_DATA9_MARK, VI4_DATA10_MARK, VI4_DATA11_MARK, VI4_DATA12_MARK, VI4_DATA13_MARK, VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const unsigned int vin4_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -4152,37 +4072,21 @@ static const unsigned int vin4_clk_mux[] = { }; /* - VIN5 ------------------------------------------------------------------- */ -static const union vin_data16 vin5_data_pins = { - .data16 = { - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - }, -}; -static const union vin_data16 vin5_data_mux = { - .data16 = { - VI5_DATA0_MARK, VI5_DATA1_MARK, - VI5_DATA2_MARK, VI5_DATA3_MARK, - VI5_DATA4_MARK, VI5_DATA5_MARK, - VI5_DATA6_MARK, VI5_DATA7_MARK, - VI5_DATA8_MARK, VI5_DATA9_MARK, - VI5_DATA10_MARK, VI5_DATA11_MARK, - VI5_DATA12_MARK, VI5_DATA13_MARK, - VI5_DATA14_MARK, VI5_DATA15_MARK, - }, -}; -static const unsigned int vin5_high8_pins[] = { +static const unsigned int vin5_data_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), }; -static const unsigned int vin5_high8_mux[] = { +static const unsigned int vin5_data_mux[] = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, VI5_DATA8_MARK, VI5_DATA9_MARK, VI5_DATA10_MARK, VI5_DATA11_MARK, VI5_DATA12_MARK, VI5_DATA13_MARK, @@ -4424,11 +4328,11 @@ static const struct { SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -4458,28 +4362,28 @@ static const struct { SH_PFC_PIN_GROUP(scif5_clk_b), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_data8), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), + BUS_DATA_PIN_GROUP(sdhi2_data, 8), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd_a), SH_PFC_PIN_GROUP(sdhi2_wp_a), SH_PFC_PIN_GROUP(sdhi2_cd_b), SH_PFC_PIN_GROUP(sdhi2_wp_b), SH_PFC_PIN_GROUP(sdhi2_ds), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_data8), + BUS_DATA_PIN_GROUP(sdhi3_data, 1), + BUS_DATA_PIN_GROUP(sdhi3_data, 4), + BUS_DATA_PIN_GROUP(sdhi3_data, 8), SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), @@ -4520,30 +4424,30 @@ static const struct { SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb30), - VIN_DATA_PIN_GROUP(vin4_data, 8, _a), - VIN_DATA_PIN_GROUP(vin4_data, 10, _a), - VIN_DATA_PIN_GROUP(vin4_data, 12, _a), - VIN_DATA_PIN_GROUP(vin4_data, 16, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _a), + BUS_DATA_PIN_GROUP(vin4_data, 10, _a), + BUS_DATA_PIN_GROUP(vin4_data, 12, _a), + BUS_DATA_PIN_GROUP(vin4_data, 16, _a), SH_PFC_PIN_GROUP(vin4_data18_a), - VIN_DATA_PIN_GROUP(vin4_data, 20, _a), - VIN_DATA_PIN_GROUP(vin4_data, 24, _a), - VIN_DATA_PIN_GROUP(vin4_data, 8, _b), - VIN_DATA_PIN_GROUP(vin4_data, 10, _b), - VIN_DATA_PIN_GROUP(vin4_data, 12, _b), - VIN_DATA_PIN_GROUP(vin4_data, 16, _b), + BUS_DATA_PIN_GROUP(vin4_data, 20, _a), + BUS_DATA_PIN_GROUP(vin4_data, 24, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _b), + BUS_DATA_PIN_GROUP(vin4_data, 10, _b), + BUS_DATA_PIN_GROUP(vin4_data, 12, _b), + BUS_DATA_PIN_GROUP(vin4_data, 16, _b), SH_PFC_PIN_GROUP(vin4_data18_b), - VIN_DATA_PIN_GROUP(vin4_data, 20, _b), - VIN_DATA_PIN_GROUP(vin4_data, 24, _b), - SH_PFC_PIN_GROUP(vin4_g8), + BUS_DATA_PIN_GROUP(vin4_data, 20, _b), + BUS_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(vin4_clk), - VIN_DATA_PIN_GROUP(vin5_data, 8), - VIN_DATA_PIN_GROUP(vin5_data, 10), - VIN_DATA_PIN_GROUP(vin5_data, 12), - VIN_DATA_PIN_GROUP(vin5_data, 16), - SH_PFC_PIN_GROUP(vin5_high8), + BUS_DATA_PIN_GROUP(vin5_data, 8), + BUS_DATA_PIN_GROUP(vin5_data, 10), + BUS_DATA_PIN_GROUP(vin5_data, 12), + BUS_DATA_PIN_GROUP(vin5_data, 16), + SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8), SH_PFC_PIN_GROUP(vin5_sync), SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), @@ -6009,8 +5913,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, - unsigned int pin, u32 *pocctrl) +static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -6267,7 +6170,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a7796_pfc_ops = { .pin_to_pocctrl = r8a7796_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -6276,7 +6179,7 @@ static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { #ifdef CONFIG_PINCTRL_PFC_R8A774A1 const struct sh_pfc_soc_info r8a774a1_pinmux_info = { .name = "r8a774a1_pfc", - .ops = &r8a7796_pinmux_ops, + .ops = &r8a7796_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -6301,7 +6204,7 @@ const struct sh_pfc_soc_info r8a774a1_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A77960 const struct sh_pfc_soc_info r8a77960_pinmux_info = { .name = "r8a77960_pfc", - .ops = &r8a7796_pinmux_ops, + .ops = &r8a7796_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -6328,7 +6231,7 @@ const struct sh_pfc_soc_info r8a77960_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A77961 const struct sh_pfc_soc_info r8a77961_pinmux_info = { .name = "r8a77961_pfc", - .ops = &r8a7796_pinmux_ops, + .ops = &r8a7796_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index 268129f82929..6bb7f7543c37 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -3424,20 +3424,13 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ - PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { +static const unsigned int qspi0_data_pins[] = { /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, /* QSPI0_IO2, QSPI0_IO3 */ PIN_QSPI0_IO2, PIN_QSPI0_IO3, }; -static const unsigned int qspi0_data4_mux[] = { +static const unsigned int qspi0_data_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK, }; @@ -3449,20 +3442,13 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ - PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { +static const unsigned int qspi1_data_pins[] = { /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, /* QSPI1_IO2, QSPI1_IO3 */ PIN_QSPI1_IO2, PIN_QSPI1_IO3, }; -static const unsigned int qspi1_data4_mux[] = { +static const unsigned int qspi1_data_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK, }; @@ -3698,22 +3684,13 @@ static const unsigned int scif_clk_b_mux[] = { }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), -}; - -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; - -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; @@ -3746,22 +3723,13 @@ static const unsigned int sdhi0_wp_mux[] = { }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 8), -}; - -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; - -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; @@ -3794,27 +3762,7 @@ static const unsigned int sdhi1_wp_mux[] = { }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 2), -}; - -static const unsigned int sdhi2_data1_mux[] = { - SD2_DAT0_MARK, -}; - -static const unsigned int sdhi2_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), -}; - -static const unsigned int sdhi2_data4_mux[] = { - SD2_DAT0_MARK, SD2_DAT1_MARK, - SD2_DAT2_MARK, SD2_DAT3_MARK, -}; - -static const unsigned int sdhi2_data8_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), @@ -3822,7 +3770,7 @@ static const unsigned int sdhi2_data8_pins[] = { RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi2_data8_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, SD2_DAT4_MARK, SD2_DAT5_MARK, @@ -3884,27 +3832,7 @@ static const unsigned int sdhi2_ds_mux[] = { }; /* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 9), -}; - -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; - -static const unsigned int sdhi3_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), - RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), -}; - -static const unsigned int sdhi3_data4_mux[] = { - SD3_DAT0_MARK, SD3_DAT1_MARK, - SD3_DAT2_MARK, SD3_DAT3_MARK, -}; - -static const unsigned int sdhi3_data8_pins[] = { +static const unsigned int sdhi3_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), @@ -3912,7 +3840,7 @@ static const unsigned int sdhi3_data8_pins[] = { RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), }; -static const unsigned int sdhi3_data8_mux[] = { +static const unsigned int sdhi3_data_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, SD3_DAT4_MARK, SD3_DAT5_MARK, @@ -4254,38 +4182,34 @@ static const unsigned int vin4_data18_a_mux[] = { VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_a_pins = { - .data24 = { - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), - RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - }, +static const unsigned int vin4_data_a_pins[] = { + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), }; -static const union vin_data vin4_data_a_mux = { - .data24 = { - VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, - VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, - VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, - VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, +static const unsigned int vin4_data_a_mux[] = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const unsigned int vin4_data18_b_pins[] = { @@ -4312,52 +4236,34 @@ static const unsigned int vin4_data18_b_mux[] = { VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_b_pins = { - .data24 = { - RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), - RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), - RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - }, -}; - -static const union vin_data vin4_data_b_mux = { - .data24 = { - VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, - VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, - VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, - VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, -}; - -static const unsigned int vin4_g8_pins[] = { - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +static const unsigned int vin4_data_b_pins[] = { + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), }; -static const unsigned int vin4_g8_mux[] = { - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, +static const unsigned int vin4_data_b_mux[] = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const unsigned int vin4_sync_pins[] = { @@ -4394,40 +4300,22 @@ static const unsigned int vin4_clk_mux[] = { }; /* - VIN5 ------------------------------------------------------------------- */ -static const union vin_data16 vin5_data_pins = { - .data16 = { - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - }, -}; - -static const union vin_data16 vin5_data_mux = { - .data16 = { - VI5_DATA0_MARK, VI5_DATA1_MARK, - VI5_DATA2_MARK, VI5_DATA3_MARK, - VI5_DATA4_MARK, VI5_DATA5_MARK, - VI5_DATA6_MARK, VI5_DATA7_MARK, - VI5_DATA8_MARK, VI5_DATA9_MARK, - VI5_DATA10_MARK, VI5_DATA11_MARK, - VI5_DATA12_MARK, VI5_DATA13_MARK, - VI5_DATA14_MARK, VI5_DATA15_MARK, - }, -}; - -static const unsigned int vin5_high8_pins[] = { +static const unsigned int vin5_data_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), }; -static const unsigned int vin5_high8_mux[] = { +static const unsigned int vin5_data_mux[] = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, VI5_DATA8_MARK, VI5_DATA9_MARK, VI5_DATA10_MARK, VI5_DATA11_MARK, VI5_DATA12_MARK, VI5_DATA13_MARK, @@ -4674,11 +4562,11 @@ static const struct { SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), SH_PFC_PIN_GROUP(sata0_devslp_a), SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif0_data), @@ -4710,28 +4598,28 @@ static const struct { SH_PFC_PIN_GROUP(scif5_clk_b), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_data8), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), + BUS_DATA_PIN_GROUP(sdhi2_data, 8), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd_a), SH_PFC_PIN_GROUP(sdhi2_wp_a), SH_PFC_PIN_GROUP(sdhi2_cd_b), SH_PFC_PIN_GROUP(sdhi2_wp_b), SH_PFC_PIN_GROUP(sdhi2_ds), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_data8), + BUS_DATA_PIN_GROUP(sdhi3_data, 1), + BUS_DATA_PIN_GROUP(sdhi3_data, 4), + BUS_DATA_PIN_GROUP(sdhi3_data, 8), SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), @@ -4772,30 +4660,30 @@ static const struct { SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb30), - VIN_DATA_PIN_GROUP(vin4_data, 8, _a), - VIN_DATA_PIN_GROUP(vin4_data, 10, _a), - VIN_DATA_PIN_GROUP(vin4_data, 12, _a), - VIN_DATA_PIN_GROUP(vin4_data, 16, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _a), + BUS_DATA_PIN_GROUP(vin4_data, 10, _a), + BUS_DATA_PIN_GROUP(vin4_data, 12, _a), + BUS_DATA_PIN_GROUP(vin4_data, 16, _a), SH_PFC_PIN_GROUP(vin4_data18_a), - VIN_DATA_PIN_GROUP(vin4_data, 20, _a), - VIN_DATA_PIN_GROUP(vin4_data, 24, _a), - VIN_DATA_PIN_GROUP(vin4_data, 8, _b), - VIN_DATA_PIN_GROUP(vin4_data, 10, _b), - VIN_DATA_PIN_GROUP(vin4_data, 12, _b), - VIN_DATA_PIN_GROUP(vin4_data, 16, _b), + BUS_DATA_PIN_GROUP(vin4_data, 20, _a), + BUS_DATA_PIN_GROUP(vin4_data, 24, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _b), + BUS_DATA_PIN_GROUP(vin4_data, 10, _b), + BUS_DATA_PIN_GROUP(vin4_data, 12, _b), + BUS_DATA_PIN_GROUP(vin4_data, 16, _b), SH_PFC_PIN_GROUP(vin4_data18_b), - VIN_DATA_PIN_GROUP(vin4_data, 20, _b), - VIN_DATA_PIN_GROUP(vin4_data, 24, _b), - SH_PFC_PIN_GROUP(vin4_g8), + BUS_DATA_PIN_GROUP(vin4_data, 20, _b), + BUS_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(vin4_clk), - VIN_DATA_PIN_GROUP(vin5_data, 8), - VIN_DATA_PIN_GROUP(vin5_data, 10), - VIN_DATA_PIN_GROUP(vin5_data, 12), - VIN_DATA_PIN_GROUP(vin5_data, 16), - SH_PFC_PIN_GROUP(vin5_high8), + BUS_DATA_PIN_GROUP(vin5_data, 8), + BUS_DATA_PIN_GROUP(vin5_data, 10), + BUS_DATA_PIN_GROUP(vin5_data, 12), + BUS_DATA_PIN_GROUP(vin5_data, 16), + SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8), SH_PFC_PIN_GROUP(vin5_sync), SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), @@ -6266,8 +6154,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, - unsigned int pin, u32 *pocctrl) +static int r8a77965_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -6524,7 +6411,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a77965_pfc_ops = { .pin_to_pocctrl = r8a77965_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -6533,7 +6420,7 @@ static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = { #ifdef CONFIG_PINCTRL_PFC_R8A774B1 const struct sh_pfc_soc_info r8a774b1_pinmux_info = { .name = "r8a774b1_pfc", - .ops = &r8a77965_pinmux_ops, + .ops = &r8a77965_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -6558,7 +6445,7 @@ const struct sh_pfc_soc_info r8a774b1_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A77965 const struct sh_pfc_soc_info r8a77965_pinmux_info = { .name = "r8a77965_pfc", - .ops = &r8a77965_pinmux_ops, + .ops = &r8a77965_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c index 45b0b235c5cc..94f90c13989e 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77970.c +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c @@ -1102,30 +1102,14 @@ static const unsigned int intc_ex_irq5_mux[] = { }; /* - MMC -------------------------------------------------------------------- */ -static const unsigned int mmc_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 6), -}; -static const unsigned int mmc_data1_mux[] = { - MMC_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), - RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), -}; -static const unsigned int mmc_data4_mux[] = { - MMC_D0_MARK, MMC_D1_MARK, - MMC_D2_MARK, MMC_D3_MARK, -}; -static const unsigned int mmc_data8_pins[] = { +static const unsigned int mmc_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, @@ -1393,22 +1377,6 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { - /* MOSI_IO0, MISO_IO1, IO2, IO3 */ - RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), - RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), -}; -static const unsigned int qspi0_data4_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, - QSPI0_IO2_MARK, QSPI0_IO3_MARK -}; /* - QSPI1 ------------------------------------------------------------------ */ static const unsigned int qspi1_ctrl_pins[] = { @@ -1418,36 +1386,14 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { - /* MOSI_IO0, MISO_IO1, IO2, IO3 */ - RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), - RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), -}; -static const unsigned int qspi1_data4_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, - QSPI1_IO2_MARK, QSPI1_IO3_MARK -}; /* - RPC -------------------------------------------------------------------- */ -static const unsigned int rpc_clk1_pins[] = { +static const unsigned int rpc_clk_pins[] = { /* Octal-SPI flash: C/SCLK */ - RCAR_GP_PIN(5, 0), -}; -static const unsigned int rpc_clk1_mux[] = { - QSPI0_SPCLK_MARK, -}; -static const unsigned int rpc_clk2_pins[] = { /* HyperFlash: CK, CK# */ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6), }; -static const unsigned int rpc_clk2_mux[] = { +static const unsigned int rpc_clk_mux[] = { QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, }; static const unsigned int rpc_ctrl_pins[] = { @@ -1639,25 +1585,21 @@ static const unsigned int tmu_tclk2_b_mux[] = { }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data12 vin0_data_pins = { - .data12 = { - RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), - RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), - RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), - RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), - }, -}; -static const union vin_data12 vin0_data_mux = { - .data12 = { - VI0_DATA0_MARK, VI0_DATA1_MARK, - VI0_DATA2_MARK, VI0_DATA3_MARK, - VI0_DATA4_MARK, VI0_DATA5_MARK, - VI0_DATA6_MARK, VI0_DATA7_MARK, - VI0_DATA8_MARK, VI0_DATA9_MARK, - VI0_DATA10_MARK, VI0_DATA11_MARK, - }, +static const unsigned int vin0_data_pins[] = { + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), +}; +static const unsigned int vin0_data_mux[] = { + VI0_DATA0_MARK, VI0_DATA1_MARK, + VI0_DATA2_MARK, VI0_DATA3_MARK, + VI0_DATA4_MARK, VI0_DATA5_MARK, + VI0_DATA6_MARK, VI0_DATA7_MARK, + VI0_DATA8_MARK, VI0_DATA9_MARK, + VI0_DATA10_MARK, VI0_DATA11_MARK, }; static const unsigned int vin0_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -1689,25 +1631,21 @@ static const unsigned int vin0_clk_mux[] = { }; /* - VIN1 ------------------------------------------------------------------- */ -static const union vin_data12 vin1_data_pins = { - .data12 = { - RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), - RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), - RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), - RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), - RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), - RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), - }, +static const unsigned int vin1_data_pins[] = { + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), }; -static const union vin_data12 vin1_data_mux = { - .data12 = { - VI1_DATA0_MARK, VI1_DATA1_MARK, - VI1_DATA2_MARK, VI1_DATA3_MARK, - VI1_DATA4_MARK, VI1_DATA5_MARK, - VI1_DATA6_MARK, VI1_DATA7_MARK, - VI1_DATA8_MARK, VI1_DATA9_MARK, - VI1_DATA10_MARK, VI1_DATA11_MARK, - }, +static const unsigned int vin1_data_mux[] = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, + VI1_DATA8_MARK, VI1_DATA9_MARK, + VI1_DATA10_MARK, VI1_DATA11_MARK, }; static const unsigned int vin1_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -1783,9 +1721,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_ex_irq3), SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), @@ -1822,13 +1760,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm4_a), SH_PFC_PIN_GROUP(pwm4_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), - SH_PFC_PIN_GROUP(rpc_clk1), - SH_PFC_PIN_GROUP(rpc_clk2), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4), + BUS_DATA_PIN_GROUP(rpc_clk, 1), + BUS_DATA_PIN_GROUP(rpc_clk, 2), SH_PFC_PIN_GROUP(rpc_ctrl), SH_PFC_PIN_GROUP(rpc_data), SH_PFC_PIN_GROUP(rpc_reset), @@ -1853,16 +1791,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), SH_PFC_PIN_GROUP(tmu_tclk2_b), - VIN_DATA_PIN_GROUP(vin0_data, 8), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 12), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 8), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 12), + BUS_DATA_PIN_GROUP(vin1_data, 8), + BUS_DATA_PIN_GROUP(vin1_data, 10), + BUS_DATA_PIN_GROUP(vin1_data, 12), SH_PFC_PIN_GROUP(vin1_sync), SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), @@ -2496,8 +2434,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, - u32 *pocctrl) +static int r8a77970_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = pin & 0x1f; @@ -2656,7 +2593,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ } }; -static const struct sh_pfc_soc_operations pinmux_ops = { +static const struct sh_pfc_soc_operations r8a77970_pfc_ops = { .pin_to_pocctrl = r8a77970_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -2664,7 +2601,7 @@ static const struct sh_pfc_soc_operations pinmux_ops = { const struct sh_pfc_soc_info r8a77970_pinmux_info = { .name = "r8a77970_pfc", - .ops = &pinmux_ops, + .ops = &r8a77970_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c index c4825b01449e..c229a5d8fa57 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77980.c +++ b/drivers/pinctrl/renesas/pfc-r8a77980.c @@ -1365,30 +1365,14 @@ static const unsigned int intc_ex_irq5_mux[] = { }; /* - MMC -------------------------------------------------------------------- */ -static const unsigned int mmc_data1_pins[] = { - /* MMC_D0 */ - RCAR_GP_PIN(3, 8), -}; -static const unsigned int mmc_data1_mux[] = { - MMC_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* MMC_D[0:3] */ - RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), - RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), -}; -static const unsigned int mmc_data4_mux[] = { - MMC_D0_MARK, MMC_D1_MARK, - MMC_D2_MARK, MMC_D3_MARK, -}; -static const unsigned int mmc_data8_pins[] = { +static const unsigned int mmc_data_pins[] = { /* MMC_D[0:7] */ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, @@ -1687,22 +1671,6 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { - /* MOSI_IO0, MISO_IO1, IO2, IO3 */ - RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), - RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), -}; -static const unsigned int qspi0_data4_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, - QSPI0_IO2_MARK, QSPI0_IO3_MARK -}; /* - QSPI1 ------------------------------------------------------------------ */ static const unsigned int qspi1_ctrl_pins[] = { @@ -1712,36 +1680,14 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { - /* MOSI_IO0, MISO_IO1, IO2, IO3 */ - RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), - RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), -}; -static const unsigned int qspi1_data4_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, - QSPI1_IO2_MARK, QSPI1_IO3_MARK -}; /* - RPC -------------------------------------------------------------------- */ -static const unsigned int rpc_clk1_pins[] = { +static const unsigned int rpc_clk_pins[] = { /* Octal-SPI flash: C/SCLK */ - RCAR_GP_PIN(5, 0), -}; -static const unsigned int rpc_clk1_mux[] = { - QSPI0_SPCLK_MARK, -}; -static const unsigned int rpc_clk2_pins[] = { /* HyperFlash: CK, CK# */ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6), }; -static const unsigned int rpc_clk2_mux[] = { +static const unsigned int rpc_clk_mux[] = { QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, }; static const unsigned int rpc_ctrl_pins[] = { @@ -1963,37 +1909,33 @@ static const unsigned int tpu_to3_mux[] = { }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data vin0_data_pins = { - .data24 = { - RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), - RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), - RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), - RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), - RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), - RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), - RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), - RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), - RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), - RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28), - }, +static const unsigned int vin0_data_pins[] = { + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), + RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), + RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), + RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28), }; -static const union vin_data vin0_data_mux = { - .data24 = { - VI0_DATA0_MARK, VI0_DATA1_MARK, - VI0_DATA2_MARK, VI0_DATA3_MARK, - VI0_DATA4_MARK, VI0_DATA5_MARK, - VI0_DATA6_MARK, VI0_DATA7_MARK, - VI0_DATA8_MARK, VI0_DATA9_MARK, - VI0_DATA10_MARK, VI0_DATA11_MARK, - VI0_DATA12_MARK, VI0_DATA13_MARK, - VI0_DATA14_MARK, VI0_DATA15_MARK, - VI0_DATA16_MARK, VI0_DATA17_MARK, - VI0_DATA18_MARK, VI0_DATA19_MARK, - VI0_DATA20_MARK, VI0_DATA21_MARK, - VI0_DATA22_MARK, VI0_DATA23_MARK, - }, +static const unsigned int vin0_data_mux[] = { + VI0_DATA0_MARK, VI0_DATA1_MARK, + VI0_DATA2_MARK, VI0_DATA3_MARK, + VI0_DATA4_MARK, VI0_DATA5_MARK, + VI0_DATA6_MARK, VI0_DATA7_MARK, + VI0_DATA8_MARK, VI0_DATA9_MARK, + VI0_DATA10_MARK, VI0_DATA11_MARK, + VI0_DATA12_MARK, VI0_DATA13_MARK, + VI0_DATA14_MARK, VI0_DATA15_MARK, + VI0_DATA16_MARK, VI0_DATA17_MARK, + VI0_DATA18_MARK, VI0_DATA19_MARK, + VI0_DATA20_MARK, VI0_DATA21_MARK, + VI0_DATA22_MARK, VI0_DATA23_MARK, }; static const unsigned int vin0_data18_pins[] = { RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), @@ -2047,25 +1989,21 @@ static const unsigned int vin0_clk_mux[] = { }; /* - VIN1 ------------------------------------------------------------------- */ -static const union vin_data12 vin1_data_pins = { - .data12 = { - RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), - RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), - RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), - RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), - RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), - RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), - }, +static const unsigned int vin1_data_pins[] = { + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), }; -static const union vin_data12 vin1_data_mux = { - .data12 = { - VI1_DATA0_MARK, VI1_DATA1_MARK, - VI1_DATA2_MARK, VI1_DATA3_MARK, - VI1_DATA4_MARK, VI1_DATA5_MARK, - VI1_DATA6_MARK, VI1_DATA7_MARK, - VI1_DATA8_MARK, VI1_DATA9_MARK, - VI1_DATA10_MARK, VI1_DATA11_MARK, - }, +static const unsigned int vin1_data_mux[] = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, + VI1_DATA8_MARK, VI1_DATA9_MARK, + VI1_DATA10_MARK, VI1_DATA11_MARK, }; static const unsigned int vin1_sync_pins[] = { /* VI1_VSYNC#, VI1_HSYNC# */ @@ -2156,9 +2094,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_ex_irq3), SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(mmc_cd), SH_PFC_PIN_GROUP(mmc_wp), @@ -2198,13 +2136,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm4_a), SH_PFC_PIN_GROUP(pwm4_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), - SH_PFC_PIN_GROUP(rpc_clk1), - SH_PFC_PIN_GROUP(rpc_clk2), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4), + BUS_DATA_PIN_GROUP(rpc_clk, 1), + BUS_DATA_PIN_GROUP(rpc_clk, 2), SH_PFC_PIN_GROUP(rpc_ctrl), SH_PFC_PIN_GROUP(rpc_data), SH_PFC_PIN_GROUP(rpc_reset), @@ -2233,20 +2171,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tpu_to1), SH_PFC_PIN_GROUP(tpu_to2), SH_PFC_PIN_GROUP(tpu_to3), - VIN_DATA_PIN_GROUP(vin0_data, 8), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 16), + BUS_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 16), SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 20), - VIN_DATA_PIN_GROUP(vin0_data, 24), + BUS_DATA_PIN_GROUP(vin0_data, 20), + BUS_DATA_PIN_GROUP(vin0_data, 24), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 8), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 12), + BUS_DATA_PIN_GROUP(vin1_data, 8), + BUS_DATA_PIN_GROUP(vin1_data, 10), + BUS_DATA_PIN_GROUP(vin1_data, 12), SH_PFC_PIN_GROUP(vin1_sync), SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), @@ -2940,8 +2878,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, - u32 *pocctrl) +static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = pin & 0x1f; @@ -3139,7 +3076,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ } }; -static const struct sh_pfc_soc_operations pinmux_ops = { +static const struct sh_pfc_soc_operations r8a77980_pfc_ops = { .pin_to_pocctrl = r8a77980_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -3147,7 +3084,7 @@ static const struct sh_pfc_soc_operations pinmux_ops = { const struct sh_pfc_soc_info r8a77980_pinmux_info = { .name = "r8a77980_pfc", - .ops = &pinmux_ops, + .ops = &r8a77980_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index f44c7da3ec16..6c4ba9e16058 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -2339,6 +2339,16 @@ static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 +/* - MLB+ ------------------------------------------------------------------- */ +static const unsigned int mlb_3pin_pins[] = { + RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), +}; +static const unsigned int mlb_3pin_mux[] = { + MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ + /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -2817,20 +2827,13 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ - RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { +static const unsigned int qspi0_data_pins[] = { /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), /* QSPI0_IO2, QSPI0_IO3 */ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), }; -static const unsigned int qspi0_data4_mux[] = { +static const unsigned int qspi0_data_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK, }; @@ -2842,20 +2845,13 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ - RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { +static const unsigned int qspi1_data_pins[] = { /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), /* QSPI1_IO2, QSPI1_IO3 */ RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), }; -static const unsigned int qspi1_data4_mux[] = { +static const unsigned int qspi1_data_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK, }; @@ -3138,22 +3134,13 @@ static const unsigned int scif_clk_b_mux[] = { }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), -}; - -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; - -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; @@ -3186,22 +3173,13 @@ static const unsigned int sdhi0_wp_mux[] = { }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 8), -}; - -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; - -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; @@ -3234,27 +3212,7 @@ static const unsigned int sdhi1_wp_mux[] = { }; /* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 2), -}; - -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; - -static const unsigned int sdhi3_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), -}; - -static const unsigned int sdhi3_data4_mux[] = { - SD3_DAT0_MARK, SD3_DAT1_MARK, - SD3_DAT2_MARK, SD3_DAT3_MARK, -}; - -static const unsigned int sdhi3_data8_pins[] = { +static const unsigned int sdhi3_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), @@ -3262,7 +3220,7 @@ static const unsigned int sdhi3_data8_pins[] = { RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), }; -static const unsigned int sdhi3_data8_mux[] = { +static const unsigned int sdhi3_data_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, SD3_DAT4_MARK, SD3_DAT5_MARK, @@ -3604,38 +3562,34 @@ static const unsigned int vin4_data18_a_mux[] = { VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_a_pins = { - .data24 = { - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), - RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), - RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), - RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), - RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), - RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), - RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), - }, +static const unsigned int vin4_data_a_pins[] = { + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), }; -static const union vin_data vin4_data_a_mux = { - .data24 = { - VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, - VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, - VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, - VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, +static const unsigned int vin4_data_a_mux[] = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const unsigned int vin4_data18_b_pins[] = { @@ -3662,52 +3616,34 @@ static const unsigned int vin4_data18_b_mux[] = { VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_b_pins = { - .data24 = { - RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), - RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), - RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), - RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), - RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), - RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), - RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), - RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), - }, -}; - -static const union vin_data vin4_data_b_mux = { - .data24 = { - VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, - VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, - VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, - VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, -}; - -static const unsigned int vin4_g8_pins[] = { +static const unsigned int vin4_data_b_pins[] = { + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), }; -static const unsigned int vin4_g8_mux[] = { - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, +static const unsigned int vin4_data_b_mux[] = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const unsigned int vin4_sync_pins[] = { @@ -3744,30 +3680,26 @@ static const unsigned int vin4_clk_mux[] = { }; /* - VIN5 ------------------------------------------------------------------- */ -static const union vin_data16 vin5_data_a_pins = { - .data16 = { - RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), - RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12), - RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - }, +static const unsigned int vin5_data_a_pins[] = { + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), }; -static const union vin_data16 vin5_data_a_mux = { - .data16 = { - VI5_DATA0_A_MARK, VI5_DATA1_A_MARK, - VI5_DATA2_A_MARK, VI5_DATA3_A_MARK, - VI5_DATA4_A_MARK, VI5_DATA5_A_MARK, - VI5_DATA6_A_MARK, VI5_DATA7_A_MARK, - VI5_DATA8_A_MARK, VI5_DATA9_A_MARK, - VI5_DATA10_A_MARK, VI5_DATA11_A_MARK, - VI5_DATA12_A_MARK, VI5_DATA13_A_MARK, - VI5_DATA14_A_MARK, VI5_DATA15_A_MARK, - }, +static const unsigned int vin5_data_a_mux[] = { + VI5_DATA0_A_MARK, VI5_DATA1_A_MARK, + VI5_DATA2_A_MARK, VI5_DATA3_A_MARK, + VI5_DATA4_A_MARK, VI5_DATA5_A_MARK, + VI5_DATA6_A_MARK, VI5_DATA7_A_MARK, + VI5_DATA8_A_MARK, VI5_DATA9_A_MARK, + VI5_DATA10_A_MARK, VI5_DATA11_A_MARK, + VI5_DATA12_A_MARK, VI5_DATA13_A_MARK, + VI5_DATA14_A_MARK, VI5_DATA15_A_MARK, }; static const unsigned int vin5_data8_b_pins[] = { @@ -3784,20 +3716,6 @@ static const unsigned int vin5_data8_b_mux[] = { VI5_DATA6_B_MARK, VI5_DATA7_B_MARK, }; -static const unsigned int vin5_high8_pins[] = { - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), -}; - -static const unsigned int vin5_high8_mux[] = { - VI5_DATA8_A_MARK, VI5_DATA9_A_MARK, - VI5_DATA10_A_MARK, VI5_DATA11_A_MARK, - VI5_DATA12_A_MARK, VI5_DATA13_A_MARK, - VI5_DATA14_A_MARK, VI5_DATA15_A_MARK, -}; - static const unsigned int vin5_sync_a_pins[] = { /* HSYNC_N, VSYNC_N */ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9), @@ -3842,7 +3760,7 @@ static const unsigned int vin5_clk_b_mux[] = { static const struct { struct sh_pfc_pin_group common[255]; #ifdef CONFIG_PINCTRL_PFC_R8A77990 - struct sh_pfc_pin_group automotive[21]; + struct sh_pfc_pin_group automotive[22]; #endif } pinmux_groups = { .common = { @@ -3989,11 +3907,11 @@ static const struct { SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_clk_a), SH_PFC_PIN_GROUP(scif0_ctrl_a), @@ -4024,19 +3942,19 @@ static const struct { SH_PFC_PIN_GROUP(scif5_data_c), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_data8), + BUS_DATA_PIN_GROUP(sdhi3_data, 1), + BUS_DATA_PIN_GROUP(sdhi3_data, 4), + BUS_DATA_PIN_GROUP(sdhi3_data, 8), SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), @@ -4071,31 +3989,31 @@ static const struct { SH_PFC_PIN_GROUP(usb0_id), SH_PFC_PIN_GROUP(usb30), SH_PFC_PIN_GROUP(usb30_id), - VIN_DATA_PIN_GROUP(vin4_data, 8, _a), - VIN_DATA_PIN_GROUP(vin4_data, 10, _a), - VIN_DATA_PIN_GROUP(vin4_data, 12, _a), - VIN_DATA_PIN_GROUP(vin4_data, 16, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _a), + BUS_DATA_PIN_GROUP(vin4_data, 10, _a), + BUS_DATA_PIN_GROUP(vin4_data, 12, _a), + BUS_DATA_PIN_GROUP(vin4_data, 16, _a), SH_PFC_PIN_GROUP(vin4_data18_a), - VIN_DATA_PIN_GROUP(vin4_data, 20, _a), - VIN_DATA_PIN_GROUP(vin4_data, 24, _a), - VIN_DATA_PIN_GROUP(vin4_data, 8, _b), - VIN_DATA_PIN_GROUP(vin4_data, 10, _b), - VIN_DATA_PIN_GROUP(vin4_data, 12, _b), - VIN_DATA_PIN_GROUP(vin4_data, 16, _b), + BUS_DATA_PIN_GROUP(vin4_data, 20, _a), + BUS_DATA_PIN_GROUP(vin4_data, 24, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _b), + BUS_DATA_PIN_GROUP(vin4_data, 10, _b), + BUS_DATA_PIN_GROUP(vin4_data, 12, _b), + BUS_DATA_PIN_GROUP(vin4_data, 16, _b), SH_PFC_PIN_GROUP(vin4_data18_b), - VIN_DATA_PIN_GROUP(vin4_data, 20, _b), - VIN_DATA_PIN_GROUP(vin4_data, 24, _b), - SH_PFC_PIN_GROUP(vin4_g8), + BUS_DATA_PIN_GROUP(vin4_data, 20, _b), + BUS_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(vin4_clk), - VIN_DATA_PIN_GROUP(vin5_data, 8, _a), - VIN_DATA_PIN_GROUP(vin5_data, 10, _a), - VIN_DATA_PIN_GROUP(vin5_data, 12, _a), - VIN_DATA_PIN_GROUP(vin5_data, 16, _a), + BUS_DATA_PIN_GROUP(vin5_data, 8, _a), + BUS_DATA_PIN_GROUP(vin5_data, 10, _a), + BUS_DATA_PIN_GROUP(vin5_data, 12, _a), + BUS_DATA_PIN_GROUP(vin5_data, 16, _a), SH_PFC_PIN_GROUP(vin5_data8_b), - SH_PFC_PIN_GROUP(vin5_high8), + SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data_a, 8, 8), SH_PFC_PIN_GROUP(vin5_sync_a), SH_PFC_PIN_GROUP(vin5_field_a), SH_PFC_PIN_GROUP(vin5_clkenb_a), @@ -4125,6 +4043,7 @@ static const struct { SH_PFC_PIN_GROUP(drif3_ctrl_b), SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), + SH_PFC_PIN_GROUP(mlb_3pin), } #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ }; @@ -4315,6 +4234,12 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq5", }; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 +static const char * const mlb_3pin_groups[] = { + "mlb_3pin", +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -4569,7 +4494,7 @@ static const char * const vin5_groups[] = { static const struct { struct sh_pfc_function common[49]; #ifdef CONFIG_PINCTRL_PFC_R8A77990 - struct sh_pfc_function automotive[4]; + struct sh_pfc_function automotive[5]; #endif } pinmux_functions = { .common = { @@ -4629,6 +4554,7 @@ static const struct { SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), + SH_PFC_FUNCTION(mlb_3pin), } #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ }; @@ -5115,8 +5041,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, - u32 *pocctrl) +static int r8a77990_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -5339,7 +5264,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a77990_pfc_ops = { .pin_to_pocctrl = r8a77990_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -5348,7 +5273,7 @@ static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = { #ifdef CONFIG_PINCTRL_PFC_R8A774C0 const struct sh_pfc_soc_info r8a774c0_pinmux_info = { .name = "r8a774c0_pfc", - .ops = &r8a77990_pinmux_ops, + .ops = &r8a77990_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -5372,7 +5297,7 @@ const struct sh_pfc_soc_info r8a774c0_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A77990 const struct sh_pfc_soc_info r8a77990_pinmux_info = { .name = "r8a77990_pfc", - .ops = &r8a77990_pinmux_ops, + .ops = &r8a77990_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c index c56e1e4c13b3..445c903a121a 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77995.c +++ b/drivers/pinctrl/renesas/pfc-r8a77995.c @@ -1257,31 +1257,23 @@ static const unsigned int i2c3_b_mux[] = { SCL3_B_MARK, SDA3_B_MARK, }; -/* - MMC ------------------------------------------------------------------- */ -static const unsigned int mmc_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), -}; -static const unsigned int mmc_data1_mux[] = { - MMC_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), - RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), +/* - MLB+ ------------------------------------------------------------------- */ +static const unsigned int mlb_3pin_pins[] = { + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), }; -static const unsigned int mmc_data4_mux[] = { - MMC_D0_MARK, MMC_D1_MARK, - MMC_D2_MARK, MMC_D3_MARK, +static const unsigned int mlb_3pin_mux[] = { + MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, }; -static const unsigned int mmc_data8_pins[] = { + +/* - MMC ------------------------------------------------------------------- */ +static const unsigned int mmc_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, @@ -1950,37 +1942,33 @@ static const unsigned int vin4_data18_mux[] = { VI4_DATA20_MARK, VI4_DATA21_MARK, VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_pins = { - .data24 = { - RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), - RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), - RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), - RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), - RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), - RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), - RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), - RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), - RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), - RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), - RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), - RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), - }, +static const unsigned int vin4_data_pins[] = { + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), + RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), + RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), + RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), }; -static const union vin_data vin4_data_mux = { - .data24 = { - VI4_DATA0_MARK, VI4_DATA1_MARK, - VI4_DATA2_MARK, VI4_DATA3_MARK, - VI4_DATA4_MARK, VI4_DATA5_MARK, - VI4_DATA6_MARK, VI4_DATA7_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, +static const unsigned int vin4_data_mux[] = { + VI4_DATA0_MARK, VI4_DATA1_MARK, + VI4_DATA2_MARK, VI4_DATA3_MARK, + VI4_DATA4_MARK, VI4_DATA5_MARK, + VI4_DATA6_MARK, VI4_DATA7_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const unsigned int vin4_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -2049,9 +2037,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c2_b), SH_PFC_PIN_GROUP(i2c3_a), SH_PFC_PIN_GROUP(i2c3_b), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(mlb_3pin), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), @@ -2128,13 +2117,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(ssi4_ctrl_b), SH_PFC_PIN_GROUP(ssi4_data_b), SH_PFC_PIN_GROUP(usb0), - VIN_DATA_PIN_GROUP(vin4_data, 8), - VIN_DATA_PIN_GROUP(vin4_data, 10), - VIN_DATA_PIN_GROUP(vin4_data, 12), - VIN_DATA_PIN_GROUP(vin4_data, 16), + BUS_DATA_PIN_GROUP(vin4_data, 8), + BUS_DATA_PIN_GROUP(vin4_data, 10), + BUS_DATA_PIN_GROUP(vin4_data, 12), + BUS_DATA_PIN_GROUP(vin4_data, 16), SH_PFC_PIN_GROUP(vin4_data18), - VIN_DATA_PIN_GROUP(vin4_data, 20), - VIN_DATA_PIN_GROUP(vin4_data, 24), + BUS_DATA_PIN_GROUP(vin4_data, 20), + BUS_DATA_PIN_GROUP(vin4_data, 24), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), @@ -2210,6 +2199,10 @@ static const char * const i2c3_groups[] = { "i2c3_b", }; +static const char * const mlb_3pin_groups[] = { + "mlb_3pin", +}; + static const char * const mmc_groups[] = { "mmc_data1", "mmc_data4", @@ -2217,6 +2210,49 @@ static const char * const mmc_groups[] = { "mmc_ctrl", }; +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_txd", + "msiof0_rxd", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk", + "msiof1_sync", + "msiof1_ss1", + "msiof1_ss2", + "msiof1_txd", + "msiof1_rxd", +}; + +static const char * const msiof2_groups[] = { + "msiof2_clk", + "msiof2_sync_a", + "msiof2_sync_b", + "msiof2_ss1", + "msiof2_ss2", + "msiof2_txd", + "msiof2_rxd", +}; + +static const char * const msiof3_groups[] = { + "msiof3_clk_a", + "msiof3_sync_a", + "msiof3_ss1_a", + "msiof3_ss2_a", + "msiof3_txd_a", + "msiof3_rxd_a", + "msiof3_clk_b", + "msiof3_sync_b", + "msiof3_ss1_b", + "msiof3_ss2_b", + "msiof3_txd_b", + "msiof3_rxd_b", +}; + static const char * const pwm0_groups[] = { "pwm0_a", "pwm0_b", @@ -2314,49 +2350,6 @@ static const char * const vin4_groups[] = { "vin4_clk", }; -static const char * const msiof0_groups[] = { - "msiof0_clk", - "msiof0_sync", - "msiof0_ss1", - "msiof0_ss2", - "msiof0_txd", - "msiof0_rxd", -}; - -static const char * const msiof1_groups[] = { - "msiof1_clk", - "msiof1_sync", - "msiof1_ss1", - "msiof1_ss2", - "msiof1_txd", - "msiof1_rxd", -}; - -static const char * const msiof2_groups[] = { - "msiof2_clk", - "msiof2_sync_a", - "msiof2_sync_b", - "msiof2_ss1", - "msiof2_ss2", - "msiof2_txd", - "msiof2_rxd", -}; - -static const char * const msiof3_groups[] = { - "msiof3_clk_a", - "msiof3_sync_a", - "msiof3_ss1_a", - "msiof3_ss2_a", - "msiof3_txd_a", - "msiof3_rxd_a", - "msiof3_clk_b", - "msiof3_sync_b", - "msiof3_ss1_b", - "msiof3_ss2_b", - "msiof3_txd_b", - "msiof3_rxd_b", -}; - static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb0), @@ -2370,6 +2363,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(mlb_3pin), SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), @@ -2842,7 +2836,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -3078,7 +3072,7 @@ r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, const struct pinmux_bias_reg *reg; unsigned int bit; - reg = rcar_pin_to_bias_reg(pfc, pin, &bit); + reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); if (!reg) return reg; @@ -3144,7 +3138,7 @@ static void r8a77995_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, sh_pfc_write(pfc, reg->puen, enable); } -static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a77995_pfc_ops = { .pin_to_pocctrl = r8a77995_pin_to_pocctrl, .get_bias = r8a77995_pinmux_get_bias, .set_bias = r8a77995_pinmux_set_bias, @@ -3152,7 +3146,7 @@ static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = { const struct sh_pfc_soc_info r8a77995_pinmux_info = { .name = "r8a77995_pfc", - .ops = &r8a77995_pinmux_ops, + .ops = &r8a77995_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c index 83580385c3ca..4a668a04b7ca 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779a0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c @@ -576,23 +576,23 @@ FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 FM(IP2SR5_27_24) IP2 FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 FM(IP2SR5_31_28) IP2SR5_31_28 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ -#define MOD_SEL2_14_15 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3) -#define MOD_SEL2_12_13 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3) -#define MOD_SEL2_10_11 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3) -#define MOD_SEL2_8_9 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3) -#define MOD_SEL2_6_7 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3) -#define MOD_SEL2_4_5 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3) -#define MOD_SEL2_2_3 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3) +#define MOD_SEL2_15_14 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3) +#define MOD_SEL2_13_12 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3) +#define MOD_SEL2_11_10 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3) +#define MOD_SEL2_9_8 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3) +#define MOD_SEL2_7_6 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3) +#define MOD_SEL2_5_4 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3) +#define MOD_SEL2_3_2 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3) #define PINMUX_MOD_SELS \ \ -MOD_SEL2_14_15 \ -MOD_SEL2_12_13 \ -MOD_SEL2_10_11 \ -MOD_SEL2_8_9 \ -MOD_SEL2_6_7 \ -MOD_SEL2_4_5 \ -MOD_SEL2_2_3 +MOD_SEL2_15_14 \ +MOD_SEL2_13_12 \ +MOD_SEL2_11_10 \ +MOD_SEL2_9_8 \ +MOD_SEL2_7_6 \ +MOD_SEL2_5_4 \ +MOD_SEL2_3_2 #define PINMUX_PHYS \ FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \ @@ -2009,30 +2009,14 @@ static const unsigned int intc_ex_irq5_mux[] = { }; /* - MMC -------------------------------------------------------------------- */ -static const unsigned int mmc_data1_pins[] = { - /* MMC_SD_D0 */ - RCAR_GP_PIN(0, 19), -}; -static const unsigned int mmc_data1_mux[] = { - MMC_SD_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* MMC_SD_D[0:3] */ - RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), - RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22), -}; -static const unsigned int mmc_data4_mux[] = { - MMC_SD_D0_MARK, MMC_SD_D1_MARK, - MMC_SD_D2_MARK, MMC_SD_D3_MARK, -}; -static const unsigned int mmc_data8_pins[] = { +static const unsigned int mmc_data_pins[] = { /* MMC_SD_D[0:3], MMC_D[4:7] */ RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 27), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC_SD_D0_MARK, MMC_SD_D1_MARK, MMC_SD_D2_MARK, MMC_SD_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, @@ -2384,19 +2368,12 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { +static const unsigned int qspi0_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), }; -static const unsigned int qspi0_data4_mux[] = { +static const unsigned int qspi0_data_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK }; @@ -2409,19 +2386,12 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { +static const unsigned int qspi1_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), }; -static const unsigned int qspi1_data4_mux[] = { +static const unsigned int qspi1_data_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK }; @@ -2715,9 +2685,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(mmc_cd), SH_PFC_PIN_GROUP(mmc_wp), @@ -2767,11 +2737,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm4), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), @@ -3696,13 +3666,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* RESERVED 19, 18, 17, 16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - MOD_SEL2_14_15 - MOD_SEL2_12_13 - MOD_SEL2_10_11 - MOD_SEL2_8_9 - MOD_SEL2_6_7 - MOD_SEL2_4_5 - MOD_SEL2_2_3 + MOD_SEL2_15_14 + MOD_SEL2_13_12 + MOD_SEL2_11_10 + MOD_SEL2_9_8 + MOD_SEL2_7_6 + MOD_SEL2_5_4 + MOD_SEL2_3_2 0, 0, 0, 0, )) }, @@ -4041,8 +4011,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a779a0_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, - u32 *pocctrl) +static int r8a779a0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = pin & 0x1f; @@ -4429,7 +4398,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static const struct sh_pfc_soc_operations pinmux_ops = { +static const struct sh_pfc_soc_operations r8a779a0_pfc_ops = { .pin_to_pocctrl = r8a779a0_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -4437,7 +4406,7 @@ static const struct sh_pfc_soc_operations pinmux_ops = { const struct sh_pfc_soc_info r8a779a0_pinmux_info = { .name = "r8a779a0_pfc", - .ops = &pinmux_ops, + .ops = &r8a779a0_pfc_ops, .unlock_reg = 0x1ff, /* PMMRn mask */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c new file mode 100644 index 000000000000..91860608242c --- /dev/null +++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c @@ -0,0 +1,2126 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R8A779F0 processor support - PFC hardware block. + * + * Copyright (C) 2021 Renesas Electronics Corp. + * + * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c + */ + +#include <linux/errno.h> +#include <linux/io.h> +#include <linux/kernel.h> + +#include "sh_pfc.h" + +#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) + +#define CPU_ALL_GP(fn, sfx) \ + PORT_GP_CFG_21(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_25(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_17(2, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_19(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(PRESETOUT0_N, "PRESETOUT0#", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ + PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) + +/* + * F_() : just information + * FM() : macro for FN_xxx / xxx_MARK + */ + +/* GPSR0 */ +#define GPSR0_20 F_(IRQ3, IP2SR0_19_16) +#define GPSR0_19 F_(IRQ2, IP2SR0_15_12) +#define GPSR0_18 F_(IRQ1, IP2SR0_11_8) +#define GPSR0_17 F_(IRQ0, IP2SR0_7_4) +#define GPSR0_16 F_(MSIOF0_SS2, IP2SR0_3_0) +#define GPSR0_15 F_(MSIOF0_SS1, IP1SR0_31_28) +#define GPSR0_14 F_(MSIOF0_SCK, IP1SR0_27_24) +#define GPSR0_13 F_(MSIOF0_TXD, IP1SR0_23_20) +#define GPSR0_12 F_(MSIOF0_RXD, IP1SR0_19_16) +#define GPSR0_11 F_(MSIOF0_SYNC, IP1SR0_15_12) +#define GPSR0_10 F_(CTS0_N, IP1SR0_11_8) +#define GPSR0_9 F_(RTS0_N, IP1SR0_7_4) +#define GPSR0_8 F_(SCK0, IP1SR0_3_0) +#define GPSR0_7 F_(TX0, IP0SR0_31_28) +#define GPSR0_6 F_(RX0, IP0SR0_27_24) +#define GPSR0_5 F_(HRTS0_N, IP0SR0_23_20) +#define GPSR0_4 F_(HCTS0_N, IP0SR0_19_16) +#define GPSR0_3 F_(HTX0, IP0SR0_15_12) +#define GPSR0_2 F_(HRX0, IP0SR0_11_8) +#define GPSR0_1 F_(HSCK0, IP0SR0_7_4) +#define GPSR0_0 F_(SCIF_CLK, IP0SR0_3_0) + +/* GPSR1 */ +#define GPSR1_24 FM(SD_WP) +#define GPSR1_23 FM(SD_CD) +#define GPSR1_22 FM(MMC_SD_CMD) +#define GPSR1_21 FM(MMC_D7) +#define GPSR1_20 FM(MMC_DS) +#define GPSR1_19 FM(MMC_D6) +#define GPSR1_18 FM(MMC_D4) +#define GPSR1_17 FM(MMC_D5) +#define GPSR1_16 FM(MMC_SD_D3) +#define GPSR1_15 FM(MMC_SD_D2) +#define GPSR1_14 FM(MMC_SD_D1) +#define GPSR1_13 FM(MMC_SD_D0) +#define GPSR1_12 FM(MMC_SD_CLK) +#define GPSR1_11 FM(GP1_11) +#define GPSR1_10 FM(GP1_10) +#define GPSR1_9 FM(GP1_09) +#define GPSR1_8 FM(GP1_08) +#define GPSR1_7 F_(GP1_07, IP0SR1_31_28) +#define GPSR1_6 F_(GP1_06, IP0SR1_27_24) +#define GPSR1_5 F_(GP1_05, IP0SR1_23_20) +#define GPSR1_4 F_(GP1_04, IP0SR1_19_16) +#define GPSR1_3 F_(GP1_03, IP0SR1_15_12) +#define GPSR1_2 F_(GP1_02, IP0SR1_11_8) +#define GPSR1_1 F_(GP1_01, IP0SR1_7_4) +#define GPSR1_0 F_(GP1_00, IP0SR1_3_0) + +/* GPSR2 */ +#define GPSR2_16 FM(PCIE1_CLKREQ_N) +#define GPSR2_15 FM(PCIE0_CLKREQ_N) +#define GPSR2_14 FM(QSPI0_IO3) +#define GPSR2_13 FM(QSPI0_SSL) +#define GPSR2_12 FM(QSPI0_MISO_IO1) +#define GPSR2_11 FM(QSPI0_IO2) +#define GPSR2_10 FM(QSPI0_SPCLK) +#define GPSR2_9 FM(QSPI0_MOSI_IO0) +#define GPSR2_8 FM(QSPI1_SPCLK) +#define GPSR2_7 FM(QSPI1_MOSI_IO0) +#define GPSR2_6 FM(QSPI1_IO2) +#define GPSR2_5 FM(QSPI1_MISO_IO1) +#define GPSR2_4 FM(QSPI1_IO3) +#define GPSR2_3 FM(QSPI1_SSL) +#define GPSR2_2 FM(RPC_RESET_N) +#define GPSR2_1 FM(RPC_WP_N) +#define GPSR2_0 FM(RPC_INT_N) + +/* GPSR3 */ +#define GPSR3_18 FM(TSN0_AVTP_CAPTURE_B) +#define GPSR3_17 FM(TSN0_AVTP_MATCH_B) +#define GPSR3_16 FM(TSN0_AVTP_PPS) +#define GPSR3_15 FM(TSN1_AVTP_CAPTURE_B) +#define GPSR3_14 FM(TSN1_AVTP_MATCH_B) +#define GPSR3_13 FM(TSN1_AVTP_PPS) +#define GPSR3_12 FM(TSN0_MAGIC_B) +#define GPSR3_11 FM(TSN1_PHY_INT_B) +#define GPSR3_10 FM(TSN0_PHY_INT_B) +#define GPSR3_9 FM(TSN2_PHY_INT_B) +#define GPSR3_8 FM(TSN0_LINK_B) +#define GPSR3_7 FM(TSN2_LINK_B) +#define GPSR3_6 FM(TSN1_LINK_B) +#define GPSR3_5 FM(TSN1_MDC_B) +#define GPSR3_4 FM(TSN0_MDC_B) +#define GPSR3_3 FM(TSN2_MDC_B) +#define GPSR3_2 FM(TSN0_MDIO_B) +#define GPSR3_1 FM(TSN2_MDIO_B) +#define GPSR3_0 FM(TSN1_MDIO_B) + +/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */ +#define IP0SR0_3_0 FM(SCIF_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_7_4 FM(HSCK0) FM(SCK3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(TSN0_AVTP_CAPTURE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_11_8 FM(HRX0) FM(RX3) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) FM(TSN0_AVTP_MATCH_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_15_12 FM(HTX0) FM(TX3) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_19_16 FM(HCTS0_N) FM(CTS3_N) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) FM(TSN0_MDC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_23_20 FM(HRTS0_N) FM(RTS3_N) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) FM(TSN0_MDIO_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_27_24 FM(RX0) FM(HRX1) F_(0, 0) FM(MSIOF1_RXD) F_(0, 0) FM(TSN1_AVTP_MATCH_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_31_28 FM(TX0) FM(HTX1) F_(0, 0) FM(MSIOF1_TXD) F_(0, 0) FM(TSN1_AVTP_CAPTURE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */ +#define IP1SR0_3_0 FM(SCK0) FM(HSCK1) F_(0, 0) FM(MSIOF1_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_7_4 FM(RTS0_N) FM(HRTS1_N) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) FM(TSN1_MDIO_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_11_8 FM(CTS0_N) FM(HCTS1_N) F_(0, 0) FM(MSIOF1_SYNC) F_(0, 0) FM(TSN1_MDC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_15_12 FM(MSIOF0_SYNC) FM(HCTS3_N) FM(CTS1_N) FM(IRQ4) F_(0, 0) FM(TSN0_LINK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_19_16 FM(MSIOF0_RXD) FM(HRX3) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_23_20 FM(MSIOF0_TXD) FM(HTX3) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_27_24 FM(MSIOF0_SCK) FM(HSCK3) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_31_28 FM(MSIOF0_SS1) FM(HRTS3_N) FM(RTS1_N) FM(IRQ5) F_(0, 0) FM(TSN1_LINK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */ +#define IP2SR0_3_0 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN2_LINK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_7_4 FM(IRQ0) F_(0, 0) F_(0, 0) FM(MSIOF1_SS1) F_(0, 0) FM(TSN0_MAGIC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_11_8 FM(IRQ1) F_(0, 0) F_(0, 0) FM(MSIOF1_SS2) F_(0, 0) FM(TSN0_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_15_12 FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN1_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_19_16 FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN2_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */ +#define IP0SR1_3_0 FM(GP1_00) FM(TCLK1) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_7_4 FM(GP1_01) FM(TCLK4) FM(HRX2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_11_8 FM(GP1_02) F_(0, 0) FM(HTX2) FM(MSIOF2_SS1) F_(0, 0) FM(TSN2_MDC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_15_12 FM(GP1_03) FM(TCLK2) FM(HCTS2_N) FM(MSIOF2_SS2) FM(CTS4_N) FM(TSN2_MDIO_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_19_16 FM(GP1_04) FM(TCLK3) FM(HRTS2_N) FM(MSIOF2_SYNC) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_23_20 FM(GP1_05) FM(MSIOF2_SCK) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_27_24 FM(GP1_06) FM(MSIOF2_RXD) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_31_28 FM(GP1_07) FM(MSIOF2_TXD) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +#define PINMUX_GPSR \ + GPSR1_24 \ + GPSR1_23 \ + GPSR1_22 \ + GPSR1_21 \ +GPSR0_20 GPSR1_20 \ +GPSR0_19 GPSR1_19 \ +GPSR0_18 GPSR1_18 GPSR3_18 \ +GPSR0_17 GPSR1_17 GPSR3_17 \ +GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 \ +GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 \ +GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 \ +GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 \ +GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 \ +GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 \ +GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 \ +GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 \ +GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 \ +GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 \ +GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 \ +GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 \ +GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 \ +GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 \ +GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 \ +GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 \ +GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 + +#define PINMUX_IPSR \ +\ +FM(IP0SR0_3_0) IP0SR0_3_0 FM(IP1SR0_3_0) IP1SR0_3_0 FM(IP2SR0_3_0) IP2SR0_3_0 \ +FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 \ +FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \ +FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 FM(IP2SR0_15_12) IP2SR0_15_12 \ +FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 FM(IP2SR0_19_16) IP2SR0_19_16 \ +FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 FM(IP2SR0_23_20) IP2SR0_23_20 \ +FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 FM(IP2SR0_27_24) IP2SR0_27_24 \ +FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 FM(IP2SR0_31_28) IP2SR0_31_28 \ +\ +FM(IP0SR1_3_0) IP0SR1_3_0 \ +FM(IP0SR1_7_4) IP0SR1_7_4 \ +FM(IP0SR1_11_8) IP0SR1_11_8 \ +FM(IP0SR1_15_12) IP0SR1_15_12 \ +FM(IP0SR1_19_16) IP0SR1_19_16 \ +FM(IP0SR1_23_20) IP0SR1_23_20 \ +FM(IP0SR1_27_24) IP0SR1_27_24 \ +FM(IP0SR1_31_28) IP0SR1_31_28 + +/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ +#define MOD_SEL1_11_10 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3) +#define MOD_SEL1_9_8 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3) +#define MOD_SEL1_7_6 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3) +#define MOD_SEL1_5_4 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3) +#define MOD_SEL1_3_2 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3) +#define MOD_SEL1_1_0 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3) + +#define PINMUX_MOD_SELS \ +\ +MOD_SEL1_11_10 \ +MOD_SEL1_9_8 \ +MOD_SEL1_7_6 \ +MOD_SEL1_5_4 \ +MOD_SEL1_3_2 \ +MOD_SEL1_1_0 + +#define PINMUX_PHYS \ + FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \ + FM(SCL4) FM(SDA4) FM(SCL5) FM(SDA5) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + +#define F_(x, y) +#define FM(x) FN_##x, + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_FUNCTION_END, +#undef F_ +#undef FM + +#define F_(x, y) +#define FM(x) x##_MARK, + PINMUX_MARK_BEGIN, + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_PHYS + PINMUX_MARK_END, +#undef F_ +#undef FM +}; + +static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), + + PINMUX_SINGLE(SD_WP), + PINMUX_SINGLE(SD_CD), + PINMUX_SINGLE(MMC_SD_CMD), + PINMUX_SINGLE(MMC_D7), + PINMUX_SINGLE(MMC_DS), + PINMUX_SINGLE(MMC_D6), + PINMUX_SINGLE(MMC_D4), + PINMUX_SINGLE(MMC_D5), + PINMUX_SINGLE(MMC_SD_D3), + PINMUX_SINGLE(MMC_SD_D2), + PINMUX_SINGLE(MMC_SD_D1), + PINMUX_SINGLE(MMC_SD_D0), + PINMUX_SINGLE(MMC_SD_CLK), + PINMUX_SINGLE(PCIE1_CLKREQ_N), + PINMUX_SINGLE(PCIE0_CLKREQ_N), + PINMUX_SINGLE(QSPI0_IO3), + PINMUX_SINGLE(QSPI0_SSL), + PINMUX_SINGLE(QSPI0_MISO_IO1), + PINMUX_SINGLE(QSPI0_IO2), + PINMUX_SINGLE(QSPI0_SPCLK), + PINMUX_SINGLE(QSPI0_MOSI_IO0), + PINMUX_SINGLE(QSPI1_SPCLK), + PINMUX_SINGLE(QSPI1_MOSI_IO0), + PINMUX_SINGLE(QSPI1_IO2), + PINMUX_SINGLE(QSPI1_MISO_IO1), + PINMUX_SINGLE(QSPI1_IO3), + PINMUX_SINGLE(QSPI1_SSL), + PINMUX_SINGLE(RPC_RESET_N), + PINMUX_SINGLE(RPC_WP_N), + PINMUX_SINGLE(RPC_INT_N), + + PINMUX_SINGLE(TSN0_AVTP_CAPTURE_B), + PINMUX_SINGLE(TSN0_AVTP_MATCH_B), + PINMUX_SINGLE(TSN0_AVTP_PPS), + PINMUX_SINGLE(TSN1_AVTP_CAPTURE_B), + PINMUX_SINGLE(TSN1_AVTP_MATCH_B), + PINMUX_SINGLE(TSN1_AVTP_PPS), + PINMUX_SINGLE(TSN0_MAGIC_B), + PINMUX_SINGLE(TSN1_PHY_INT_B), + PINMUX_SINGLE(TSN0_PHY_INT_B), + PINMUX_SINGLE(TSN2_PHY_INT_B), + PINMUX_SINGLE(TSN0_LINK_B), + PINMUX_SINGLE(TSN2_LINK_B), + PINMUX_SINGLE(TSN1_LINK_B), + PINMUX_SINGLE(TSN1_MDC_B), + PINMUX_SINGLE(TSN0_MDC_B), + PINMUX_SINGLE(TSN2_MDC_B), + PINMUX_SINGLE(TSN0_MDIO_B), + PINMUX_SINGLE(TSN2_MDIO_B), + PINMUX_SINGLE(TSN1_MDIO_B), + + /* IP0SR0 */ + PINMUX_IPSR_GPSR(IP0SR0_3_0, SCIF_CLK), + + PINMUX_IPSR_GPSR(IP0SR0_7_4, HSCK0), + PINMUX_IPSR_GPSR(IP0SR0_7_4, SCK3), + PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SCK), + PINMUX_IPSR_GPSR(IP0SR0_7_4, TSN0_AVTP_CAPTURE_A), + + PINMUX_IPSR_GPSR(IP0SR0_11_8, HRX0), + PINMUX_IPSR_GPSR(IP0SR0_11_8, RX3), + PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_RXD), + PINMUX_IPSR_GPSR(IP0SR0_11_8, TSN0_AVTP_MATCH_A), + + PINMUX_IPSR_GPSR(IP0SR0_15_12, HTX0), + PINMUX_IPSR_GPSR(IP0SR0_15_12, TX3), + PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_TXD), + + PINMUX_IPSR_GPSR(IP0SR0_19_16, HCTS0_N), + PINMUX_IPSR_GPSR(IP0SR0_19_16, CTS3_N), + PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_SS1), + PINMUX_IPSR_GPSR(IP0SR0_19_16, TSN0_MDC_A), + + PINMUX_IPSR_GPSR(IP0SR0_23_20, HRTS0_N), + PINMUX_IPSR_GPSR(IP0SR0_23_20, RTS3_N), + PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_SS2), + PINMUX_IPSR_GPSR(IP0SR0_23_20, TSN0_MDIO_A), + + PINMUX_IPSR_GPSR(IP0SR0_27_24, RX0), + PINMUX_IPSR_GPSR(IP0SR0_27_24, HRX1), + PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF1_RXD), + PINMUX_IPSR_GPSR(IP0SR0_27_24, TSN1_AVTP_MATCH_A), + + PINMUX_IPSR_GPSR(IP0SR0_31_28, TX0), + PINMUX_IPSR_GPSR(IP0SR0_31_28, HTX1), + PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF1_TXD), + PINMUX_IPSR_GPSR(IP0SR0_31_28, TSN1_AVTP_CAPTURE_A), + + /* IP1SR0 */ + PINMUX_IPSR_GPSR(IP1SR0_3_0, SCK0), + PINMUX_IPSR_GPSR(IP1SR0_3_0, HSCK1), + PINMUX_IPSR_GPSR(IP1SR0_3_0, MSIOF1_SCK), + + PINMUX_IPSR_GPSR(IP1SR0_7_4, RTS0_N), + PINMUX_IPSR_GPSR(IP1SR0_7_4, HRTS1_N), + PINMUX_IPSR_GPSR(IP1SR0_7_4, MSIOF3_SYNC), + PINMUX_IPSR_GPSR(IP1SR0_7_4, TSN1_MDIO_A), + + PINMUX_IPSR_GPSR(IP1SR0_11_8, CTS0_N), + PINMUX_IPSR_GPSR(IP1SR0_11_8, HCTS1_N), + PINMUX_IPSR_GPSR(IP1SR0_11_8, MSIOF1_SYNC), + PINMUX_IPSR_GPSR(IP1SR0_11_8, TSN1_MDC_A), + + PINMUX_IPSR_GPSR(IP1SR0_15_12, MSIOF0_SYNC), + PINMUX_IPSR_GPSR(IP1SR0_15_12, HCTS3_N), + PINMUX_IPSR_GPSR(IP1SR0_15_12, CTS1_N), + PINMUX_IPSR_GPSR(IP1SR0_15_12, IRQ4), + PINMUX_IPSR_GPSR(IP1SR0_15_12, TSN0_LINK_A), + + PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF0_RXD), + PINMUX_IPSR_GPSR(IP1SR0_19_16, HRX3), + PINMUX_IPSR_GPSR(IP1SR0_19_16, RX1), + + PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF0_TXD), + PINMUX_IPSR_GPSR(IP1SR0_23_20, HTX3), + PINMUX_IPSR_GPSR(IP1SR0_23_20, TX1), + + PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF0_SCK), + PINMUX_IPSR_GPSR(IP1SR0_27_24, HSCK3), + PINMUX_IPSR_GPSR(IP1SR0_27_24, SCK1), + + PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF0_SS1), + PINMUX_IPSR_GPSR(IP1SR0_31_28, HRTS3_N), + PINMUX_IPSR_GPSR(IP1SR0_31_28, RTS1_N), + PINMUX_IPSR_GPSR(IP1SR0_31_28, IRQ5), + PINMUX_IPSR_GPSR(IP1SR0_31_28, TSN1_LINK_A), + + /* IP2SR0 */ + PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF0_SS2), + PINMUX_IPSR_GPSR(IP2SR0_3_0, TSN2_LINK_A), + + PINMUX_IPSR_GPSR(IP2SR0_7_4, IRQ0), + PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF1_SS1), + PINMUX_IPSR_GPSR(IP2SR0_7_4, TSN0_MAGIC_A), + + PINMUX_IPSR_GPSR(IP2SR0_11_8, IRQ1), + PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF1_SS2), + PINMUX_IPSR_GPSR(IP2SR0_11_8, TSN0_PHY_INT_A), + + PINMUX_IPSR_GPSR(IP2SR0_15_12, IRQ2), + PINMUX_IPSR_GPSR(IP2SR0_15_12, TSN1_PHY_INT_A), + + PINMUX_IPSR_GPSR(IP2SR0_19_16, IRQ3), + PINMUX_IPSR_GPSR(IP2SR0_19_16, TSN2_PHY_INT_A), + + /* IP0SR1 */ + /* GP1_00 = SCL0 */ + PINMUX_IPSR_MSEL(IP0SR1_3_0, GP1_00, SEL_I2C0_0), + PINMUX_IPSR_MSEL(IP0SR1_3_0, TCLK1, SEL_I2C0_0), + PINMUX_IPSR_MSEL(IP0SR1_3_0, HSCK2, SEL_I2C0_0), + PINMUX_IPSR_PHYS(IP0SR1_3_0, SCL0, SEL_I2C0_3), + + /* GP1_01 = SDA0 */ + PINMUX_IPSR_MSEL(IP0SR1_7_4, GP1_01, SEL_I2C0_0), + PINMUX_IPSR_MSEL(IP0SR1_7_4, TCLK4, SEL_I2C0_0), + PINMUX_IPSR_MSEL(IP0SR1_7_4, HRX2, SEL_I2C0_0), + PINMUX_IPSR_PHYS(IP0SR1_7_4, SDA0, SEL_I2C0_3), + + /* GP1_02 = SCL1 */ + PINMUX_IPSR_MSEL(IP0SR1_11_8, GP1_02, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR1_11_8, HTX2, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR1_11_8, MSIOF2_SS1, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR1_11_8, TSN2_MDC_A, SEL_I2C1_0), + PINMUX_IPSR_PHYS(IP0SR1_11_8, SCL1, SEL_I2C1_3), + + /* GP1_03 = SDA1 */ + PINMUX_IPSR_MSEL(IP0SR1_15_12, GP1_03, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR1_15_12, TCLK2, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR1_15_12, HCTS2_N, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR1_15_12, MSIOF2_SS2, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR1_15_12, CTS4_N, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR1_15_12, TSN2_MDIO_A, SEL_I2C1_0), + PINMUX_IPSR_PHYS(IP0SR1_15_12, SDA1, SEL_I2C1_3), + + /* GP1_04 = SCL2 */ + PINMUX_IPSR_MSEL(IP0SR1_19_16, GP1_04, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR1_19_16, TCLK3, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR1_19_16, HRTS2_N, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR1_19_16, MSIOF2_SYNC, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR1_19_16, RTS4_N, SEL_I2C2_0), + PINMUX_IPSR_PHYS(IP0SR1_19_16, SCL2, SEL_I2C2_3), + + /* GP1_05 = SDA2 */ + PINMUX_IPSR_MSEL(IP0SR1_23_20, GP1_05, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR1_23_20, MSIOF2_SCK, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR1_23_20, SCK4, SEL_I2C2_0), + PINMUX_IPSR_PHYS(IP0SR1_23_20, SDA2, SEL_I2C2_3), + + /* GP1_06 = SCL3 */ + PINMUX_IPSR_MSEL(IP0SR1_27_24, GP1_06, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP0SR1_27_24, MSIOF2_RXD, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP0SR1_27_24, RX4, SEL_I2C3_0), + PINMUX_IPSR_PHYS(IP0SR1_27_24, SCL3, SEL_I2C3_3), + + /* GP1_07 = SDA3 */ + PINMUX_IPSR_MSEL(IP0SR1_31_28, GP1_07, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP0SR1_31_28, MSIOF2_TXD, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP0SR1_31_28, TX4, SEL_I2C3_0), + PINMUX_IPSR_PHYS(IP0SR1_31_28, SDA3, SEL_I2C3_3), + + /* GP1_08 = SCL4 */ + PINMUX_IPSR_NOGM(0, GP1_08, SEL_I2C4_0), + PINMUX_IPSR_NOFN(GP1_08, SCL4, SEL_I2C4_3), + + /* GP1_09 = SDA4 */ + PINMUX_IPSR_NOGM(0, GP1_09, SEL_I2C4_0), + PINMUX_IPSR_NOFN(GP1_09, SDA4, SEL_I2C4_3), + + /* GP1_10 = SCL5 */ + PINMUX_IPSR_NOGM(0, GP1_10, SEL_I2C5_0), + PINMUX_IPSR_NOFN(GP1_10, SCL5, SEL_I2C5_3), + + /* GP1_11 = SDA5 */ + PINMUX_IPSR_NOGM(0, GP1_11, SEL_I2C5_0), + PINMUX_IPSR_NOFN(GP1_11, SDA5, SEL_I2C5_3), +}; + +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), +}; + +/* - HSCIF0 ----------------------------------------------------------------- */ +static const unsigned int hscif0_data_pins[] = { + /* HRX0, HTX0 */ + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), +}; +static const unsigned int hscif0_data_mux[] = { + HRX0_MARK, HTX0_MARK, +}; +static const unsigned int hscif0_clk_pins[] = { + /* HSCK0 */ + RCAR_GP_PIN(0, 1), +}; +static const unsigned int hscif0_clk_mux[] = { + HSCK0_MARK, +}; +static const unsigned int hscif0_ctrl_pins[] = { + /* HRTS0#, HCTS0# */ + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), +}; +static const unsigned int hscif0_ctrl_mux[] = { + HRTS0_N_MARK, HCTS0_N_MARK, +}; + +/* - HSCIF1 ----------------------------------------------------------------- */ +static const unsigned int hscif1_data_pins[] = { + /* HRX1, HTX1 */ + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int hscif1_data_mux[] = { + HRX1_MARK, HTX1_MARK, +}; +static const unsigned int hscif1_clk_pins[] = { + /* HSCK1 */ + RCAR_GP_PIN(0, 8), +}; +static const unsigned int hscif1_clk_mux[] = { + HSCK1_MARK, +}; +static const unsigned int hscif1_ctrl_pins[] = { + /* HRTS1#, HCTS1# */ + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), +}; +static const unsigned int hscif1_ctrl_mux[] = { + HRTS1_N_MARK, HCTS1_N_MARK, +}; + +/* - HSCIF2 ----------------------------------------------------------------- */ +static const unsigned int hscif2_data_pins[] = { + /* HRX2, HTX2 */ + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), +}; +static const unsigned int hscif2_data_mux[] = { + HRX2_MARK, HTX2_MARK, +}; +static const unsigned int hscif2_clk_pins[] = { + /* HSCK2 */ + RCAR_GP_PIN(1, 0), +}; +static const unsigned int hscif2_clk_mux[] = { + HSCK2_MARK, +}; +static const unsigned int hscif2_ctrl_pins[] = { + /* HRTS2#, HCTS2# */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), +}; +static const unsigned int hscif2_ctrl_mux[] = { + HRTS2_N_MARK, HCTS2_N_MARK, +}; + +/* - HSCIF3 ----------------------------------------------------------------- */ +static const unsigned int hscif3_data_pins[] = { + /* HRX3, HTX3 */ + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), +}; +static const unsigned int hscif3_data_mux[] = { + HRX3_MARK, HTX3_MARK, +}; +static const unsigned int hscif3_clk_pins[] = { + /* HSCK3 */ + RCAR_GP_PIN(0, 14), +}; +static const unsigned int hscif3_clk_mux[] = { + HSCK3_MARK, +}; +static const unsigned int hscif3_ctrl_pins[] = { + /* HRTS3#, HCTS3# */ + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11), +}; +static const unsigned int hscif3_ctrl_mux[] = { + HRTS3_N_MARK, HCTS3_N_MARK, +}; + +/* - I2C0 ------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SDA0, SCL0 */ + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), +}; +static const unsigned int i2c0_mux[] = { + SDA0_MARK, SCL0_MARK, +}; + +/* - I2C1 ------------------------------------------------------------------- */ +static const unsigned int i2c1_pins[] = { + /* SDA1, SCL1 */ + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), +}; +static const unsigned int i2c1_mux[] = { + SDA1_MARK, SCL1_MARK, +}; + +/* - I2C2 ------------------------------------------------------------------- */ +static const unsigned int i2c2_pins[] = { + /* SDA2, SCL2 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), +}; +static const unsigned int i2c2_mux[] = { + SDA2_MARK, SCL2_MARK, +}; + +/* - I2C3 ------------------------------------------------------------------- */ +static const unsigned int i2c3_pins[] = { + /* SDA3, SCL3 */ + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), +}; +static const unsigned int i2c3_mux[] = { + SDA3_MARK, SCL3_MARK, +}; + +/* - I2C4 ------------------------------------------------------------------- */ +static const unsigned int i2c4_pins[] = { + /* SDA4, SCL4 */ + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), +}; +static const unsigned int i2c4_mux[] = { + SDA4_MARK, SCL4_MARK, +}; + +/* - I2C5 ------------------------------------------------------------------- */ +static const unsigned int i2c5_pins[] = { + /* SDA5, SCL5 */ + RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), +}; +static const unsigned int i2c5_mux[] = { + SDA5_MARK, SCL5_MARK, +}; + + +/* - INTC-EX ---------------------------------------------------------------- */ +static const unsigned int intc_ex_irq0_pins[] = { + /* IRQ0 */ + RCAR_GP_PIN(0, 17), +}; +static const unsigned int intc_ex_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_ex_irq1_pins[] = { + /* IRQ1 */ + RCAR_GP_PIN(0, 18), +}; +static const unsigned int intc_ex_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_ex_irq2_pins[] = { + /* IRQ2 */ + RCAR_GP_PIN(0, 19), +}; +static const unsigned int intc_ex_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_ex_irq3_pins[] = { + /* IRQ3 */ + RCAR_GP_PIN(0, 20), +}; +static const unsigned int intc_ex_irq3_mux[] = { + IRQ3_MARK, +}; +static const unsigned int intc_ex_irq4_pins[] = { + /* IRQ4 */ + RCAR_GP_PIN(0, 11), +}; +static const unsigned int intc_ex_irq4_mux[] = { + IRQ4_MARK, +}; +static const unsigned int intc_ex_irq5_pins[] = { + /* IRQ5 */ + RCAR_GP_PIN(0, 15), +}; +static const unsigned int intc_ex_irq5_mux[] = { + IRQ5_MARK, +}; + +/* - MMC -------------------------------------------------------------------- */ +static const unsigned int mmc_data_pins[] = { + /* MMC_SD_D[0:3], MMC_D[4:7] */ + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 21), +}; +static const unsigned int mmc_data_mux[] = { + MMC_SD_D0_MARK, MMC_SD_D1_MARK, + MMC_SD_D2_MARK, MMC_SD_D3_MARK, + MMC_D4_MARK, MMC_D5_MARK, + MMC_D6_MARK, MMC_D7_MARK, +}; +static const unsigned int mmc_ctrl_pins[] = { + /* MMC_SD_CLK, MMC_SD_CMD */ + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 22), +}; +static const unsigned int mmc_ctrl_mux[] = { + MMC_SD_CLK_MARK, MMC_SD_CMD_MARK, +}; +static const unsigned int mmc_cd_pins[] = { + /* SD_CD */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int mmc_cd_mux[] = { + SD_CD_MARK, +}; +static const unsigned int mmc_wp_pins[] = { + /* SD_WP */ + RCAR_GP_PIN(1, 24), +}; +static const unsigned int mmc_wp_mux[] = { + SD_WP_MARK, +}; +static const unsigned int mmc_ds_pins[] = { + /* MMC_DS */ + RCAR_GP_PIN(1, 20), +}; +static const unsigned int mmc_ds_mux[] = { + MMC_DS_MARK, +}; + +/* - MSIOF0 ----------------------------------------------------------------- */ +static const unsigned int msiof0_clk_pins[] = { + /* MSIOF0_SCK */ + RCAR_GP_PIN(0, 14), +}; +static const unsigned int msiof0_clk_mux[] = { + MSIOF0_SCK_MARK, +}; +static const unsigned int msiof0_sync_pins[] = { + /* MSIOF0_SYNC */ + RCAR_GP_PIN(0, 11), +}; +static const unsigned int msiof0_sync_mux[] = { + MSIOF0_SYNC_MARK, +}; +static const unsigned int msiof0_ss1_pins[] = { + /* MSIOF0_SS1 */ + RCAR_GP_PIN(0, 15), +}; +static const unsigned int msiof0_ss1_mux[] = { + MSIOF0_SS1_MARK, +}; +static const unsigned int msiof0_ss2_pins[] = { + /* MSIOF0_SS2 */ + RCAR_GP_PIN(0, 16), +}; +static const unsigned int msiof0_ss2_mux[] = { + MSIOF0_SS2_MARK, +}; +static const unsigned int msiof0_txd_pins[] = { + /* MSIOF0_TXD */ + RCAR_GP_PIN(0, 13), +}; +static const unsigned int msiof0_txd_mux[] = { + MSIOF0_TXD_MARK, +}; +static const unsigned int msiof0_rxd_pins[] = { + /* MSIOF0_RXD */ + RCAR_GP_PIN(0, 12), +}; +static const unsigned int msiof0_rxd_mux[] = { + MSIOF0_RXD_MARK, +}; + +/* - MSIOF1 ----------------------------------------------------------------- */ +static const unsigned int msiof1_clk_pins[] = { + /* MSIOF1_SCK */ + RCAR_GP_PIN(0, 8), +}; +static const unsigned int msiof1_clk_mux[] = { + MSIOF1_SCK_MARK, +}; +static const unsigned int msiof1_sync_pins[] = { + /* MSIOF1_SYNC */ + RCAR_GP_PIN(0, 10), +}; +static const unsigned int msiof1_sync_mux[] = { + MSIOF1_SYNC_MARK, +}; +static const unsigned int msiof1_ss1_pins[] = { + /* MSIOF1_SS1 */ + RCAR_GP_PIN(0, 17), +}; +static const unsigned int msiof1_ss1_mux[] = { + MSIOF1_SS1_MARK, +}; +static const unsigned int msiof1_ss2_pins[] = { + /* MSIOF1_SS2 */ + RCAR_GP_PIN(0, 18), +}; +static const unsigned int msiof1_ss2_mux[] = { + MSIOF1_SS2_MARK, +}; +static const unsigned int msiof1_txd_pins[] = { + /* MSIOF1_TXD */ + RCAR_GP_PIN(0, 7), +}; +static const unsigned int msiof1_txd_mux[] = { + MSIOF1_TXD_MARK, +}; +static const unsigned int msiof1_rxd_pins[] = { + /* MSIOF1_RXD */ + RCAR_GP_PIN(0, 6), +}; +static const unsigned int msiof1_rxd_mux[] = { + MSIOF1_RXD_MARK, +}; + +/* - MSIOF2 ----------------------------------------------------------------- */ +static const unsigned int msiof2_clk_pins[] = { + /* MSIOF2_SCK */ + RCAR_GP_PIN(1, 5), +}; +static const unsigned int msiof2_clk_mux[] = { + MSIOF2_SCK_MARK, +}; +static const unsigned int msiof2_sync_pins[] = { + /* MSIOF2_SYNC */ + RCAR_GP_PIN(1, 4), +}; +static const unsigned int msiof2_sync_mux[] = { + MSIOF2_SYNC_MARK, +}; +static const unsigned int msiof2_ss1_pins[] = { + /* MSIOF2_SS1 */ + RCAR_GP_PIN(1, 2), +}; +static const unsigned int msiof2_ss1_mux[] = { + MSIOF2_SS1_MARK, +}; +static const unsigned int msiof2_ss2_pins[] = { + /* MSIOF2_SS2 */ + RCAR_GP_PIN(1, 3), +}; +static const unsigned int msiof2_ss2_mux[] = { + MSIOF2_SS2_MARK, +}; +static const unsigned int msiof2_txd_pins[] = { + /* MSIOF2_TXD */ + RCAR_GP_PIN(1, 7), +}; +static const unsigned int msiof2_txd_mux[] = { + MSIOF2_TXD_MARK, +}; +static const unsigned int msiof2_rxd_pins[] = { + /* MSIOF2_RXD */ + RCAR_GP_PIN(1, 6), +}; +static const unsigned int msiof2_rxd_mux[] = { + MSIOF2_RXD_MARK, +}; + +/* - MSIOF3 ----------------------------------------------------------------- */ +static const unsigned int msiof3_clk_pins[] = { + /* MSIOF3_SCK */ + RCAR_GP_PIN(0, 1), +}; +static const unsigned int msiof3_clk_mux[] = { + MSIOF3_SCK_MARK, +}; +static const unsigned int msiof3_sync_pins[] = { + /* MSIOF3_SYNC */ + RCAR_GP_PIN(0, 9), +}; +static const unsigned int msiof3_sync_mux[] = { + MSIOF3_SYNC_MARK, +}; +static const unsigned int msiof3_ss1_pins[] = { + /* MSIOF3_SS1 */ + RCAR_GP_PIN(0, 4), +}; +static const unsigned int msiof3_ss1_mux[] = { + MSIOF3_SS1_MARK, +}; +static const unsigned int msiof3_ss2_pins[] = { + /* MSIOF3_SS2 */ + RCAR_GP_PIN(0, 5), +}; +static const unsigned int msiof3_ss2_mux[] = { + MSIOF3_SS2_MARK, +}; +static const unsigned int msiof3_txd_pins[] = { + /* MSIOF3_TXD */ + RCAR_GP_PIN(0, 3), +}; +static const unsigned int msiof3_txd_mux[] = { + MSIOF3_TXD_MARK, +}; +static const unsigned int msiof3_rxd_pins[] = { + /* MSIOF3_RXD */ + RCAR_GP_PIN(0, 2), +}; +static const unsigned int msiof3_rxd_mux[] = { + MSIOF3_RXD_MARK, +}; + +/* - PCIE ------------------------------------------------------------------- */ +static const unsigned int pcie0_clkreq_n_pins[] = { + /* PCIE0_CLKREQ# */ + RCAR_GP_PIN(2, 15), +}; + +static const unsigned int pcie0_clkreq_n_mux[] = { + PCIE0_CLKREQ_N_MARK, +}; + +static const unsigned int pcie1_clkreq_n_pins[] = { + /* PCIE1_CLKREQ# */ + RCAR_GP_PIN(2, 16), +}; + +static const unsigned int pcie1_clkreq_n_mux[] = { + PCIE1_CLKREQ_N_MARK, +}; + +/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 12), + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 14), +}; +static const unsigned int qspi0_data_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK +}; + +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 3), +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 4), +}; +static const unsigned int qspi1_data_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK +}; + +/* - SCIF0 ------------------------------------------------------------------ */ +static const unsigned int scif0_data_pins[] = { + /* RX0, TX0 */ + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int scif0_data_mux[] = { + RX0_MARK, TX0_MARK, +}; +static const unsigned int scif0_clk_pins[] = { + /* SCK0 */ + RCAR_GP_PIN(0, 8), +}; +static const unsigned int scif0_clk_mux[] = { + SCK0_MARK, +}; +static const unsigned int scif0_ctrl_pins[] = { + /* RTS0#, CTS0# */ + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), +}; +static const unsigned int scif0_ctrl_mux[] = { + RTS0_N_MARK, CTS0_N_MARK, +}; + +/* - SCIF1 ------------------------------------------------------------------ */ +static const unsigned int scif1_data_pins[] = { + /* RX1, TX1 */ + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), +}; +static const unsigned int scif1_data_mux[] = { + RX1_MARK, TX1_MARK, +}; +static const unsigned int scif1_clk_pins[] = { + /* SCK1 */ + RCAR_GP_PIN(0, 14), +}; +static const unsigned int scif1_clk_mux[] = { + SCK1_MARK, +}; +static const unsigned int scif1_ctrl_pins[] = { + /* RTS1#, CTS1# */ + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11), +}; +static const unsigned int scif1_ctrl_mux[] = { + RTS1_N_MARK, CTS1_N_MARK, +}; + +/* - SCIF3 ------------------------------------------------------------------ */ +static const unsigned int scif3_data_pins[] = { + /* RX3, TX3 */ + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), +}; +static const unsigned int scif3_data_mux[] = { + RX3_MARK, TX3_MARK, +}; +static const unsigned int scif3_clk_pins[] = { + /* SCK3 */ + RCAR_GP_PIN(0, 1), +}; +static const unsigned int scif3_clk_mux[] = { + SCK3_MARK, +}; +static const unsigned int scif3_ctrl_pins[] = { + /* RTS3#, CTS3# */ + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), +}; +static const unsigned int scif3_ctrl_mux[] = { + RTS3_N_MARK, CTS3_N_MARK, +}; + +/* - SCIF4 ------------------------------------------------------------------ */ +static const unsigned int scif4_data_pins[] = { + /* RX4, TX4 */ + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +}; +static const unsigned int scif4_data_mux[] = { + RX4_MARK, TX4_MARK, +}; +static const unsigned int scif4_clk_pins[] = { + /* SCK4 */ + RCAR_GP_PIN(1, 5), +}; +static const unsigned int scif4_clk_mux[] = { + SCK4_MARK, +}; +static const unsigned int scif4_ctrl_pins[] = { + /* RTS4#, CTS4# */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), +}; +static const unsigned int scif4_ctrl_mux[] = { + RTS4_N_MARK, CTS4_N_MARK, +}; + +/* - SCIF Clock ------------------------------------------------------------- */ +static const unsigned int scif_clk_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(0, 0), +}; +static const unsigned int scif_clk_mux[] = { + SCIF_CLK_MARK, +}; + +/* - TSN0 ------------------------------------------------ */ +static const unsigned int tsn0_link_a_pins[] = { + /* TSN0_LINK_A */ + RCAR_GP_PIN(0, 11), +}; +static const unsigned int tsn0_link_a_mux[] = { + TSN0_LINK_A_MARK, +}; +static const unsigned int tsn0_magic_a_pins[] = { + /* TSN0_MAGIC_A */ + RCAR_GP_PIN(0, 17), +}; +static const unsigned int tsn0_magic_a_mux[] = { + TSN0_MAGIC_A_MARK, +}; +static const unsigned int tsn0_phy_int_a_pins[] = { + /* TSN0_PHY_INT_A */ + RCAR_GP_PIN(0, 18), +}; +static const unsigned int tsn0_phy_int_a_mux[] = { + TSN0_PHY_INT_A_MARK, +}; +static const unsigned int tsn0_mdio_a_pins[] = { + /* TSN0_MDC_A, TSN0_MDIO_A */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), +}; +static const unsigned int tsn0_mdio_a_mux[] = { + TSN0_MDC_A_MARK, TSN0_MDIO_A_MARK, +}; +static const unsigned int tsn0_link_b_pins[] = { + /* TSN0_LINK_B */ + RCAR_GP_PIN(3, 8), +}; +static const unsigned int tsn0_link_b_mux[] = { + TSN0_LINK_B_MARK, +}; +static const unsigned int tsn0_magic_b_pins[] = { + /* TSN0_MAGIC_B */ + RCAR_GP_PIN(3, 12), +}; +static const unsigned int tsn0_magic_b_mux[] = { + TSN0_MAGIC_B_MARK, +}; +static const unsigned int tsn0_phy_int_b_pins[] = { + /* TSN0_PHY_INT_B */ + RCAR_GP_PIN(3, 10), +}; +static const unsigned int tsn0_phy_int_b_mux[] = { + TSN0_PHY_INT_B_MARK, +}; +static const unsigned int tsn0_mdio_b_pins[] = { + /* TSN0_MDC_B, TSN0_MDIO_B */ + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 2), +}; +static const unsigned int tsn0_mdio_b_mux[] = { + TSN0_MDC_B_MARK, TSN0_MDIO_B_MARK, +}; +static const unsigned int tsn0_avtp_pps_pins[] = { + /* TSN0_AVTP_PPS */ + RCAR_GP_PIN(3, 16), +}; +static const unsigned int tsn0_avtp_pps_mux[] = { + TSN0_AVTP_PPS_MARK, +}; +static const unsigned int tsn0_avtp_capture_a_pins[] = { + /* TSN0_AVTP_CAPTURE_A */ + RCAR_GP_PIN(0, 1), +}; +static const unsigned int tsn0_avtp_capture_a_mux[] = { + TSN0_AVTP_CAPTURE_A_MARK, +}; +static const unsigned int tsn0_avtp_match_a_pins[] = { + /* TSN0_AVTP_MATCH_A */ + RCAR_GP_PIN(0, 2), +}; +static const unsigned int tsn0_avtp_match_a_mux[] = { + TSN0_AVTP_MATCH_A_MARK, +}; +static const unsigned int tsn0_avtp_capture_b_pins[] = { + /* TSN0_AVTP_CAPTURE_B */ + RCAR_GP_PIN(3, 18), +}; +static const unsigned int tsn0_avtp_capture_b_mux[] = { + TSN0_AVTP_CAPTURE_B_MARK, +}; +static const unsigned int tsn0_avtp_match_b_pins[] = { + /* TSN0_AVTP_MATCH_B */ + RCAR_GP_PIN(3, 17), +}; +static const unsigned int tsn0_avtp_match_b_mux[] = { + TSN0_AVTP_MATCH_B_MARK, +}; + +/* - TSN1 ------------------------------------------------ */ +static const unsigned int tsn1_link_a_pins[] = { + /* TSN1_LINK_A */ + RCAR_GP_PIN(0, 15), +}; +static const unsigned int tsn1_link_a_mux[] = { + TSN1_LINK_A_MARK, +}; +static const unsigned int tsn1_phy_int_a_pins[] = { + /* TSN1_PHY_INT_A */ + RCAR_GP_PIN(0, 19), +}; +static const unsigned int tsn1_phy_int_a_mux[] = { + TSN1_PHY_INT_A_MARK, +}; +static const unsigned int tsn1_mdio_a_pins[] = { + /* TSN1_MDC_A, TSN1_MDIO_A */ + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), +}; +static const unsigned int tsn1_mdio_a_mux[] = { + TSN1_MDC_A_MARK, TSN1_MDIO_A_MARK, +}; +static const unsigned int tsn1_link_b_pins[] = { + /* TSN1_LINK_B */ + RCAR_GP_PIN(3, 6), +}; +static const unsigned int tsn1_link_b_mux[] = { + TSN1_LINK_B_MARK, +}; +static const unsigned int tsn1_phy_int_b_pins[] = { + /* TSN1_PHY_INT_B */ + RCAR_GP_PIN(3, 11), +}; +static const unsigned int tsn1_phy_int_b_mux[] = { + TSN1_PHY_INT_B_MARK, +}; +static const unsigned int tsn1_mdio_b_pins[] = { + /* TSN1_MDC_B, TSN1_MDIO_B */ + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0), +}; +static const unsigned int tsn1_mdio_b_mux[] = { + TSN1_MDC_B_MARK, TSN1_MDIO_B_MARK, +}; +static const unsigned int tsn1_avtp_pps_pins[] = { + /* TSN1_AVTP_PPS */ + RCAR_GP_PIN(3, 13), +}; +static const unsigned int tsn1_avtp_pps_mux[] = { + TSN0_AVTP_PPS_MARK, +}; +static const unsigned int tsn1_avtp_capture_a_pins[] = { + /* TSN1_AVTP_CAPTURE_A */ + RCAR_GP_PIN(0, 7), +}; +static const unsigned int tsn1_avtp_capture_a_mux[] = { + TSN1_AVTP_CAPTURE_A_MARK, +}; +static const unsigned int tsn1_avtp_match_a_pins[] = { + /* TSN1_AVTP_MATCH_A */ + RCAR_GP_PIN(0, 6), +}; +static const unsigned int tsn1_avtp_match_a_mux[] = { + TSN1_AVTP_MATCH_A_MARK, +}; +static const unsigned int tsn1_avtp_capture_b_pins[] = { + /* TSN1_AVTP_CAPTURE_B */ + RCAR_GP_PIN(3, 15), +}; +static const unsigned int tsn1_avtp_capture_b_mux[] = { + TSN1_AVTP_CAPTURE_B_MARK, +}; +static const unsigned int tsn1_avtp_match_b_pins[] = { + /* TSN1_AVTP_MATCH_B */ + RCAR_GP_PIN(3, 14), +}; +static const unsigned int tsn1_avtp_match_b_mux[] = { + TSN1_AVTP_MATCH_B_MARK, +}; + +/* - TSN2 ------------------------------------------------ */ +static const unsigned int tsn2_link_a_pins[] = { + /* TSN2_LINK_A */ + RCAR_GP_PIN(0, 16), +}; +static const unsigned int tsn2_link_a_mux[] = { + TSN2_LINK_A_MARK, +}; +static const unsigned int tsn2_phy_int_a_pins[] = { + /* TSN2_PHY_INT_A */ + RCAR_GP_PIN(0, 20), +}; +static const unsigned int tsn2_phy_int_a_mux[] = { + TSN2_PHY_INT_A_MARK, +}; +static const unsigned int tsn2_mdio_a_pins[] = { + /* TSN2_MDC_A, TSN2_MDIO_A */ + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), +}; +static const unsigned int tsn2_mdio_a_mux[] = { + TSN2_MDC_A_MARK, TSN2_MDIO_A_MARK, +}; +static const unsigned int tsn2_link_b_pins[] = { + /* TSN2_LINK_B */ + RCAR_GP_PIN(3, 7), +}; +static const unsigned int tsn2_link_b_mux[] = { + TSN2_LINK_B_MARK, +}; +static const unsigned int tsn2_phy_int_b_pins[] = { + /* TSN2_PHY_INT_B */ + RCAR_GP_PIN(3, 9), +}; +static const unsigned int tsn2_phy_int_b_mux[] = { + TSN2_PHY_INT_B_MARK, +}; +static const unsigned int tsn2_mdio_b_pins[] = { + /* TSN2_MDC_B, TSN2_MDIO_B */ + RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 1), +}; +static const unsigned int tsn2_mdio_b_mux[] = { + TSN2_MDC_B_MARK, TSN2_MDIO_B_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif1_data), + SH_PFC_PIN_GROUP(hscif1_clk), + SH_PFC_PIN_GROUP(hscif1_ctrl), + SH_PFC_PIN_GROUP(hscif2_data), + SH_PFC_PIN_GROUP(hscif2_clk), + SH_PFC_PIN_GROUP(hscif2_ctrl), + SH_PFC_PIN_GROUP(hscif3_data), + SH_PFC_PIN_GROUP(hscif3_clk), + SH_PFC_PIN_GROUP(hscif3_ctrl), + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c2), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c4), + SH_PFC_PIN_GROUP(i2c5), + SH_PFC_PIN_GROUP(intc_ex_irq0), + SH_PFC_PIN_GROUP(intc_ex_irq1), + SH_PFC_PIN_GROUP(intc_ex_irq2), + SH_PFC_PIN_GROUP(intc_ex_irq3), + SH_PFC_PIN_GROUP(intc_ex_irq4), + SH_PFC_PIN_GROUP(intc_ex_irq5), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), + SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(mmc_cd), + SH_PFC_PIN_GROUP(mmc_wp), + SH_PFC_PIN_GROUP(mmc_ds), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_txd), + SH_PFC_PIN_GROUP(msiof0_rxd), + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_ss1), + SH_PFC_PIN_GROUP(msiof1_ss2), + SH_PFC_PIN_GROUP(msiof1_txd), + SH_PFC_PIN_GROUP(msiof1_rxd), + SH_PFC_PIN_GROUP(msiof2_clk), + SH_PFC_PIN_GROUP(msiof2_sync), + SH_PFC_PIN_GROUP(msiof2_ss1), + SH_PFC_PIN_GROUP(msiof2_ss2), + SH_PFC_PIN_GROUP(msiof2_txd), + SH_PFC_PIN_GROUP(msiof2_rxd), + SH_PFC_PIN_GROUP(msiof3_clk), + SH_PFC_PIN_GROUP(msiof3_sync), + SH_PFC_PIN_GROUP(msiof3_ss1), + SH_PFC_PIN_GROUP(msiof3_ss2), + SH_PFC_PIN_GROUP(msiof3_txd), + SH_PFC_PIN_GROUP(msiof3_rxd), + SH_PFC_PIN_GROUP(pcie0_clkreq_n), + SH_PFC_PIN_GROUP(pcie1_clkreq_n), + SH_PFC_PIN_GROUP(qspi0_ctrl), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif1_data), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif3_data), + SH_PFC_PIN_GROUP(scif3_clk), + SH_PFC_PIN_GROUP(scif3_ctrl), + SH_PFC_PIN_GROUP(scif4_data), + SH_PFC_PIN_GROUP(scif4_clk), + SH_PFC_PIN_GROUP(scif4_ctrl), + SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(tsn0_link_a), + SH_PFC_PIN_GROUP(tsn0_magic_a), + SH_PFC_PIN_GROUP(tsn0_phy_int_a), + SH_PFC_PIN_GROUP(tsn0_mdio_a), + SH_PFC_PIN_GROUP(tsn0_link_b), + SH_PFC_PIN_GROUP(tsn0_magic_b), + SH_PFC_PIN_GROUP(tsn0_phy_int_b), + SH_PFC_PIN_GROUP(tsn0_mdio_b), + SH_PFC_PIN_GROUP(tsn0_avtp_pps), + SH_PFC_PIN_GROUP(tsn0_avtp_capture_a), + SH_PFC_PIN_GROUP(tsn0_avtp_match_a), + SH_PFC_PIN_GROUP(tsn0_avtp_capture_b), + SH_PFC_PIN_GROUP(tsn0_avtp_match_b), + SH_PFC_PIN_GROUP(tsn1_link_a), + SH_PFC_PIN_GROUP(tsn1_phy_int_a), + SH_PFC_PIN_GROUP(tsn1_mdio_a), + SH_PFC_PIN_GROUP(tsn1_link_b), + SH_PFC_PIN_GROUP(tsn1_phy_int_b), + SH_PFC_PIN_GROUP(tsn1_mdio_b), + SH_PFC_PIN_GROUP(tsn1_avtp_pps), + SH_PFC_PIN_GROUP(tsn1_avtp_capture_a), + SH_PFC_PIN_GROUP(tsn1_avtp_match_a), + SH_PFC_PIN_GROUP(tsn1_avtp_capture_b), + SH_PFC_PIN_GROUP(tsn1_avtp_match_b), + SH_PFC_PIN_GROUP(tsn2_link_a), + SH_PFC_PIN_GROUP(tsn2_phy_int_a), + SH_PFC_PIN_GROUP(tsn2_mdio_a), + SH_PFC_PIN_GROUP(tsn2_link_b), + SH_PFC_PIN_GROUP(tsn2_phy_int_b), + SH_PFC_PIN_GROUP(tsn2_mdio_b), +}; + +static const char * const hscif0_groups[] = { + "hscif0_data", + "hscif0_clk", + "hscif0_ctrl", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data", + "hscif1_clk", + "hscif1_ctrl", +}; + +static const char * const hscif2_groups[] = { + "hscif2_data", + "hscif2_clk", + "hscif2_ctrl", +}; + +static const char * const hscif3_groups[] = { + "hscif3_data", + "hscif3_clk", + "hscif3_ctrl", +}; + +static const char * const i2c0_groups[] = { + "i2c0", +}; + +static const char * const i2c1_groups[] = { + "i2c1", +}; + +static const char * const i2c2_groups[] = { + "i2c2", +}; + +static const char * const i2c3_groups[] = { + "i2c3", +}; + +static const char * const i2c4_groups[] = { + "i2c4", +}; + +static const char * const i2c5_groups[] = { + "i2c5", +}; + +static const char * const intc_ex_groups[] = { + "intc_ex_irq0", + "intc_ex_irq1", + "intc_ex_irq2", + "intc_ex_irq3", + "intc_ex_irq4", + "intc_ex_irq5", +}; + +static const char * const mmc_groups[] = { + "mmc_data1", + "mmc_data4", + "mmc_data8", + "mmc_ctrl", + "mmc_cd", + "mmc_wp", + "mmc_ds", +}; + +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_txd", + "msiof0_rxd", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk", + "msiof1_sync", + "msiof1_ss1", + "msiof1_ss2", + "msiof1_txd", + "msiof1_rxd", +}; + +static const char * const msiof2_groups[] = { + "msiof2_clk", + "msiof2_sync", + "msiof2_ss1", + "msiof2_ss2", + "msiof2_txd", + "msiof2_rxd", +}; + +static const char * const msiof3_groups[] = { + "msiof3_clk", + "msiof3_sync", + "msiof3_ss1", + "msiof3_ss2", + "msiof3_txd", + "msiof3_rxd", +}; + +static const char * const pcie_groups[] = { + "pcie0_clkreq_n", + "pcie1_clkreq_n", +}; + +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + +static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk", + "scif0_ctrl", +}; + +static const char * const scif1_groups[] = { + "scif1_data", + "scif1_clk", + "scif1_ctrl", +}; + +static const char * const scif3_groups[] = { + "scif3_data", + "scif3_clk", + "scif3_ctrl", +}; + +static const char * const scif4_groups[] = { + "scif4_data", + "scif4_clk", + "scif4_ctrl", +}; + +static const char * const scif_clk_groups[] = { + "scif_clk", +}; + +static const char * const tsn0_groups[] = { + "tsn0_link_a", + "tsn0_magic_a", + "tsn0_phy_int_a", + "tsn0_mdio_a", + "tsn0_link_b", + "tsn0_magic_b", + "tsn0_phy_int_b", + "tsn0_mdio_b", + "tsn0_avtp_pps", + "tsn0_avtp_capture_a", + "tsn0_avtp_match_a", + "tsn0_avtp_capture_b", + "tsn0_avtp_match_b", +}; + +static const char * const tsn1_groups[] = { + "tsn1_link_a", + "tsn1_phy_int_a", + "tsn1_mdio_a", + "tsn1_link_b", + "tsn1_phy_int_b", + "tsn1_mdio_b", + "tsn1_avtp_pps", + "tsn1_avtp_capture_a", + "tsn1_avtp_match_a", + "tsn1_avtp_capture_b", + "tsn1_avtp_match_b", +}; + +static const char * const tsn2_groups[] = { + "tsn2_link_a", + "tsn2_phy_int_a", + "tsn2_mdio_a", + "tsn2_link_b", + "tsn2_phy_int_b", + "tsn2_mdio_b", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(hscif3), + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c4), + SH_PFC_FUNCTION(i2c5), + SH_PFC_FUNCTION(intc_ex), + SH_PFC_FUNCTION(mmc), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(pcie), + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(tsn0), + SH_PFC_FUNCTION(tsn1), + SH_PFC_FUNCTION(tsn2), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { +#define F_(x, y) FN_##y +#define FM(x) FN_##x + { PINMUX_CFG_REG("GPSR0", 0xe6050040, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_0_20_FN, GPSR0_20, + GP_0_19_FN, GPSR0_19, + GP_0_18_FN, GPSR0_18, + GP_0_17_FN, GPSR0_17, + GP_0_16_FN, GPSR0_16, + GP_0_15_FN, GPSR0_15, + GP_0_14_FN, GPSR0_14, + GP_0_13_FN, GPSR0_13, + GP_0_12_FN, GPSR0_12, + GP_0_11_FN, GPSR0_11, + GP_0_10_FN, GPSR0_10, + GP_0_9_FN, GPSR0_9, + GP_0_8_FN, GPSR0_8, + GP_0_7_FN, GPSR0_7, + GP_0_6_FN, GPSR0_6, + GP_0_5_FN, GPSR0_5, + GP_0_4_FN, GPSR0_4, + GP_0_3_FN, GPSR0_3, + GP_0_2_FN, GPSR0_2, + GP_0_1_FN, GPSR0_1, + GP_0_0_FN, GPSR0_0, )) + }, + { PINMUX_CFG_REG("GPSR1", 0xe6050840, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_24_FN, GPSR1_24, + GP_1_23_FN, GPSR1_23, + GP_1_22_FN, GPSR1_22, + GP_1_21_FN, GPSR1_21, + GP_1_20_FN, GPSR1_20, + GP_1_19_FN, GPSR1_19, + GP_1_18_FN, GPSR1_18, + GP_1_17_FN, GPSR1_17, + GP_1_16_FN, GPSR1_16, + GP_1_15_FN, GPSR1_15, + GP_1_14_FN, GPSR1_14, + GP_1_13_FN, GPSR1_13, + GP_1_12_FN, GPSR1_12, + GP_1_11_FN, GPSR1_11, + GP_1_10_FN, GPSR1_10, + GP_1_9_FN, GPSR1_9, + GP_1_8_FN, GPSR1_8, + GP_1_7_FN, GPSR1_7, + GP_1_6_FN, GPSR1_6, + GP_1_5_FN, GPSR1_5, + GP_1_4_FN, GPSR1_4, + GP_1_3_FN, GPSR1_3, + GP_1_2_FN, GPSR1_2, + GP_1_1_FN, GPSR1_1, + GP_1_0_FN, GPSR1_0, )) + }, + { PINMUX_CFG_REG("GPSR2", 0xe6051040, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_2_16_FN, GPSR2_16, + GP_2_15_FN, GPSR2_15, + GP_2_14_FN, GPSR2_14, + GP_2_13_FN, GPSR2_13, + GP_2_12_FN, GPSR2_12, + GP_2_11_FN, GPSR2_11, + GP_2_10_FN, GPSR2_10, + GP_2_9_FN, GPSR2_9, + GP_2_8_FN, GPSR2_8, + GP_2_7_FN, GPSR2_7, + GP_2_6_FN, GPSR2_6, + GP_2_5_FN, GPSR2_5, + GP_2_4_FN, GPSR2_4, + GP_2_3_FN, GPSR2_3, + GP_2_2_FN, GPSR2_2, + GP_2_1_FN, GPSR2_1, + GP_2_0_FN, GPSR2_0, )) + }, + { PINMUX_CFG_REG("GPSR3", 0xe6051840, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_3_18_FN, GPSR3_18, + GP_3_17_FN, GPSR3_17, + GP_3_16_FN, GPSR3_16, + GP_3_15_FN, GPSR3_15, + GP_3_14_FN, GPSR3_14, + GP_3_13_FN, GPSR3_13, + GP_3_12_FN, GPSR3_12, + GP_3_11_FN, GPSR3_11, + GP_3_10_FN, GPSR3_10, + GP_3_9_FN, GPSR3_9, + GP_3_8_FN, GPSR3_8, + GP_3_7_FN, GPSR3_7, + GP_3_6_FN, GPSR3_6, + GP_3_5_FN, GPSR3_5, + GP_3_4_FN, GPSR3_4, + GP_3_3_FN, GPSR3_3, + GP_3_2_FN, GPSR3_2, + GP_3_1_FN, GPSR3_1, + GP_3_0_FN, GPSR3_0, )) + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG("IP0SR0", 0xe6050060, 32, 4, GROUP( + IP0SR0_31_28 + IP0SR0_27_24 + IP0SR0_23_20 + IP0SR0_19_16 + IP0SR0_15_12 + IP0SR0_11_8 + IP0SR0_7_4 + IP0SR0_3_0)) + }, + { PINMUX_CFG_REG("IP1SR0", 0xe6050064, 32, 4, GROUP( + IP1SR0_31_28 + IP1SR0_27_24 + IP1SR0_23_20 + IP1SR0_19_16 + IP1SR0_15_12 + IP1SR0_11_8 + IP1SR0_7_4 + IP1SR0_3_0)) + }, + { PINMUX_CFG_REG("IP2SR0", 0xe6050068, 32, 4, GROUP( + IP2SR0_31_28 + IP2SR0_27_24 + IP2SR0_23_20 + IP2SR0_19_16 + IP2SR0_15_12 + IP2SR0_11_8 + IP2SR0_7_4 + IP2SR0_3_0)) + }, + { PINMUX_CFG_REG("IP0SR1", 0xe6050860, 32, 4, GROUP( + IP0SR1_31_28 + IP0SR1_27_24 + IP0SR1_23_20 + IP0SR1_19_16 + IP0SR1_15_12 + IP0SR1_11_8 + IP0SR1_7_4 + IP0SR1_3_0)) + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6050900, 32, + GROUP(4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2), + GROUP( + /* RESERVED 31, 30, 29, 28 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 27, 26, 25, 24 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 23, 22, 21, 20 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 19, 18, 17, 16 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 15, 14, 13, 12 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + MOD_SEL1_11_10 + MOD_SEL1_9_8 + MOD_SEL1_7_6 + MOD_SEL1_5_4 + MOD_SEL1_3_2 + MOD_SEL1_1_0)) + }, + { /* sentinel */ }, +}; + +static const struct pinmux_drive_reg pinmux_drive_regs[] = { + { PINMUX_DRIVE_REG("DRV0CTRL0", 0xe6050080) { + { RCAR_GP_PIN(0, 7), 28, 3 }, /* TX0 */ + { RCAR_GP_PIN(0, 6), 24, 3 }, /* RX0 */ + { RCAR_GP_PIN(0, 5), 20, 3 }, /* HRTS0_N */ + { RCAR_GP_PIN(0, 4), 16, 3 }, /* HCTS0_N */ + { RCAR_GP_PIN(0, 3), 12, 3 }, /* HTX0 */ + { RCAR_GP_PIN(0, 2), 8, 3 }, /* HRX0 */ + { RCAR_GP_PIN(0, 1), 4, 3 }, /* HSCK0 */ + { RCAR_GP_PIN(0, 0), 0, 3 }, /* SCIF_CLK */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL0", 0xe6050084) { + { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF0_SS1 */ + { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF0_SCK */ + { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF0_TXD */ + { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF0_RXD */ + { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF0_SYNC */ + { RCAR_GP_PIN(0, 10), 8, 3 }, /* CTS0_N */ + { RCAR_GP_PIN(0, 9), 4, 3 }, /* RTS0_N */ + { RCAR_GP_PIN(0, 8), 0, 3 }, /* SCK0 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL0", 0xe6050088) { + { RCAR_GP_PIN(0, 20), 16, 3 }, /* IRQ3 */ + { RCAR_GP_PIN(0, 19), 12, 3 }, /* IRQ2 */ + { RCAR_GP_PIN(0, 18), 8, 3 }, /* IRQ1 */ + { RCAR_GP_PIN(0, 17), 4, 3 }, /* IRQ0 */ + { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF0_SS2 */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL1", 0xe6050880) { + { RCAR_GP_PIN(1, 7), 28, 3 }, /* GP1_07 */ + { RCAR_GP_PIN(1, 6), 24, 3 }, /* GP1_06 */ + { RCAR_GP_PIN(1, 5), 20, 3 }, /* GP1_05 */ + { RCAR_GP_PIN(1, 4), 16, 3 }, /* GP1_04 */ + { RCAR_GP_PIN(1, 3), 12, 3 }, /* GP1_03 */ + { RCAR_GP_PIN(1, 2), 8, 3 }, /* GP1_02 */ + { RCAR_GP_PIN(1, 1), 4, 3 }, /* GP1_01 */ + { RCAR_GP_PIN(1, 0), 0, 3 }, /* GP1_00 */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL1", 0xe6050884) { + { RCAR_GP_PIN(1, 15), 28, 3 }, /* MMC_SD_D2 */ + { RCAR_GP_PIN(1, 14), 24, 3 }, /* MMC_SD_D1 */ + { RCAR_GP_PIN(1, 13), 20, 3 }, /* MMC_SD_D0 */ + { RCAR_GP_PIN(1, 12), 16, 3 }, /* MMC_SD_CLK */ + { RCAR_GP_PIN(1, 11), 12, 3 }, /* GP1_11 */ + { RCAR_GP_PIN(1, 10), 8, 3 }, /* GP1_10 */ + { RCAR_GP_PIN(1, 9), 4, 3 }, /* GP1_09 */ + { RCAR_GP_PIN(1, 8), 0, 3 }, /* GP1_08 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL1", 0xe6050888) { + { RCAR_GP_PIN(1, 23), 28, 3 }, /* SD_CD */ + { RCAR_GP_PIN(1, 22), 24, 3 }, /* MMC_SD_CMD */ + { RCAR_GP_PIN(1, 21), 20, 3 }, /* MMC_D7 */ + { RCAR_GP_PIN(1, 20), 16, 3 }, /* MMC_DS */ + { RCAR_GP_PIN(1, 19), 12, 3 }, /* MMC_D6 */ + { RCAR_GP_PIN(1, 18), 8, 3 }, /* MMC_D4 */ + { RCAR_GP_PIN(1, 17), 4, 3 }, /* MMC_D5 */ + { RCAR_GP_PIN(1, 16), 0, 3 }, /* MMC_SD_D3 */ + } }, + { PINMUX_DRIVE_REG("DRV3CTRL1", 0xe605088c) { + { RCAR_GP_PIN(1, 24), 0, 3 }, /* SD_WP */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL2", 0xe6051080) { + { RCAR_GP_PIN(2, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */ + { RCAR_GP_PIN(2, 6), 24, 2 }, /* QSPI1_IO2 */ + { RCAR_GP_PIN(2, 5), 20, 2 }, /* QSPI1_MISO_IO1 */ + { RCAR_GP_PIN(2, 4), 16, 2 }, /* QSPI1_IO3 */ + { RCAR_GP_PIN(2, 3), 12, 2 }, /* QSPI1_SSL */ + { RCAR_GP_PIN(2, 2), 8, 2 }, /* RPC_RESET_N */ + { RCAR_GP_PIN(2, 1), 4, 2 }, /* RPC_WP_N */ + { RCAR_GP_PIN(2, 0), 0, 2 }, /* RPC_INT_N */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL2", 0xe6051084) { + { RCAR_GP_PIN(2, 15), 28, 3 }, /* PCIE0_CLKREQ_N */ + { RCAR_GP_PIN(2, 14), 24, 2 }, /* QSPI0_IO3 */ + { RCAR_GP_PIN(2, 13), 20, 2 }, /* QSPI0_SSL */ + { RCAR_GP_PIN(2, 12), 16, 2 }, /* QSPI0_MISO_IO1 */ + { RCAR_GP_PIN(2, 11), 12, 2 }, /* QSPI0_IO2 */ + { RCAR_GP_PIN(2, 10), 8, 2 }, /* QSPI0_SPCLK */ + { RCAR_GP_PIN(2, 9), 4, 2 }, /* QSPI0_MOSI_IO0 */ + { RCAR_GP_PIN(2, 8), 0, 2 }, /* QSPI1_SPCLK */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL2", 0xe6051088) { + { RCAR_GP_PIN(2, 16), 0, 3 }, /* PCIE1_CLKREQ_N */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL3", 0xe6051880) { + { RCAR_GP_PIN(3, 7), 28, 3 }, /* TSN2_LINK_B */ + { RCAR_GP_PIN(3, 6), 24, 3 }, /* TSN1_LINK_B */ + { RCAR_GP_PIN(3, 5), 20, 3 }, /* TSN1_MDC_B */ + { RCAR_GP_PIN(3, 4), 16, 3 }, /* TSN0_MDC_B */ + { RCAR_GP_PIN(3, 3), 12, 3 }, /* TSN2_MDC_B */ + { RCAR_GP_PIN(3, 2), 8, 3 }, /* TSN0_MDIO_B */ + { RCAR_GP_PIN(3, 1), 4, 3 }, /* TSN2_MDIO_B */ + { RCAR_GP_PIN(3, 0), 0, 3 }, /* TSN1_MDIO_B */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL3", 0xe6051884) { + { RCAR_GP_PIN(3, 15), 28, 3 }, /* TSN1_AVTP_CAPTURE_B */ + { RCAR_GP_PIN(3, 14), 24, 3 }, /* TSN1_AVTP_MATCH_B */ + { RCAR_GP_PIN(3, 13), 20, 3 }, /* TSN1_AVTP_PPS */ + { RCAR_GP_PIN(3, 12), 16, 3 }, /* TSN0_MAGIC_B */ + { RCAR_GP_PIN(3, 11), 12, 3 }, /* TSN1_PHY_INT_B */ + { RCAR_GP_PIN(3, 10), 8, 3 }, /* TSN0_PHY_INT_B */ + { RCAR_GP_PIN(3, 9), 4, 3 }, /* TSN2_PHY_INT_B */ + { RCAR_GP_PIN(3, 8), 0, 3 }, /* TSN0_LINK_B */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6051888) { + { RCAR_GP_PIN(3, 18), 8, 3 }, /* TSN0_AVTP_CAPTURE_B */ + { RCAR_GP_PIN(3, 17), 4, 3 }, /* TSN0_AVTP_MATCH_B */ + { RCAR_GP_PIN(3, 16), 0, 3 }, /* TSN0_AVTP_PPS */ + } }, + { /* sentinel */ }, +}; + +enum ioctrl_regs { + POC0, + POC1, + POC2, + POC3, + TD0SEL1, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [POC0] = { 0xe60500a0, }, + [POC1] = { 0xe60508a0, }, + [POC2] = { 0xe60510a0, }, + [POC3] = { 0xe60518a0, }, + [TD0SEL1] = { 0xe6050920, }, + { /* sentinel */ }, +}; + +static int r8a779f0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) +{ + int bit = pin & 0x1f; + + *pocctrl = pinmux_ioctrl_regs[POC0].reg; + if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 20)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC1].reg; + if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 24)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC3].reg; + if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 18)) + return bit; + + return -EINVAL; +} + +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUEN0", 0xe60500c0, "PUD0", 0xe60500e0) { + [ 0] = RCAR_GP_PIN(0, 0), /* SCIF_CLK */ + [ 1] = RCAR_GP_PIN(0, 1), /* HSCK0 */ + [ 2] = RCAR_GP_PIN(0, 2), /* HRX0 */ + [ 3] = RCAR_GP_PIN(0, 3), /* HTX0 */ + [ 4] = RCAR_GP_PIN(0, 4), /* HCTS0_N */ + [ 5] = RCAR_GP_PIN(0, 5), /* HRTS0_N */ + [ 6] = RCAR_GP_PIN(0, 6), /* RX0 */ + [ 7] = RCAR_GP_PIN(0, 7), /* TX0 */ + [ 8] = RCAR_GP_PIN(0, 8), /* SCK0 */ + [ 9] = RCAR_GP_PIN(0, 9), /* RTS0_N */ + [10] = RCAR_GP_PIN(0, 10), /* CTS0_N */ + [11] = RCAR_GP_PIN(0, 11), /* MSIOF0_SYNC */ + [12] = RCAR_GP_PIN(0, 12), /* MSIOF0_RXD */ + [13] = RCAR_GP_PIN(0, 13), /* MSIOF0_TXD */ + [14] = RCAR_GP_PIN(0, 14), /* MSIOF0_SCK */ + [15] = RCAR_GP_PIN(0, 15), /* MSIOF0_SS1 */ + [16] = RCAR_GP_PIN(0, 16), /* MSIOF0_SS2 */ + [17] = RCAR_GP_PIN(0, 17), /* IRQ0 */ + [18] = RCAR_GP_PIN(0, 18), /* IRQ1 */ + [19] = RCAR_GP_PIN(0, 19), /* IRQ2 */ + [20] = RCAR_GP_PIN(0, 20), /* IRQ3 */ + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN1", 0xe60508c0, "PUD1", 0xe60508e0) { + [ 0] = RCAR_GP_PIN(1, 0), /* GP1_00 */ + [ 1] = RCAR_GP_PIN(1, 1), /* GP1_01 */ + [ 2] = RCAR_GP_PIN(1, 2), /* GP1_02 */ + [ 3] = RCAR_GP_PIN(1, 3), /* GP1_03 */ + [ 4] = RCAR_GP_PIN(1, 4), /* GP1_04 */ + [ 5] = RCAR_GP_PIN(1, 5), /* GP1_05 */ + [ 6] = RCAR_GP_PIN(1, 6), /* GP1_06 */ + [ 7] = RCAR_GP_PIN(1, 7), /* GP1_07 */ + [ 8] = RCAR_GP_PIN(1, 8), /* GP1_08 */ + [ 9] = RCAR_GP_PIN(1, 9), /* GP1_09 */ + [10] = RCAR_GP_PIN(1, 10), /* GP1_10 */ + [11] = RCAR_GP_PIN(1, 11), /* GP1_11 */ + [12] = RCAR_GP_PIN(1, 12), /* MMC_SD_CLK */ + [13] = RCAR_GP_PIN(1, 13), /* MMC_SD_D0 */ + [14] = RCAR_GP_PIN(1, 14), /* MMC_SD_D1 */ + [15] = RCAR_GP_PIN(1, 15), /* MMC_SD_D2 */ + [16] = RCAR_GP_PIN(1, 16), /* MMC_SD_D3 */ + [17] = RCAR_GP_PIN(1, 17), /* MMC_D5 */ + [18] = RCAR_GP_PIN(1, 18), /* MMC_D4 */ + [19] = RCAR_GP_PIN(1, 19), /* MMC_D6 */ + [20] = RCAR_GP_PIN(1, 20), /* MMC_DS */ + [21] = RCAR_GP_PIN(1, 21), /* MMC_D7 */ + [22] = RCAR_GP_PIN(1, 22), /* MMC_SD_CMD */ + [23] = RCAR_GP_PIN(1, 23), /* SD_CD */ + [24] = RCAR_GP_PIN(1, 24), /* SD_WP */ + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN2", 0xe60510c0, "PUD2", 0xe60510e0) { + [ 0] = RCAR_GP_PIN(2, 0), /* RPC_INT_N */ + [ 1] = RCAR_GP_PIN(2, 1), /* RPC_WP_N */ + [ 2] = RCAR_GP_PIN(2, 2), /* RPC_RESET_N */ + [ 3] = RCAR_GP_PIN(2, 3), /* QSPI1_SSL */ + [ 4] = RCAR_GP_PIN(2, 4), /* QSPI1_IO3 */ + [ 5] = RCAR_GP_PIN(2, 5), /* QSPI1_MISO_IO1 */ + [ 6] = RCAR_GP_PIN(2, 6), /* QSPI1_IO2 */ + [ 7] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI_IO0 */ + [ 8] = RCAR_GP_PIN(2, 8), /* QSPI1_SPCLK */ + [ 9] = RCAR_GP_PIN(2, 9), /* QSPI0_MOSI_IO0 */ + [10] = RCAR_GP_PIN(2, 10), /* QSPI0_SPCLK */ + [11] = RCAR_GP_PIN(2, 11), /* QSPI0_IO2 */ + [12] = RCAR_GP_PIN(2, 12), /* QSPI0_MISO_IO1 */ + [13] = RCAR_GP_PIN(2, 13), /* QSPI0_SSL */ + [14] = RCAR_GP_PIN(2, 14), /* QSPI0_IO3 */ + [15] = RCAR_GP_PIN(2, 15), /* PCIE0_CLKREQ_N */ + [16] = RCAR_GP_PIN(2, 16), /* PCIE1_CLKREQ_N */ + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN3", 0xe60518c0, "PUD3", 0xe60518e0) { + [ 0] = RCAR_GP_PIN(3, 0), /* TSN1_MDIO_B */ + [ 1] = RCAR_GP_PIN(3, 1), /* TSN2_MDIO_B */ + [ 2] = RCAR_GP_PIN(3, 2), /* TSN0_MDIO_B */ + [ 3] = RCAR_GP_PIN(3, 3), /* TSN2_MDC_B */ + [ 4] = RCAR_GP_PIN(3, 4), /* TSN0_MDC_B */ + [ 5] = RCAR_GP_PIN(3, 5), /* TSN1_MDC_B */ + [ 6] = RCAR_GP_PIN(3, 6), /* TSN1_LINK_B */ + [ 7] = RCAR_GP_PIN(3, 7), /* TSN2_LINK_B */ + [ 8] = RCAR_GP_PIN(3, 8), /* TSN0_LINK_B */ + [ 9] = RCAR_GP_PIN(3, 9), /* TSN2_PHY_INT_B */ + [10] = RCAR_GP_PIN(3, 10), /* TSN0_PHY_INT_B */ + [11] = RCAR_GP_PIN(3, 11), /* TSN1_PHY_INT_B */ + [12] = RCAR_GP_PIN(3, 12), /* TSN0_MAGIC_B */ + [13] = RCAR_GP_PIN(3, 13), /* TSN1_AVTP_PPS */ + [14] = RCAR_GP_PIN(3, 14), /* TSN1_AVTP_MATCH_B */ + [15] = RCAR_GP_PIN(3, 15), /* TSN1_AVTP_CAPTURE_B */ + [16] = RCAR_GP_PIN(3, 16), /* TSN0_AVTP_PPS */ + [17] = RCAR_GP_PIN(3, 17), /* TSN0_AVTP_MATCH_B */ + [18] = RCAR_GP_PIN(3, 18), /* TSN0_AVTP_CAPTURE_B */ + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { /* sentinel */ }, +}; + +static const struct sh_pfc_soc_operations r8a779f0_pfc_ops = { + .pin_to_pocctrl = r8a779f0_pin_to_pocctrl, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, +}; + +const struct sh_pfc_soc_info r8a779f0_pinmux_info = { + .name = "r8a779f0_pfc", + .ops = &r8a779f0_pfc_ops, + .unlock_reg = 0x1ff, /* PMMRn mask */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + .drive_regs = pinmux_drive_regs, + .bias_regs = pinmux_bias_regs, + .ioctrl_regs = pinmux_ioctrl_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/renesas/pfc-sh7203.c b/drivers/pinctrl/renesas/pfc-sh7203.c index 811a6f2cb1fc..3986802b448a 100644 --- a/drivers/pinctrl/renesas/pfc-sh7203.c +++ b/drivers/pinctrl/renesas/pfc-sh7203.c @@ -6,7 +6,6 @@ */ #include <linux/kernel.h> -#include <linux/gpio.h> #include <cpu/sh7203.h> #include "sh_pfc.h" diff --git a/drivers/pinctrl/renesas/pfc-sh7264.c b/drivers/pinctrl/renesas/pfc-sh7264.c index 908837ea487b..7476b982101d 100644 --- a/drivers/pinctrl/renesas/pfc-sh7264.c +++ b/drivers/pinctrl/renesas/pfc-sh7264.c @@ -6,7 +6,6 @@ */ #include <linux/kernel.h> -#include <linux/gpio.h> #include <cpu/sh7264.h> #include "sh_pfc.h" diff --git a/drivers/pinctrl/renesas/pfc-sh7269.c b/drivers/pinctrl/renesas/pfc-sh7269.c index e2916aaa8304..733a2c114ca2 100644 --- a/drivers/pinctrl/renesas/pfc-sh7269.c +++ b/drivers/pinctrl/renesas/pfc-sh7269.c @@ -7,7 +7,6 @@ */ #include <linux/kernel.h> -#include <linux/gpio.h> #include <cpu/sh7269.h> #include "sh_pfc.h" diff --git a/drivers/pinctrl/renesas/pfc-sh73a0.c b/drivers/pinctrl/renesas/pfc-sh73a0.c index ed6db809e80d..5d8a0179fd60 100644 --- a/drivers/pinctrl/renesas/pfc-sh73a0.c +++ b/drivers/pinctrl/renesas/pfc-sh73a0.c @@ -1777,35 +1777,11 @@ static const unsigned int irda_1_mux[] = { PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK, }; /* - KEYSC ------------------------------------------------------------------ */ -static const unsigned int keysc_in5_pins[] = { - /* KEYIN[0:4] */ - 66, 67, 68, 69, 70, -}; -static const unsigned int keysc_in5_mux[] = { - KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, - KEYIN4_MARK, -}; -static const unsigned int keysc_in6_pins[] = { - /* KEYIN[0:5] */ - 66, 67, 68, 69, 70, 71, -}; -static const unsigned int keysc_in6_mux[] = { - KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, - KEYIN4_MARK, KEYIN5_MARK, -}; -static const unsigned int keysc_in7_pins[] = { - /* KEYIN[0:6] */ - 66, 67, 68, 69, 70, 71, 72, -}; -static const unsigned int keysc_in7_mux[] = { - KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, - KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, -}; -static const unsigned int keysc_in8_pins[] = { +static const unsigned int keysc_in_pins[] = { /* KEYIN[0:7] */ 66, 67, 68, 69, 70, 71, 72, 73, }; -static const unsigned int keysc_in8_mux[] = { +static const unsigned int keysc_in_mux[] = { KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK, }; @@ -1936,65 +1912,13 @@ static const unsigned int keysc_out11_1_mux[] = { PORT143_KEYOUT11_MARK, }; /* - LCD -------------------------------------------------------------------- */ -static const unsigned int lcd_data8_pins[] = { - /* D[0:7] */ - 192, 193, 194, 195, 196, 197, 198, 199, -}; -static const unsigned int lcd_data8_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, -}; -static const unsigned int lcd_data9_pins[] = { - /* D[0:8] */ - 192, 193, 194, 195, 196, 197, 198, 199, - 200, -}; -static const unsigned int lcd_data9_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, - LCDD8_MARK, -}; -static const unsigned int lcd_data12_pins[] = { - /* D[0:11] */ - 192, 193, 194, 195, 196, 197, 198, 199, - 200, 201, 202, 203, -}; -static const unsigned int lcd_data12_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, - LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, -}; -static const unsigned int lcd_data16_pins[] = { - /* D[0:15] */ - 192, 193, 194, 195, 196, 197, 198, 199, - 200, 201, 202, 203, 204, 205, 206, 207, -}; -static const unsigned int lcd_data16_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, - LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, - LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, -}; -static const unsigned int lcd_data18_pins[] = { - /* D[0:17] */ - 192, 193, 194, 195, 196, 197, 198, 199, - 200, 201, 202, 203, 204, 205, 206, 207, - 208, 209, -}; -static const unsigned int lcd_data18_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, - LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, - LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, - LCDD16_MARK, LCDD17_MARK, -}; -static const unsigned int lcd_data24_pins[] = { +static const unsigned int lcd_data_pins[] = { /* D[0:23] */ 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215 }; -static const unsigned int lcd_data24_mux[] = { +static const unsigned int lcd_data_mux[] = { LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, @@ -2031,65 +1955,13 @@ static const unsigned int lcd_sys_mux[] = { LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK, }; /* - LCD2 ------------------------------------------------------------------- */ -static const unsigned int lcd2_data8_pins[] = { - /* D[0:7] */ - 128, 129, 142, 143, 144, 145, 138, 139, -}; -static const unsigned int lcd2_data8_mux[] = { - LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, - LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, -}; -static const unsigned int lcd2_data9_pins[] = { - /* D[0:8] */ - 128, 129, 142, 143, 144, 145, 138, 139, - 140, -}; -static const unsigned int lcd2_data9_mux[] = { - LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, - LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, - LCD2D8_MARK, -}; -static const unsigned int lcd2_data12_pins[] = { - /* D[0:11] */ - 128, 129, 142, 143, 144, 145, 138, 139, - 140, 141, 130, 131, -}; -static const unsigned int lcd2_data12_mux[] = { - LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, - LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, - LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, -}; -static const unsigned int lcd2_data16_pins[] = { - /* D[0:15] */ - 128, 129, 142, 143, 144, 145, 138, 139, - 140, 141, 130, 131, 132, 133, 134, 135, -}; -static const unsigned int lcd2_data16_mux[] = { - LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, - LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, - LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, - LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK, -}; -static const unsigned int lcd2_data18_pins[] = { - /* D[0:17] */ - 128, 129, 142, 143, 144, 145, 138, 139, - 140, 141, 130, 131, 132, 133, 134, 135, - 136, 137, -}; -static const unsigned int lcd2_data18_mux[] = { - LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, - LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, - LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, - LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK, - LCD2D16_MARK, LCD2D17_MARK, -}; -static const unsigned int lcd2_data24_pins[] = { +static const unsigned int lcd2_data_pins[] = { /* D[0:23] */ 128, 129, 142, 143, 144, 145, 138, 139, 140, 141, 130, 131, 132, 133, 134, 135, 136, 137, 146, 147, 234, 235, 238, 239 }; -static const unsigned int lcd2_data24_mux[] = { +static const unsigned int lcd2_data_mux[] = { LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, @@ -2130,25 +2002,11 @@ static const unsigned int lcd2_sys_1_mux[] = { LCD2RD__MARK, PORT217_LCD2RS_MARK, }; /* - MMCIF ------------------------------------------------------------------ */ -static const unsigned int mmc0_data1_0_pins[] = { - /* D[0] */ - 271, -}; -static const unsigned int mmc0_data1_0_mux[] = { - MMCD0_0_MARK, -}; -static const unsigned int mmc0_data4_0_pins[] = { - /* D[0:3] */ - 271, 272, 273, 274, -}; -static const unsigned int mmc0_data4_0_mux[] = { - MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, -}; -static const unsigned int mmc0_data8_0_pins[] = { +static const unsigned int mmc0_data_0_pins[] = { /* D[0:7] */ 271, 272, 273, 274, 275, 276, 277, 278, }; -static const unsigned int mmc0_data8_0_mux[] = { +static const unsigned int mmc0_data_0_mux[] = { MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK, }; @@ -2160,25 +2018,11 @@ static const unsigned int mmc0_ctrl_0_mux[] = { MMCCMD0_MARK, MMCCLK0_MARK, }; -static const unsigned int mmc0_data1_1_pins[] = { - /* D[0] */ - 305, -}; -static const unsigned int mmc0_data1_1_mux[] = { - MMCD1_0_MARK, -}; -static const unsigned int mmc0_data4_1_pins[] = { - /* D[0:3] */ - 305, 304, 303, 302, -}; -static const unsigned int mmc0_data4_1_mux[] = { - MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, -}; -static const unsigned int mmc0_data8_1_pins[] = { +static const unsigned int mmc0_data_1_pins[] = { /* D[0:7] */ 305, 304, 303, 302, 301, 300, 299, 298, }; -static const unsigned int mmc0_data8_1_mux[] = { +static const unsigned int mmc0_data_1_mux[] = { MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK, }; @@ -2851,18 +2695,11 @@ static const unsigned int scifb_ctrl_1_mux[] = { PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK, }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - 252, -}; -static const unsigned int sdhi0_data1_mux[] = { - SDHID0_0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ 252, 253, 254, 255, }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -2887,18 +2724,11 @@ static const unsigned int sdhi0_wp_mux[] = { SDHIWP0_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - 259, -}; -static const unsigned int sdhi1_data1_mux[] = { - SDHID1_0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ 259, 260, 261, 262, }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK, }; static const unsigned int sdhi1_ctrl_pins[] = { @@ -2909,18 +2739,11 @@ static const unsigned int sdhi1_ctrl_mux[] = { SDHICMD1_MARK, SDHICLK1_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - 265, -}; -static const unsigned int sdhi2_data1_mux[] = { - SDHID2_0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:3] */ 265, 266, 267, 268, }; -static const unsigned int sdhi2_data4_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { @@ -3138,10 +2961,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c3_2), SH_PFC_PIN_GROUP(irda_0), SH_PFC_PIN_GROUP(irda_1), - SH_PFC_PIN_GROUP(keysc_in5), - SH_PFC_PIN_GROUP(keysc_in6), - SH_PFC_PIN_GROUP(keysc_in7), - SH_PFC_PIN_GROUP(keysc_in8), + BUS_DATA_PIN_GROUP(keysc_in, 5), + BUS_DATA_PIN_GROUP(keysc_in, 6), + BUS_DATA_PIN_GROUP(keysc_in, 7), + BUS_DATA_PIN_GROUP(keysc_in, 8), SH_PFC_PIN_GROUP(keysc_out04), SH_PFC_PIN_GROUP(keysc_out5), SH_PFC_PIN_GROUP(keysc_out6_0), @@ -3160,33 +2983,33 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(keysc_out10_1), SH_PFC_PIN_GROUP(keysc_out11_0), SH_PFC_PIN_GROUP(keysc_out11_1), - SH_PFC_PIN_GROUP(lcd_data8), - SH_PFC_PIN_GROUP(lcd_data9), - SH_PFC_PIN_GROUP(lcd_data12), - SH_PFC_PIN_GROUP(lcd_data16), - SH_PFC_PIN_GROUP(lcd_data18), - SH_PFC_PIN_GROUP(lcd_data24), + BUS_DATA_PIN_GROUP(lcd_data, 8), + BUS_DATA_PIN_GROUP(lcd_data, 9), + BUS_DATA_PIN_GROUP(lcd_data, 12), + BUS_DATA_PIN_GROUP(lcd_data, 16), + BUS_DATA_PIN_GROUP(lcd_data, 18), + BUS_DATA_PIN_GROUP(lcd_data, 24), SH_PFC_PIN_GROUP(lcd_display), SH_PFC_PIN_GROUP(lcd_lclk), SH_PFC_PIN_GROUP(lcd_sync), SH_PFC_PIN_GROUP(lcd_sys), - SH_PFC_PIN_GROUP(lcd2_data8), - SH_PFC_PIN_GROUP(lcd2_data9), - SH_PFC_PIN_GROUP(lcd2_data12), - SH_PFC_PIN_GROUP(lcd2_data16), - SH_PFC_PIN_GROUP(lcd2_data18), - SH_PFC_PIN_GROUP(lcd2_data24), + BUS_DATA_PIN_GROUP(lcd2_data, 8), + BUS_DATA_PIN_GROUP(lcd2_data, 9), + BUS_DATA_PIN_GROUP(lcd2_data, 12), + BUS_DATA_PIN_GROUP(lcd2_data, 16), + BUS_DATA_PIN_GROUP(lcd2_data, 18), + BUS_DATA_PIN_GROUP(lcd2_data, 24), SH_PFC_PIN_GROUP(lcd2_sync_0), SH_PFC_PIN_GROUP(lcd2_sync_1), SH_PFC_PIN_GROUP(lcd2_sys_0), SH_PFC_PIN_GROUP(lcd2_sys_1), - SH_PFC_PIN_GROUP(mmc0_data1_0), - SH_PFC_PIN_GROUP(mmc0_data4_0), - SH_PFC_PIN_GROUP(mmc0_data8_0), + BUS_DATA_PIN_GROUP(mmc0_data, 1, _0), + BUS_DATA_PIN_GROUP(mmc0_data, 4, _0), + BUS_DATA_PIN_GROUP(mmc0_data, 8, _0), SH_PFC_PIN_GROUP(mmc0_ctrl_0), - SH_PFC_PIN_GROUP(mmc0_data1_1), - SH_PFC_PIN_GROUP(mmc0_data4_1), - SH_PFC_PIN_GROUP(mmc0_data8_1), + BUS_DATA_PIN_GROUP(mmc0_data, 1, _1), + BUS_DATA_PIN_GROUP(mmc0_data, 4, _1), + BUS_DATA_PIN_GROUP(mmc0_data, 8, _1), SH_PFC_PIN_GROUP(mmc0_ctrl_1), SH_PFC_PIN_GROUP(msiof0_rsck), SH_PFC_PIN_GROUP(msiof0_tsck), @@ -3280,16 +3103,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scifb_data_1), SH_PFC_PIN_GROUP(scifb_clk_1), SH_PFC_PIN_GROUP(scifb_ctrl_1), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(tpu0_to0), SH_PFC_PIN_GROUP(tpu0_to1), @@ -4314,9 +4137,9 @@ static const unsigned int sh73a0_portcr_offsets[] = { 0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000, }; -static void __iomem *sh73a0_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin) +static int sh73a0_pin_to_portcr(unsigned int pin) { - return pfc->windows->virt + sh73a0_portcr_offsets[pin >> 5] + pin; + return sh73a0_portcr_offsets[pin >> 5] + pin; } /* ----------------------------------------------------------------------------- diff --git a/drivers/pinctrl/renesas/pfc-sh7720.c b/drivers/pinctrl/renesas/pfc-sh7720.c index 37bcae6b3208..7071ef52449d 100644 --- a/drivers/pinctrl/renesas/pfc-sh7720.c +++ b/drivers/pinctrl/renesas/pfc-sh7720.c @@ -6,7 +6,6 @@ */ #include <linux/kernel.h> -#include <linux/gpio.h> #include <cpu/sh7720.h> #include "sh_pfc.h" diff --git a/drivers/pinctrl/renesas/pfc-sh7722.c b/drivers/pinctrl/renesas/pfc-sh7722.c index 95295be4e703..13d9967dce59 100644 --- a/drivers/pinctrl/renesas/pfc-sh7722.c +++ b/drivers/pinctrl/renesas/pfc-sh7722.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include <linux/init.h> #include <linux/kernel.h> -#include <linux/gpio.h> #include <cpu/sh7722.h> #include "sh_pfc.h" diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index ccee9c9e2e22..cb805502fb0f 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1090,12 +1090,12 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) } if (of_args.args[0] != 0 || of_args.args[1] != 0 || - of_args.args[2] != ARRAY_SIZE(rzg2l_gpio_names)) { + of_args.args[2] != pctrl->data->n_port_pins) { dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); return -EINVAL; } - chip->names = rzg2l_gpio_names; + chip->names = pctrl->data->port_pins; chip->request = rzg2l_gpio_request; chip->free = rzg2l_gpio_free; chip->get_direction = rzg2l_gpio_get_direction; diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index 96b9de974246..4c37aebc75b8 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -397,7 +397,7 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pfc->lock, flags); - if (!pfc->gpio) { + if (!pfc->gpio && !cfg->mux_mark) { /* If GPIOs are handled externally the pin mux type needs to be * set to GPIO here. */ @@ -639,7 +639,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) return -ENOTSUPP; - bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl); + bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl); if (WARN(bit < 0, "invalid pin %#x", _pin)) return bit; @@ -711,7 +711,7 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) return -ENOTSUPP; - bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl); + bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl); if (WARN(bit < 0, "invalid pin %#x", _pin)) return bit; @@ -835,16 +835,16 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc) } const struct pinmux_bias_reg * -rcar_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, +rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin, unsigned int *bit) { unsigned int i, j; - for (i = 0; pfc->info->bias_regs[i].puen || pfc->info->bias_regs[i].pud; i++) { - for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) { - if (pfc->info->bias_regs[i].pins[j] == pin) { + for (i = 0; info->bias_regs[i].puen || info->bias_regs[i].pud; i++) { + for (j = 0; j < ARRAY_SIZE(info->bias_regs[i].pins); j++) { + if (info->bias_regs[i].pins[j] == pin) { *bit = j; - return &pfc->info->bias_regs[i]; + return &info->bias_regs[i]; } } } @@ -859,7 +859,7 @@ unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) const struct pinmux_bias_reg *reg; unsigned int bit; - reg = rcar_pin_to_bias_reg(pfc, pin, &bit); + reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); if (!reg) return PIN_CONFIG_BIAS_DISABLE; @@ -885,7 +885,7 @@ void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, u32 enable, updown; unsigned int bit; - reg = rcar_pin_to_bias_reg(pfc, pin, &bit); + reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); if (!reg) return; @@ -919,7 +919,8 @@ void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) { - void __iomem *reg = pfc->info->ops->pin_to_portcr(pfc, pin); + void __iomem *reg = pfc->windows->virt + + pfc->info->ops->pin_to_portcr(pin); u32 value = ioread8(reg) & PORTnCR_PULMD_MASK; switch (value) { @@ -936,7 +937,8 @@ unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, unsigned int bias) { - void __iomem *reg = pfc->info->ops->pin_to_portcr(pfc, pin); + void __iomem *reg = pfc->windows->virt + + pfc->info->ops->pin_to_portcr(pin); u32 value = ioread8(reg) & ~PORTnCR_PULMD_MASK; switch (bias) { diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 2479b4fb9cf9..6b5836ea47de 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -49,15 +49,34 @@ struct sh_pfc_pin { u16 enum_id; }; -#define SH_PFC_PIN_GROUP_ALIAS(alias, n) \ - { \ - .name = #alias, \ - .pins = n##_pins, \ - .mux = n##_mux, \ - .nr_pins = ARRAY_SIZE(n##_pins) + \ - BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \ - } -#define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n) +#define SH_PFC_PIN_GROUP_ALIAS(alias, _name) { \ + .name = #alias, \ + .pins = _name##_pins, \ + .mux = _name##_mux, \ + .nr_pins = ARRAY_SIZE(_name##_pins) + \ + BUILD_BUG_ON_ZERO(sizeof(_name##_pins) != sizeof(_name##_mux)), \ +} +#define SH_PFC_PIN_GROUP(name) SH_PFC_PIN_GROUP_ALIAS(name, name) + +/* + * Define a pin group referring to a subset of an array of pins. + */ +#define SH_PFC_PIN_GROUP_SUBSET(_name, data, first, n) { \ + .name = #_name, \ + .pins = data##_pins + first, \ + .mux = data##_mux + first, \ + .nr_pins = n + \ + BUILD_BUG_ON_ZERO(first + n > ARRAY_SIZE(data##_pins)) + \ + BUILD_BUG_ON_ZERO(first + n > ARRAY_SIZE(data##_mux)), \ +} + +/* + * Define a pin group for the data pins of a resizable bus. + * An optional 'suffix' argument is accepted, to be used when the same group + * can appear on a different set of pins. + */ +#define BUS_DATA_PIN_GROUP(base, n, ...) \ + SH_PFC_PIN_GROUP_SUBSET(base##n##__VA_ARGS__, base##__VA_ARGS__, 0, n) struct sh_pfc_pin_group { const char *name; @@ -66,49 +85,11 @@ struct sh_pfc_pin_group { unsigned int nr_pins; }; -/* - * Using union vin_data{,12,16} saves memory occupied by the VIN data pins. - * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups - * in this case. It accepts an optional 'version' argument used when the - * same group can appear on a different set of pins. - */ -#define VIN_DATA_PIN_GROUP(n, s, ...) \ - { \ - .name = #n#s#__VA_ARGS__, \ - .pins = n##__VA_ARGS__##_pins.data##s, \ - .mux = n##__VA_ARGS__##_mux.data##s, \ - .nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \ - } - -union vin_data12 { - unsigned int data12[12]; - unsigned int data10[10]; - unsigned int data8[8]; -}; - -union vin_data16 { - unsigned int data16[16]; - unsigned int data12[12]; - unsigned int data10[10]; - unsigned int data8[8]; -}; - -union vin_data { - unsigned int data24[24]; - unsigned int data20[20]; - unsigned int data16[16]; - unsigned int data12[12]; - unsigned int data10[10]; - unsigned int data8[8]; - unsigned int data4[4]; -}; - -#define SH_PFC_FUNCTION(n) \ - { \ - .name = #n, \ - .groups = n##_groups, \ - .nr_groups = ARRAY_SIZE(n##_groups), \ - } +#define SH_PFC_FUNCTION(n) { \ + .name = #n, \ + .groups = n##_groups, \ + .nr_groups = ARRAY_SIZE(n##_groups), \ +} struct sh_pfc_function { const char *name; @@ -231,8 +212,9 @@ struct pinmux_irq { * Describe the mapping from GPIOs to a single IRQ * - ids...: List of GPIOs that are mapped to the same IRQ */ -#define PINMUX_IRQ(ids...) \ - { .gpios = (const short []) { ids, -1 } } +#define PINMUX_IRQ(ids...) { \ + .gpios = (const short []) { ids, -1 } \ +} struct pinmux_range { u16 begin; @@ -272,8 +254,8 @@ struct sh_pfc_soc_operations { unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, unsigned int bias); - int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl); - void __iomem * (*pin_to_portcr)(struct sh_pfc *pfc, unsigned int pin); + int (*pin_to_pocctrl)(unsigned int pin, u32 *pocctrl); + int (*pin_to_portcr)(unsigned int pin); }; struct sh_pfc_soc_info { @@ -342,6 +324,7 @@ extern const struct sh_pfc_soc_info r8a77980_pinmux_info; extern const struct sh_pfc_soc_info r8a77990_pinmux_info; extern const struct sh_pfc_soc_info r8a77995_pinmux_info; extern const struct sh_pfc_soc_info r8a779a0_pinmux_info; +extern const struct sh_pfc_soc_info r8a779f0_pinmux_info; extern const struct sh_pfc_soc_info sh7203_pinmux_info; extern const struct sh_pfc_soc_info sh7264_pinmux_info; extern const struct sh_pfc_soc_info sh7269_pinmux_info; @@ -535,9 +518,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0) -#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_19(bank, fn, sfx, cfg) \ PORT_GP_CFG_18(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 18, fn, sfx, cfg) +#define PORT_GP_19(bank, fn, sfx) PORT_GP_CFG_19(bank, fn, sfx, 0) + +#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \ + PORT_GP_CFG_19(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 19, fn, sfx, cfg) #define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0) @@ -624,13 +611,12 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; #define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str) /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ -#define _GP_GPIO(bank, _pin, _name, sfx, cfg) \ - { \ - .pin = (bank * 32) + _pin, \ - .name = __stringify(_name), \ - .enum_id = _name##_DATA, \ - .configs = cfg, \ - } +#define _GP_GPIO(bank, _pin, _name, sfx, cfg) { \ + .pin = (bank * 32) + _pin, \ + .name = __stringify(_name), \ + .enum_id = _name##_DATA, \ + .configs = cfg, \ +} #define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused) /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ @@ -688,13 +674,12 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; } /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */ -#define SH_PFC_PIN_CFG(_pin, cfgs) \ - { \ - .pin = _pin, \ - .name = __stringify(PORT##_pin), \ - .enum_id = PORT##_pin##_DATA, \ - .configs = cfgs, \ - } +#define SH_PFC_PIN_CFG(_pin, cfgs) { \ + .pin = _pin, \ + .name = __stringify(PORT##_pin), \ + .enum_id = PORT##_pin##_DATA, \ + .configs = cfgs, \ +} /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, * PORT_name_OUT, PORT_name_IN marks @@ -743,35 +728,32 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; #define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL) /* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */ -#define _NOGP_PINMUX(_pin, _name, cfg) \ - { \ - .pin = PIN_##_pin, \ - .name = "PIN_" _name, \ - .configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \ - } +#define _NOGP_PINMUX(_pin, _name, cfg) { \ + .pin = PIN_##_pin, \ + .name = "PIN_" _name, \ + .configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \ +} #define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX) /* * PORTnCR helper macro for SH-Mobile/R-Mobile */ -#define PORTCR(nr, reg) \ - { \ - PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \ - GROUP(2, 2, 1, 3), \ - GROUP( \ - /* PULMD[1:0], handled by .set_bias() */ \ - 0, 0, 0, 0, \ - /* IE and OE */ \ - 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \ - /* SEC, not supported */ \ - 0, 0, \ - /* PTMD[2:0] */ \ - PORT##nr##_FN0, PORT##nr##_FN1, \ - PORT##nr##_FN2, PORT##nr##_FN3, \ - PORT##nr##_FN4, PORT##nr##_FN5, \ - PORT##nr##_FN6, PORT##nr##_FN7 \ - )) \ - } +#define PORTCR(nr, reg) { \ + PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, GROUP(2, 2, 1, 3), \ + GROUP( \ + /* PULMD[1:0], handled by .set_bias() */ \ + 0, 0, 0, 0, \ + /* IE and OE */ \ + 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \ + /* SEC, not supported */ \ + 0, 0, \ + /* PTMD[2:0] */ \ + PORT##nr##_FN0, PORT##nr##_FN1, \ + PORT##nr##_FN2, PORT##nr##_FN3, \ + PORT##nr##_FN4, PORT##nr##_FN5, \ + PORT##nr##_FN6, PORT##nr##_FN7 \ + )) \ +} /* * GPIO number helper macro for R-Car @@ -782,7 +764,7 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; * Bias helpers */ const struct pinmux_bias_reg * -rcar_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, +rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin, unsigned int *bit); unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin); void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index 4102ce955bd7..d291819c2f77 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -725,3 +725,74 @@ const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = { .ctrl = exynosautov9_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynosautov9_pin_ctrl), }; + +/* + * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three + * gpio/pin-mux/pinconfig controllers. + */ + +/* pin banks of FSD pin-controller 0 (FSYS) */ +static const struct samsung_pin_bank_data fsd_pin_banks0[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(7, 0x00, "gpf0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gpf1", 0x04), + EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gpf6", 0x08), + EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpf4", 0x0c), + EXYNOS850_PIN_BANK_EINTG(6, 0x80, "gpf5", 0x10), +}; + +/* pin banks of FSD pin-controller 1 (PERIC) */ +static const struct samsung_pin_bank_data fsd_pin_banks1[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpc8", 0x00), + EXYNOS850_PIN_BANK_EINTG(7, 0x020, "gpf2", 0x04), + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpf3", 0x08), + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpd0", 0x0c), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpb0", 0x10), + EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpb1", 0x14), + EXYNOS850_PIN_BANK_EINTG(8, 0x0c0, "gpb4", 0x18), + EXYNOS850_PIN_BANK_EINTG(4, 0x0e0, "gpb5", 0x1c), + EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb6", 0x20), + EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb7", 0x24), + EXYNOS850_PIN_BANK_EINTG(5, 0x140, "gpd1", 0x28), + EXYNOS850_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), + EXYNOS850_PIN_BANK_EINTG(7, 0x180, "gpd3", 0x30), + EXYNOS850_PIN_BANK_EINTG(8, 0x1a0, "gpg0", 0x34), + EXYNOS850_PIN_BANK_EINTG(8, 0x1c0, "gpg1", 0x38), + EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpg2", 0x3c), + EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), + EXYNOS850_PIN_BANK_EINTG(8, 0x220, "gpg4", 0x44), + EXYNOS850_PIN_BANK_EINTG(8, 0x240, "gpg5", 0x48), + EXYNOS850_PIN_BANK_EINTG(8, 0x260, "gpg6", 0x4c), + EXYNOS850_PIN_BANK_EINTG(8, 0x280, "gpg7", 0x50), +}; + +/* pin banks of FSD pin-controller 2 (PMU) */ +static const struct samsung_pin_bank_data fsd_pin_banks2[] __initconst = { + EXYNOS850_PIN_BANK_EINTN(3, 0x00, "gpq0"), +}; + +const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 FSYS0 data */ + .pin_banks = fsd_pin_banks0, + .nr_banks = ARRAY_SIZE(fsd_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 PERIC data */ + .pin_banks = fsd_pin_banks1, + .nr_banks = ARRAY_SIZE(fsd_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 PMU data */ + .pin_banks = fsd_pin_banks2, + .nr_banks = ARRAY_SIZE(fsd_pin_banks2), + }, +}; + +const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { + .ctrl = fsd_pin_ctrl, + .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index a158d587814e..c1c4ffbae6e2 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -344,7 +344,8 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); - pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq); + pr_info("wake %s for irq %u (%s-%lu)\n", on ? "enabled" : "disabled", + irqd->irq, bank->name, irqd->hwirq); if (!on) *our_chip->eint_wake_mask_value |= bit; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 568b6e65dfed..f610beab23a0 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1320,6 +1320,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos850_of_data }, { .compatible = "samsung,exynosautov9-pinctrl", .data = &exynosautov9_of_data }, + { .compatible = "tesla,fsd-pinctrl", + .data = &fsd_of_data }, #endif #ifdef CONFIG_PINCTRL_S3C64XX { .compatible = "samsung,s3c64xx-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 1f8d30ba05af..5b32d3f30fcd 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -342,6 +342,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data; extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; +extern const struct samsung_pinctrl_of_match_data fsd_of_data; extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; extern const struct samsung_pinctrl_of_match_data s3c2416_of_data; diff --git a/drivers/pinctrl/sunplus/Kconfig b/drivers/pinctrl/sunplus/Kconfig new file mode 100644 index 000000000000..4b5c47c193d9 --- /dev/null +++ b/drivers/pinctrl/sunplus/Kconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Sunplus Pin control driver configuration +# + +config PINCTRL_SPPCTL + tristate "Sunplus SP7021 PinMux and GPIO driver" + depends on SOC_SP7021 + depends on OF && HAS_IOMEM + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + select PINCONF + select PINMUX + select GPIOLIB + select OF_GPIO + help + Say Y here to support Sunplus SP7021 pinmux controller. + This driver requires the pinctrl framework. + GPIO is provided by the same driver. + To compile this driver as a module, choose M here. + The module will be called sppinctrl. diff --git a/drivers/pinctrl/sunplus/Makefile b/drivers/pinctrl/sunplus/Makefile new file mode 100644 index 000000000000..a26952c5286a --- /dev/null +++ b/drivers/pinctrl/sunplus/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the Sunplus Pin control drivers. +# +obj-$(CONFIG_PINCTRL_SPPCTL) += sppinctrl.o +sppinctrl-objs := sppctl.o sppctl_sp7021.o diff --git a/drivers/pinctrl/sunplus/sppctl.c b/drivers/pinctrl/sunplus/sppctl.c new file mode 100644 index 000000000000..3ba47040ac42 --- /dev/null +++ b/drivers/pinctrl/sunplus/sppctl.c @@ -0,0 +1,1118 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SP7021 Pin Controller Driver. + * Copyright (C) Sunplus Tech / Tibbo Tech. + */ + +#include <linux/bitfield.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/gpio/driver.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/overflow.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/slab.h> + +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinmux.h> + +#include <dt-bindings/pinctrl/sppctl-sp7021.h> + +#include "../core.h" +#include "../pinctrl-utils.h" + +#include "sppctl.h" + +struct sppctl_gpio_chip { + void __iomem *gpioxt_base; /* MASTER, OE, OUT, IN, I_INV, O_INV, OD */ + void __iomem *first_base; /* GPIO_FIRST */ + + struct gpio_chip chip; + spinlock_t lock; /* lock for accessing OE register */ +}; + +static inline u32 sppctl_first_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off); +} + +static inline void sppctl_first_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) +{ + writel(val, spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off); +} + +static inline u32 sppctl_gpio_master_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off); +} + +static inline void sppctl_gpio_master_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, + u32 off) +{ + writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off); +} + +static inline u32 sppctl_gpio_oe_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off); +} + +static inline void sppctl_gpio_oe_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) +{ + writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off); +} + +static inline void sppctl_gpio_out_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) +{ + writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OUT + off); +} + +static inline u32 sppctl_gpio_in_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IN + off); +} + +static inline u32 sppctl_gpio_iinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off); +} + +static inline void sppctl_gpio_iinv_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, + u32 off) +{ + writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off); +} + +static inline u32 sppctl_gpio_oinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off); +} + +static inline void sppctl_gpio_oinv_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, + u32 off) +{ + writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off); +} + +static inline u32 sppctl_gpio_od_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off); +} + +static inline void sppctl_gpio_od_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) +{ + writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off); +} + +static inline u32 sppctl_get_reg_and_bit_offset(unsigned int offset, u32 *reg_off) +{ + u32 bit_off; + + /* Each register has 32 bits. */ + *reg_off = (offset / 32) * 4; + bit_off = offset % 32; + + return bit_off; +} + +static inline u32 sppctl_get_moon_reg_and_bit_offset(unsigned int offset, u32 *reg_off) +{ + u32 bit_off; + + /* + * Each MOON register has 32 bits. Upper 16-bit word are mask-fields. + * The lower 16-bit word are the control-fields. The corresponding + * bits in mask-field should be set then you can write something to + * control-field. + */ + *reg_off = (offset / 16) * 4; + bit_off = offset % 16; + + return bit_off; +} + +static inline u32 sppctl_prep_moon_reg_and_offset(unsigned int offset, u32 *reg_off, int val) +{ + u32 bit_off; + + bit_off = sppctl_get_moon_reg_and_bit_offset(offset, reg_off); + if (val) + return SPPCTL_SET_MOON_REG_BIT(bit_off); + else + return SPPCTL_CLR_MOON_REG_BIT(bit_off); +} + +/** + * sppctl_func_set() - Set pin of fully-pinmux function. + * + * Mask-fields and control-fields of fully-pinmux function of SP7021 are + * arranged as shown below: + * + * func# | register | mask-field | control-field + * -------+----------+--------------+--------------- + * 0 | base[0] | (22 : 16) | ( 6 : 0) + * 1 | base[0] | (30 : 24) | (14 : 8) + * 2 | base[1] | (22 : 16) | ( 6 : 0) + * 3 | baeg[1] | (30 : 24) | (14 : 8) + * : | : | : | : + * + * where mask-fields are used to protect control-fields from write-in + * accidentally. Set the corresponding bits in the mask-field before + * you write a value into a control-field. + * + * Control-fields are used to set where the function pin is going to + * be routed to. + * + * Note that mask-fields and control-fields of even number of 'func' + * are located at bits (22:16) and (6:0), while odd number of 'func's + * are located at bits (30:24) and (14:8). + */ +static void sppctl_func_set(struct sppctl_pdata *pctl, u8 func, u8 val) +{ + u32 reg, offset; + + /* + * Note that upper 16-bit word are mask-fields and lower 16-bit + * word are the control-fields. Set corresponding bits in mask- + * field before write to a control-field. + */ + reg = SPPCTL_FULLY_PINMUX_MASK_MASK | val; + + /* + * MUXF_L2SW_CLK_OUT is the first fully-pinmux pin + * and its register offset is 0. + */ + func -= MUXF_L2SW_CLK_OUT; + + /* + * Check if 'func' is an odd number or not. Mask and control- + * fields of odd number 'func' is located at upper portion of + * a register. Extra shift is needed. + */ + if (func & BIT(0)) + reg <<= SPPCTL_FULLY_PINMUX_UPPER_SHIFT; + + /* Convert func# to register offset w.r.t. base register. */ + offset = func * 2; + offset &= GENMASK(31, 2); + + writel(reg, pctl->moon2_base + offset); +} + +/** + * sppctl_gmx_set() - Set pin of group-pinmux. + * + * Mask-fields and control-fields of group-pinmux function of SP7021 are + * arranged as shown below: + * + * register | mask-fields | control-fields + * ----------+--------------+---------------- + * base[0] | (31 : 16) | (15 : 0) + * base[1] | (31 : 24) | (15 : 0) + * base[2] | (31 : 24) | (15 : 0) + * : | : | : + * + * where mask-fields are used to protect control-fields from write-in + * accidentally. Set the corresponding bits in the mask-field before + * you write a value into a control-field. + * + * Control-fields are used to set where the function pin is going to + * be routed to. A control-field consists of one or more bits. + */ +static void sppctl_gmx_set(struct sppctl_pdata *pctl, u8 reg_off, u8 bit_off, u8 bit_sz, + u8 val) +{ + u32 mask, reg; + + /* + * Note that upper 16-bit word are mask-fields and lower 16-bit + * word are the control-fields. Set corresponding bits in mask- + * field before write to a control-field. + */ + mask = GENMASK(bit_sz - 1, 0) << SPPCTL_MOON_REG_MASK_SHIFT; + reg = (mask | val) << bit_off; + + writel(reg, pctl->moon1_base + reg_off * 4); +} + +/** + * sppctl_first_get() - get bit of FIRST register. + * + * There are 4 FIRST registers. Each has 32 control-bits. + * Totally, there are 4 * 32 = 128 control-bits. + * Control-bits are arranged as shown below: + * + * registers | control-bits + * -----------+-------------- + * first[0] | (31 : 0) + * first[1] | (63 : 32) + * first[2] | (95 : 64) + * first[3] | (127 : 96) + * + * Each control-bit sets type of a GPIO pin. + * 0: a fully-pinmux pin + * 1: a GPIO or IOP pin + */ +static int sppctl_first_get(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + + bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off); + reg = sppctl_first_readl(spp_gchip, reg_off); + + return (reg & BIT(bit_off)) ? 1 : 0; +} + +/** + * sppctl_master_get() - get bit of MASTER register. + * + * There are 8 MASTER registers. Each has 16 mask-bits and 16 control-bits. + * Upper 16-bit of MASTER registers are mask-bits while lower 16-bit are + * control-bits. Totally, there are 128 mask-bits and 128 control-bits. + * They are arranged as shown below: + * + * register | mask-bits | control-bits + * -----------+-------------+-------------- + * master[0] | (15 : 0) | (15 : 0) + * master[1] | (31 : 16) | (31 : 16) + * master[2] | (47 : 32) | (47 : 32) + * : | : | : + * master[7] | (127 : 112) | (127 : 112) + * + * where mask-bits are used to protect control-bits from write-in + * accidentally. Set the corresponding mask-bit before you write + * a value into a control-bit. + * + * Each control-bit sets type of a GPIO pin when FIRST bit is 1. + * 0: a IOP pin + * 1: a GPIO pin + */ +static int sppctl_master_get(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + + bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); + reg = sppctl_gpio_master_readl(spp_gchip, reg_off); + return (reg & BIT(bit_off)) ? 1 : 0; +} + +static void sppctl_first_master_set(struct gpio_chip *chip, unsigned int offset, + enum mux_first_reg first, enum mux_master_reg master) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + enum mux_first_reg val; + + /* FIRST register */ + if (first != mux_f_keep) { + bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off); + reg = sppctl_first_readl(spp_gchip, reg_off); + val = (reg & BIT(bit_off)) ? mux_f_gpio : mux_f_mux; + + if (first != val) + switch (first) { + case mux_f_gpio: + reg |= BIT(bit_off); + sppctl_first_writel(spp_gchip, reg, reg_off); + break; + + case mux_f_mux: + reg &= ~BIT(bit_off); + sppctl_first_writel(spp_gchip, reg, reg_off); + break; + + case mux_f_keep: + break; + } + } + + /* MASTER register */ + if (master != mux_m_keep) { + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, (master == mux_m_gpio)); + sppctl_gpio_master_writel(spp_gchip, reg, reg_off); + } +} + +static void sppctl_gpio_input_inv_set(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, reg; + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); + sppctl_gpio_iinv_writel(spp_gchip, reg, reg_off); +} + +static void sppctl_gpio_output_inv_set(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, reg; + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); + sppctl_gpio_oinv_writel(spp_gchip, reg, reg_off); +} + +static int sppctl_gpio_output_od_get(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + + bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); + reg = sppctl_gpio_od_readl(spp_gchip, reg_off); + + return (reg & BIT(bit_off)) ? 1 : 0; +} + +static void sppctl_gpio_output_od_set(struct gpio_chip *chip, unsigned int offset, + unsigned int val) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, reg; + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val); + sppctl_gpio_od_writel(spp_gchip, reg, reg_off); +} + +static int sppctl_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + + bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); + reg = sppctl_gpio_oe_readl(spp_gchip, reg_off); + + return (reg & BIT(bit_off)) ? 0 : 1; +} + +static int sppctl_gpio_inv_get(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + unsigned long flags; + + bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); + + spin_lock_irqsave(&spp_gchip->lock, flags); + + if (sppctl_gpio_get_direction(chip, offset)) + reg = sppctl_gpio_iinv_readl(spp_gchip, reg_off); + else + reg = sppctl_gpio_oinv_readl(spp_gchip, reg_off); + + spin_unlock_irqrestore(&spp_gchip->lock, flags); + + return (reg & BIT(bit_off)) ? 1 : 0; +} + +static int sppctl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + unsigned long flags; + u32 reg_off, reg; + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 0); + + spin_lock_irqsave(&spp_gchip->lock, flags); + + sppctl_gpio_oe_writel(spp_gchip, reg, reg_off); + + spin_unlock_irqrestore(&spp_gchip->lock, flags); + return 0; +} + +static int sppctl_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int val) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + unsigned long flags; + u32 reg_off, reg; + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); + + spin_lock_irqsave(&spp_gchip->lock, flags); + + sppctl_gpio_oe_writel(spp_gchip, reg, reg_off); + + if (val < 0) { + spin_unlock_irqrestore(&spp_gchip->lock, flags); + return 0; + } + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val); + sppctl_gpio_out_writel(spp_gchip, reg, reg_off); + + spin_unlock_irqrestore(&spp_gchip->lock, flags); + return 0; +} + +static int sppctl_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + + bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off); + reg = sppctl_gpio_in_readl(spp_gchip, reg_off); + + return (reg & BIT(bit_off)) ? 1 : 0; +} + +static void sppctl_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, reg; + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val); + sppctl_gpio_out_writel(spp_gchip, reg, reg_off); +} + +static int sppctl_gpio_set_config(struct gpio_chip *chip, unsigned int offset, + unsigned long config) +{ + enum pin_config_param param = pinconf_to_config_param(config); + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, reg; + + switch (param) { + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); + sppctl_gpio_od_writel(spp_gchip, reg, reg_off); + break; + + case PIN_CONFIG_INPUT_ENABLE: + break; + + case PIN_CONFIG_OUTPUT: + return sppctl_gpio_direction_output(chip, offset, 0); + + case PIN_CONFIG_PERSIST_STATE: + return -ENOTSUPP; + + default: + return -EINVAL; + } + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void sppctl_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + const char *label; + int i; + + for (i = 0; i < chip->ngpio; i++) { + label = gpiochip_is_requested(chip, i); + if (!label) + label = ""; + + seq_printf(s, " gpio-%03d (%-16.16s | %-16.16s)", i + chip->base, + chip->names[i], label); + seq_printf(s, " %c", sppctl_gpio_get_direction(chip, i) ? 'I' : 'O'); + seq_printf(s, ":%d", sppctl_gpio_get(chip, i)); + seq_printf(s, " %s", sppctl_first_get(chip, i) ? "gpi" : "mux"); + seq_printf(s, " %s", sppctl_master_get(chip, i) ? "gpi" : "iop"); + seq_printf(s, " %s", sppctl_gpio_inv_get(chip, i) ? "inv" : " "); + seq_printf(s, " %s", sppctl_gpio_output_od_get(chip, i) ? "oDr" : ""); + seq_puts(s, "\n"); + } +} +#endif + +static int sppctl_gpio_new(struct platform_device *pdev, struct sppctl_pdata *pctl) +{ + struct sppctl_gpio_chip *spp_gchip; + struct gpio_chip *gchip; + int err; + + spp_gchip = devm_kzalloc(&pdev->dev, sizeof(*spp_gchip), GFP_KERNEL); + if (!spp_gchip) + return -ENOMEM; + pctl->spp_gchip = spp_gchip; + + spp_gchip->gpioxt_base = pctl->gpioxt_base; + spp_gchip->first_base = pctl->first_base; + spin_lock_init(&spp_gchip->lock); + + gchip = &spp_gchip->chip; + gchip->label = SPPCTL_MODULE_NAME; + gchip->parent = &pdev->dev; + gchip->owner = THIS_MODULE; + gchip->request = gpiochip_generic_request; + gchip->free = gpiochip_generic_free; + gchip->get_direction = sppctl_gpio_get_direction; + gchip->direction_input = sppctl_gpio_direction_input; + gchip->direction_output = sppctl_gpio_direction_output; + gchip->get = sppctl_gpio_get; + gchip->set = sppctl_gpio_set; + gchip->set_config = sppctl_gpio_set_config; +#ifdef CONFIG_DEBUG_FS + gchip->dbg_show = sppctl_gpio_dbg_show; +#endif + gchip->base = -1; + gchip->ngpio = sppctl_gpio_list_sz; + gchip->names = sppctl_gpio_list_s; + gchip->of_gpio_n_cells = 2; + + pctl->pctl_grange.npins = gchip->ngpio; + pctl->pctl_grange.name = gchip->label; + pctl->pctl_grange.gc = gchip; + + err = devm_gpiochip_add_data(&pdev->dev, gchip, spp_gchip); + if (err) + return dev_err_probe(&pdev->dev, err, "Failed to add gpiochip!\n"); + + return 0; +} + +static int sppctl_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + unsigned int param = pinconf_to_config_param(*config); + unsigned int arg; + + switch (param) { + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!sppctl_gpio_output_od_get(&pctl->spp_gchip->chip, pin)) + return -EINVAL; + arg = 0; + break; + + case PIN_CONFIG_OUTPUT: + if (!sppctl_first_get(&pctl->spp_gchip->chip, pin)) + return -EINVAL; + if (!sppctl_master_get(&pctl->spp_gchip->chip, pin)) + return -EINVAL; + if (sppctl_gpio_get_direction(&pctl->spp_gchip->chip, pin)) + return -EINVAL; + arg = sppctl_gpio_get(&pctl->spp_gchip->chip, pin); + break; + + default: + return -EOPNOTSUPP; + } + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int sppctl_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + int i; + + /* Special handling for IOP pins */ + if (configs[0] == SPPCTL_IOP_CONFIGS) { + sppctl_first_master_set(&pctl->spp_gchip->chip, pin, mux_f_gpio, mux_m_iop); + return 0; + } + + for (i = 0; i < num_configs; i++) { + if (configs[i] & SPPCTL_PCTL_L_OUT) + sppctl_gpio_direction_output(&pctl->spp_gchip->chip, pin, 0); + if (configs[i] & SPPCTL_PCTL_L_OU1) + sppctl_gpio_direction_output(&pctl->spp_gchip->chip, pin, 1); + if (configs[i] & SPPCTL_PCTL_L_INV) + sppctl_gpio_input_inv_set(&pctl->spp_gchip->chip, pin); + if (configs[i] & SPPCTL_PCTL_L_ONV) + sppctl_gpio_output_inv_set(&pctl->spp_gchip->chip, pin); + if (configs[i] & SPPCTL_PCTL_L_ODR) + sppctl_gpio_output_od_set(&pctl->spp_gchip->chip, pin, 1); + } + + return 0; +} + +static const struct pinconf_ops sppctl_pconf_ops = { + .is_generic = true, + .pin_config_get = sppctl_pin_config_get, + .pin_config_set = sppctl_pin_config_set, +}; + +static int sppctl_get_functions_count(struct pinctrl_dev *pctldev) +{ + return sppctl_list_funcs_sz; +} + +static const char *sppctl_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return sppctl_list_funcs[selector].name; +} + +static int sppctl_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, + const char * const **groups, unsigned int *num_groups) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + const struct sppctl_func *f = &sppctl_list_funcs[selector]; + int i; + + *num_groups = 0; + switch (f->type) { + case pinmux_type_fpmx: + *num_groups = sppctl_pmux_list_sz; + *groups = sppctl_pmux_list_s; + break; + + case pinmux_type_grp: + if (!f->grps) + break; + + *num_groups = f->gnum; + for (i = 0; i < pctl->unq_grps_sz; i++) + if (pctl->g2fp_maps[i].f_idx == selector) + break; + *groups = &pctl->unq_grps[i]; + break; + + default: + dev_err(pctldev->dev, "Unknown pinmux (selector: %d, type: %d)\n", + selector, f->type); + break; + } + + return 0; +} + +/** + * sppctl_fully_pinmux_conv - Convert GPIO# to fully-pinmux control-field setting + * + * Each fully-pinmux function can be mapped to any of GPIO 8 ~ 71 by + * settings its control-field. Refer to following table: + * + * control-field | GPIO + * --------------+-------- + * 0 | No map + * 1 | 8 + * 2 | 9 + * 3 | 10 + * : | : + * 65 | 71 + */ +static inline int sppctl_fully_pinmux_conv(unsigned int offset) +{ + return (offset < 8) ? 0 : offset - 7; +} + +static int sppctl_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, + unsigned int group_selector) +{ + const struct sppctl_func *f = &sppctl_list_funcs[func_selector]; + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + struct grp2fp_map g2fpm = pctl->g2fp_maps[group_selector]; + int i; + + switch (f->type) { + case pinmux_type_fpmx: + sppctl_first_master_set(&pctl->spp_gchip->chip, group_selector, + mux_f_mux, mux_m_keep); + sppctl_func_set(pctl, func_selector, sppctl_fully_pinmux_conv(group_selector)); + break; + + case pinmux_type_grp: + for (i = 0; i < f->grps[g2fpm.g_idx].pnum; i++) + sppctl_first_master_set(&pctl->spp_gchip->chip, + f->grps[g2fpm.g_idx].pins[i], + mux_f_mux, mux_m_keep); + sppctl_gmx_set(pctl, f->roff, f->boff, f->blen, f->grps[g2fpm.g_idx].gval); + break; + + default: + dev_err(pctldev->dev, "Unknown pinmux type (func_selector: %d, type: %d)\n", + func_selector, f->type); + break; + } + + return 0; +} + +static int sppctl_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned int offset) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + int g_f, g_m; + + g_f = sppctl_first_get(&pctl->spp_gchip->chip, offset); + g_m = sppctl_master_get(&pctl->spp_gchip->chip, offset); + if (g_f == mux_f_gpio && g_m == mux_m_gpio) + return 0; + + sppctl_first_master_set(&pctl->spp_gchip->chip, offset, mux_f_gpio, mux_m_gpio); + return 0; +} + +static const struct pinmux_ops sppctl_pinmux_ops = { + .get_functions_count = sppctl_get_functions_count, + .get_function_name = sppctl_get_function_name, + .get_function_groups = sppctl_get_function_groups, + .set_mux = sppctl_set_mux, + .gpio_request_enable = sppctl_gpio_request_enable, + .strict = true, +}; + +static int sppctl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->unq_grps_sz; +} + +static const char *sppctl_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->unq_grps[selector]; +} + +static int sppctl_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, + const unsigned int **pins, unsigned int *num_pins) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + struct grp2fp_map g2fpm = pctl->g2fp_maps[selector]; + const struct sppctl_func *f; + + f = &sppctl_list_funcs[g2fpm.f_idx]; + *num_pins = 0; + + /* Except group-pinmux, each group has 1 pin. */ + if (f->type != pinmux_type_grp) { + *num_pins = 1; + *pins = &sppctl_pins_gpio[selector]; + return 0; + } + + /* Group-pinmux may have more than one pin. */ + if (!f->grps) + return 0; + + if (f->gnum < 1) + return 0; + + *num_pins = f->grps[g2fpm.g_idx].pnum; + *pins = f->grps[g2fpm.g_idx].pins; + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void sppctl_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned int offset) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + const char *pin_type; + u8 first, master; + + first = sppctl_first_get(&pctl->spp_gchip->chip, offset); + master = sppctl_master_get(&pctl->spp_gchip->chip, offset); + if (first) + if (master) + pin_type = "GPIO"; + else + pin_type = " IOP"; + else + pin_type = " MUX"; + seq_printf(s, " %s", pin_type); +} +#endif + +static int sppctl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np_config, + struct pinctrl_map **map, unsigned int *num_maps) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + int nmG = of_property_count_strings(np_config, "groups"); + const struct sppctl_func *f = NULL; + u8 pin_num, pin_type, pin_func; + struct device_node *parent; + unsigned long *configs; + struct property *prop; + const char *s_f, *s_g; + + const __be32 *list; + u32 dt_pin, dt_fun; + int i, size = 0; + + list = of_get_property(np_config, "sunplus,pins", &size); + + if (nmG <= 0) + nmG = 0; + + parent = of_get_parent(np_config); + *num_maps = size / sizeof(*list); + + /* + * Process property: + * sunplus,pins = < u32 u32 u32 ... >; + * + * Each 32-bit integer defines a individual pin in which: + * + * Bit 32~24: defines GPIO pin number. Its range is 0 ~ 98. + * Bit 23~16: defines types: (1) fully-pinmux pins + * (2) IO processor pins + * (3) digital GPIO pins + * Bit 15~8: defines pins of peripherals (which are defined in + * 'include/dt-binging/pinctrl/sppctl.h'). + * Bit 7~0: defines types or initial-state of digital GPIO pins. + */ + for (i = 0; i < (*num_maps); i++) { + dt_pin = be32_to_cpu(list[i]); + pin_num = FIELD_GET(GENMASK(31, 24), dt_pin); + + if (pin_num >= sppctl_pins_all_sz) { + dev_err(pctldev->dev, "Invalid pin property at index %d (0x%08x)\n", + i, dt_pin); + return -EINVAL; + } + } + + *map = kcalloc(*num_maps + nmG, sizeof(**map), GFP_KERNEL); + for (i = 0; i < (*num_maps); i++) { + dt_pin = be32_to_cpu(list[i]); + pin_num = FIELD_GET(GENMASK(31, 24), dt_pin); + pin_type = FIELD_GET(GENMASK(23, 16), dt_pin); + pin_func = FIELD_GET(GENMASK(15, 8), dt_pin); + (*map)[i].name = parent->name; + + if (pin_type == SPPCTL_PCTL_G_GPIO) { + /* A digital GPIO pin */ + (*map)[i].type = PIN_MAP_TYPE_CONFIGS_PIN; + (*map)[i].data.configs.num_configs = 1; + (*map)[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_num); + configs = kmalloc(sizeof(*configs), GFP_KERNEL); + *configs = FIELD_GET(GENMASK(7, 0), dt_pin); + (*map)[i].data.configs.configs = configs; + + dev_dbg(pctldev->dev, "%s: GPIO (%s)\n", + (*map)[i].data.configs.group_or_pin, + (*configs & (SPPCTL_PCTL_L_OUT | SPPCTL_PCTL_L_OU1)) ? + "OUT" : "IN"); + } else if (pin_type == SPPCTL_PCTL_G_IOPP) { + /* A IO Processor (IOP) pin */ + (*map)[i].type = PIN_MAP_TYPE_CONFIGS_PIN; + (*map)[i].data.configs.num_configs = 1; + (*map)[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_num); + configs = kmalloc(sizeof(*configs), GFP_KERNEL); + *configs = SPPCTL_IOP_CONFIGS; + (*map)[i].data.configs.configs = configs; + + dev_dbg(pctldev->dev, "%s: IOP\n", + (*map)[i].data.configs.group_or_pin); + } else { + /* A fully-pinmux pin */ + (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[i].data.mux.function = sppctl_list_funcs[pin_func].name; + (*map)[i].data.mux.group = pin_get_name(pctldev, pin_num); + + dev_dbg(pctldev->dev, "%s: %s\n", (*map)[i].data.mux.group, + (*map)[i].data.mux.function); + } + } + + /* + * Process properties: + * function = "xxx"; + * groups = "yyy"; + */ + if (nmG > 0 && of_property_read_string(np_config, "function", &s_f) == 0) { + of_property_for_each_string(np_config, "groups", prop, s_g) { + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.function = s_f; + (*map)[*num_maps].data.mux.group = s_g; + (*num_maps)++; + + dev_dbg(pctldev->dev, "%s: %s\n", s_f, s_g); + } + } + + /* + * Process property: + * sunplus,zerofunc = < u32 u32 u32 ...> + */ + list = of_get_property(np_config, "sunplus,zerofunc", &size); + if (list) { + for (i = 0; i < (size / sizeof(*list)); i++) { + dt_fun = be32_to_cpu(list[i]); + if (dt_fun >= sppctl_list_funcs_sz) { + dev_err(pctldev->dev, "Zero-func %d out of range!\n", + dt_fun); + continue; + } + + f = &sppctl_list_funcs[dt_fun]; + switch (f->type) { + case pinmux_type_fpmx: + sppctl_func_set(pctl, dt_fun, 0); + dev_dbg(pctldev->dev, "%s: No map\n", f->name); + break; + + case pinmux_type_grp: + sppctl_gmx_set(pctl, f->roff, f->boff, f->blen, 0); + dev_dbg(pctldev->dev, "%s: No map\n", f->name); + break; + + default: + dev_err(pctldev->dev, "Wrong zero-group: %d (%s)\n", + dt_fun, f->name); + break; + } + } + } + + of_node_put(parent); + dev_dbg(pctldev->dev, "%d pins mapped\n", *num_maps); + return 0; +} + +static const struct pinctrl_ops sppctl_pctl_ops = { + .get_groups_count = sppctl_get_groups_count, + .get_group_name = sppctl_get_group_name, + .get_group_pins = sppctl_get_group_pins, +#ifdef CONFIG_DEBUG_FS + .pin_dbg_show = sppctl_pin_dbg_show, +#endif + .dt_node_to_map = sppctl_dt_node_to_map, + .dt_free_map = pinctrl_utils_free_map, +}; + +static int sppctl_group_groups(struct platform_device *pdev) +{ + struct sppctl_pdata *sppctl = platform_get_drvdata(pdev); + int i, k, j; + + /* Calculate number of total group (GPIO + group-pinmux group). */ + sppctl->unq_grps_sz = sppctl_gpio_list_sz; + for (i = 0; i < sppctl_list_funcs_sz; i++) + if (sppctl_list_funcs[i].type == pinmux_type_grp) + sppctl->unq_grps_sz += sppctl_list_funcs[i].gnum; + + sppctl->unq_grps = devm_kcalloc(&pdev->dev, sppctl->unq_grps_sz + 1, + sizeof(*sppctl->unq_grps), GFP_KERNEL); + if (!sppctl->unq_grps) + return -ENOMEM; + + sppctl->g2fp_maps = devm_kcalloc(&pdev->dev, sppctl->unq_grps_sz + 1, + sizeof(*sppctl->g2fp_maps), GFP_KERNEL); + if (!sppctl->g2fp_maps) + return -ENOMEM; + + /* Add GPIO pins. */ + for (i = 0; i < sppctl_gpio_list_sz; i++) { + sppctl->unq_grps[i] = sppctl_gpio_list_s[i]; + sppctl->g2fp_maps[i].f_idx = 0; + sppctl->g2fp_maps[i].g_idx = i; + } + + /* Add group-pinmux to end of GPIO pins. */ + j = sppctl_gpio_list_sz; + for (i = 0; i < sppctl_list_funcs_sz; i++) { + if (sppctl_list_funcs[i].type != pinmux_type_grp) + continue; + + for (k = 0; k < sppctl_list_funcs[i].gnum; k++) { + sppctl->unq_grps[j] = sppctl_list_funcs[i].grps[k].name; + sppctl->g2fp_maps[j].f_idx = i; + sppctl->g2fp_maps[j].g_idx = k; + j++; + } + } + + return 0; +} + +static int sppctl_pinctrl_init(struct platform_device *pdev) +{ + struct sppctl_pdata *sppctl = platform_get_drvdata(pdev); + int err; + + sppctl->pctl_desc.owner = THIS_MODULE; + sppctl->pctl_desc.name = dev_name(&pdev->dev); + sppctl->pctl_desc.pins = sppctl_pins_all; + sppctl->pctl_desc.npins = sppctl_pins_all_sz; + sppctl->pctl_desc.pctlops = &sppctl_pctl_ops; + sppctl->pctl_desc.confops = &sppctl_pconf_ops; + sppctl->pctl_desc.pmxops = &sppctl_pinmux_ops; + + err = sppctl_group_groups(pdev); + if (err) + return err; + + err = devm_pinctrl_register_and_init(&pdev->dev, &sppctl->pctl_desc, + sppctl, &sppctl->pctl_dev); + if (err) + return dev_err_probe(&pdev->dev, err, "Failed to register pinctrl!\n"); + + pinctrl_enable(sppctl->pctl_dev); + return 0; +} + +static int sppctl_resource_map(struct platform_device *pdev, struct sppctl_pdata *sppctl) +{ + sppctl->moon2_base = devm_platform_ioremap_resource_byname(pdev, "moon2"); + if (IS_ERR(sppctl->moon2_base)) + return PTR_ERR(sppctl->moon2_base); + + sppctl->gpioxt_base = devm_platform_ioremap_resource_byname(pdev, "gpioxt"); + if (IS_ERR(sppctl->gpioxt_base)) + return PTR_ERR(sppctl->gpioxt_base); + + sppctl->first_base = devm_platform_ioremap_resource_byname(pdev, "first"); + if (IS_ERR(sppctl->first_base)) + return PTR_ERR(sppctl->first_base); + + sppctl->moon1_base = devm_platform_ioremap_resource_byname(pdev, "moon1"); + if (IS_ERR(sppctl->moon1_base)) + return PTR_ERR(sppctl->moon1_base); + + return 0; +} + +static int sppctl_probe(struct platform_device *pdev) +{ + struct sppctl_pdata *sppctl; + int ret; + + sppctl = devm_kzalloc(&pdev->dev, sizeof(*sppctl), GFP_KERNEL); + if (!sppctl) + return -ENOMEM; + platform_set_drvdata(pdev, sppctl); + + ret = sppctl_resource_map(pdev, sppctl); + if (ret) + return ret; + + ret = sppctl_gpio_new(pdev, sppctl); + if (ret) + return ret; + + ret = sppctl_pinctrl_init(pdev); + if (ret) + return ret; + + pinctrl_add_gpio_range(sppctl->pctl_dev, &sppctl->pctl_grange); + + return 0; +} + +static const struct of_device_id sppctl_match_table[] = { + { .compatible = "sunplus,sp7021-pctl" }, + { /* sentinel */ } +}; + +static struct platform_driver sppctl_pinctrl_driver = { + .driver = { + .name = SPPCTL_MODULE_NAME, + .of_match_table = sppctl_match_table, + }, + .probe = sppctl_probe, +}; +builtin_platform_driver(sppctl_pinctrl_driver) + +MODULE_AUTHOR("Dvorkin Dmitry <dvorkin@tibbo.com>"); +MODULE_AUTHOR("Wells Lu <wellslutw@gmail.com>"); +MODULE_DESCRIPTION("Sunplus SP7021 Pin Control and GPIO driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/sunplus/sppctl.h b/drivers/pinctrl/sunplus/sppctl.h new file mode 100644 index 000000000000..6210f2200586 --- /dev/null +++ b/drivers/pinctrl/sunplus/sppctl.h @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * SP7021 Pin Controller Driver. + * Copyright (C) Sunplus Tech / Tibbo Tech. + */ + +#ifndef __SPPCTL_H__ +#define __SPPCTL_H__ + +#include <linux/bits.h> +#include <linux/gpio/driver.h> +#include <linux/kernel.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/spinlock.h> +#include <linux/types.h> + +#define SPPCTL_MODULE_NAME "sppctl_sp7021" + +#define SPPCTL_GPIO_OFF_FIRST 0x00 +#define SPPCTL_GPIO_OFF_MASTER 0x00 +#define SPPCTL_GPIO_OFF_OE 0x20 +#define SPPCTL_GPIO_OFF_OUT 0x40 +#define SPPCTL_GPIO_OFF_IN 0x60 +#define SPPCTL_GPIO_OFF_IINV 0x80 +#define SPPCTL_GPIO_OFF_OINV 0xa0 +#define SPPCTL_GPIO_OFF_OD 0xc0 + +#define SPPCTL_FULLY_PINMUX_MASK_MASK GENMASK(22, 16) +#define SPPCTL_FULLY_PINMUX_SEL_MASK GENMASK(6, 0) +#define SPPCTL_FULLY_PINMUX_UPPER_SHIFT 8 + +/* + * Mask-fields and control-fields of MOON registers of SP7021 are + * arranged as shown below: + * + * register | mask-fields | control-fields + * ----------+--------------+---------------- + * base[0] | (31 : 16) | (15 : 0) + * base[1] | (31 : 24) | (15 : 0) + * base[2] | (31 : 24) | (15 : 0) + * : | : | : + * + * where mask-fields are used to protect control-fields from write-in + * accidentally. Set the corresponding bits in the mask-field before + * you write a value into a control-field. + */ +#define SPPCTL_MOON_REG_MASK_SHIFT 16 +#define SPPCTL_SET_MOON_REG_BIT(bit) (BIT((bit) + SPPCTL_MOON_REG_MASK_SHIFT) | BIT(bit)) +#define SPPCTL_CLR_MOON_REG_BIT(bit) BIT((bit) + SPPCTL_MOON_REG_MASK_SHIFT) + +#define SPPCTL_IOP_CONFIGS 0xff + +#define FNCE(n, r, o, bo, bl, g) { \ + .name = n, \ + .type = r, \ + .roff = o, \ + .boff = bo, \ + .blen = bl, \ + .grps = (g), \ + .gnum = ARRAY_SIZE(g), \ +} + +#define FNCN(n, r, o, bo, bl) { \ + .name = n, \ + .type = r, \ + .roff = o, \ + .boff = bo, \ + .blen = bl, \ + .grps = NULL, \ + .gnum = 0, \ +} + +#define EGRP(n, v, p) { \ + .name = n, \ + .gval = (v), \ + .pins = (p), \ + .pnum = ARRAY_SIZE(p), \ +} + +/** + * enum mux_first_reg - Define modes of access of FIRST register + * @mux_f_mux: Set the corresponding pin to a fully-pinmux pin + * @mux_f_gpio: Set the corresponding pin to a GPIO or IOP pin + * @mux_f_keep: Don't change (keep intact) + */ +enum mux_first_reg { + mux_f_mux = 0, + mux_f_gpio = 1, + mux_f_keep = 2, +}; + +/** + * enum mux_master_reg - Define modes of access of MASTER register + * @mux_m_iop: Set the corresponding pin to an IO processor (IOP) pin + * @mux_m_gpio: Set the corresponding pin to a digital GPIO pin + * @mux_m_keep: Don't change (keep intact) + */ +enum mux_master_reg { + mux_m_iop = 0, + mux_m_gpio = 1, + mux_m_keep = 2, +}; + +/** + * enum pinmux_type - Define types of pinmux pins + * @pinmux_type_fpmx: A fully-pinmux pin + * @pinmux_type_grp: A group-pinmux pin + */ +enum pinmux_type { + pinmux_type_fpmx, + pinmux_type_grp, +}; + +/** + * struct grp2fp_map - A map storing indexes + * @f_idx: an index to function table + * @g_idx: an index to group table + */ +struct grp2fp_map { + u16 f_idx; + u16 g_idx; +}; + +struct sppctl_gpio_chip; + +struct sppctl_pdata { + void __iomem *moon2_base; /* MOON2 */ + void __iomem *gpioxt_base; /* MASTER, OE, OUT, IN, I_INV, O_INV, OD */ + void __iomem *first_base; /* FIRST */ + void __iomem *moon1_base; /* MOON1 */ + + struct pinctrl_desc pctl_desc; + struct pinctrl_dev *pctl_dev; + struct pinctrl_gpio_range pctl_grange; + struct sppctl_gpio_chip *spp_gchip; + + char const **unq_grps; + size_t unq_grps_sz; + struct grp2fp_map *g2fp_maps; +}; + +struct sppctl_grp { + const char * const name; + const u8 gval; /* group number */ + const unsigned * const pins; /* list of pins */ + const unsigned int pnum; /* number of pins */ +}; + +struct sppctl_func { + const char * const name; + const enum pinmux_type type; /* function type */ + const u8 roff; /* register offset */ + const u8 boff; /* bit offset */ + const u8 blen; /* bit length */ + const struct sppctl_grp * const grps; /* list of groups */ + const unsigned int gnum; /* number of groups */ +}; + +extern const struct sppctl_func sppctl_list_funcs[]; +extern const char * const sppctl_pmux_list_s[]; +extern const char * const sppctl_gpio_list_s[]; +extern const struct pinctrl_pin_desc sppctl_pins_all[]; +extern const unsigned int sppctl_pins_gpio[]; + +extern const size_t sppctl_list_funcs_sz; +extern const size_t sppctl_pmux_list_sz; +extern const size_t sppctl_gpio_list_sz; +extern const size_t sppctl_pins_all_sz; + +#endif diff --git a/drivers/pinctrl/sunplus/sppctl_sp7021.c b/drivers/pinctrl/sunplus/sppctl_sp7021.c new file mode 100644 index 000000000000..9748345b9298 --- /dev/null +++ b/drivers/pinctrl/sunplus/sppctl_sp7021.c @@ -0,0 +1,583 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SP7021 Pin Controller Driver. + * Copyright (C) Sunplus Tech / Tibbo Tech. + */ + +#include <linux/gpio/driver.h> +#include <linux/kernel.h> +#include <linux/pinctrl/pinctrl.h> + +#include "sppctl.h" + +#define D_PIS(x, y) "P" __stringify(x) "_0" __stringify(y) +#define D(x, y) ((x) * 8 + (y)) +#define P(x, y) PINCTRL_PIN(D(x, y), D_PIS(x, y)) + +const char * const sppctl_gpio_list_s[] = { + D_PIS(0, 0), D_PIS(0, 1), D_PIS(0, 2), D_PIS(0, 3), + D_PIS(0, 4), D_PIS(0, 5), D_PIS(0, 6), D_PIS(0, 7), + D_PIS(1, 0), D_PIS(1, 1), D_PIS(1, 2), D_PIS(1, 3), + D_PIS(1, 4), D_PIS(1, 5), D_PIS(1, 6), D_PIS(1, 7), + D_PIS(2, 0), D_PIS(2, 1), D_PIS(2, 2), D_PIS(2, 3), + D_PIS(2, 4), D_PIS(2, 5), D_PIS(2, 6), D_PIS(2, 7), + D_PIS(3, 0), D_PIS(3, 1), D_PIS(3, 2), D_PIS(3, 3), + D_PIS(3, 4), D_PIS(3, 5), D_PIS(3, 6), D_PIS(3, 7), + D_PIS(4, 0), D_PIS(4, 1), D_PIS(4, 2), D_PIS(4, 3), + D_PIS(4, 4), D_PIS(4, 5), D_PIS(4, 6), D_PIS(4, 7), + D_PIS(5, 0), D_PIS(5, 1), D_PIS(5, 2), D_PIS(5, 3), + D_PIS(5, 4), D_PIS(5, 5), D_PIS(5, 6), D_PIS(5, 7), + D_PIS(6, 0), D_PIS(6, 1), D_PIS(6, 2), D_PIS(6, 3), + D_PIS(6, 4), D_PIS(6, 5), D_PIS(6, 6), D_PIS(6, 7), + D_PIS(7, 0), D_PIS(7, 1), D_PIS(7, 2), D_PIS(7, 3), + D_PIS(7, 4), D_PIS(7, 5), D_PIS(7, 6), D_PIS(7, 7), + D_PIS(8, 0), D_PIS(8, 1), D_PIS(8, 2), D_PIS(8, 3), + D_PIS(8, 4), D_PIS(8, 5), D_PIS(8, 6), D_PIS(8, 7), + D_PIS(9, 0), D_PIS(9, 1), D_PIS(9, 2), D_PIS(9, 3), + D_PIS(9, 4), D_PIS(9, 5), D_PIS(9, 6), D_PIS(9, 7), + D_PIS(10, 0), D_PIS(10, 1), D_PIS(10, 2), D_PIS(10, 3), + D_PIS(10, 4), D_PIS(10, 5), D_PIS(10, 6), D_PIS(10, 7), + D_PIS(11, 0), D_PIS(11, 1), D_PIS(11, 2), D_PIS(11, 3), + D_PIS(11, 4), D_PIS(11, 5), D_PIS(11, 6), D_PIS(11, 7), + D_PIS(12, 0), D_PIS(12, 1), D_PIS(12, 2), +}; + +const size_t sppctl_gpio_list_sz = ARRAY_SIZE(sppctl_gpio_list_s); + +const unsigned int sppctl_pins_gpio[] = { + D(0, 0), D(0, 1), D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7), + D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), + D(2, 0), D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), + D(3, 0), D(3, 1), D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7), + D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7), + D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7), + D(6, 0), D(6, 1), D(6, 2), D(6, 3), D(6, 4), D(6, 5), D(6, 6), D(6, 7), + D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7), + D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), D(8, 7), + D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), D(9, 6), D(9, 7), + D(10, 0), D(10, 1), D(10, 2), D(10, 3), D(10, 4), D(10, 5), D(10, 6), D(10, 7), + D(11, 0), D(11, 1), D(11, 2), D(11, 3), D(11, 4), D(11, 5), D(11, 6), D(11, 7), + D(12, 0), D(12, 1), D(12, 2), +}; + +const struct pinctrl_pin_desc sppctl_pins_all[] = { + /* gpio and iop only */ + P(0, 0), P(0, 1), P(0, 2), P(0, 3), P(0, 4), P(0, 5), P(0, 6), P(0, 7), + /* gpio, iop, muxable */ + P(1, 0), P(1, 1), P(1, 2), P(1, 3), P(1, 4), P(1, 5), P(1, 6), P(1, 7), + P(2, 0), P(2, 1), P(2, 2), P(2, 3), P(2, 4), P(2, 5), P(2, 6), P(2, 7), + P(3, 0), P(3, 1), P(3, 2), P(3, 3), P(3, 4), P(3, 5), P(3, 6), P(3, 7), + P(4, 0), P(4, 1), P(4, 2), P(4, 3), P(4, 4), P(4, 5), P(4, 6), P(4, 7), + P(5, 0), P(5, 1), P(5, 2), P(5, 3), P(5, 4), P(5, 5), P(5, 6), P(5, 7), + P(6, 0), P(6, 1), P(6, 2), P(6, 3), P(6, 4), P(6, 5), P(6, 6), P(6, 7), + P(7, 0), P(7, 1), P(7, 2), P(7, 3), P(7, 4), P(7, 5), P(7, 6), P(7, 7), + P(8, 0), P(8, 1), P(8, 2), P(8, 3), P(8, 4), P(8, 5), P(8, 6), P(8, 7), + /* gpio and iop only */ + P(9, 0), P(9, 1), P(9, 2), P(9, 3), P(9, 4), P(9, 5), P(9, 6), P(9, 7), + P(10, 0), P(10, 1), P(10, 2), P(10, 3), P(10, 4), P(10, 5), P(10, 6), P(10, 7), + P(11, 0), P(11, 1), P(11, 2), P(11, 3), P(11, 4), P(11, 5), P(11, 6), P(11, 7), + P(12, 0), P(12, 1), P(12, 2), +}; + +const size_t sppctl_pins_all_sz = ARRAY_SIZE(sppctl_pins_all); + +const char * const sppctl_pmux_list_s[] = { + D_PIS(0, 0), + D_PIS(1, 0), D_PIS(1, 1), D_PIS(1, 2), D_PIS(1, 3), + D_PIS(1, 4), D_PIS(1, 5), D_PIS(1, 6), D_PIS(1, 7), + D_PIS(2, 0), D_PIS(2, 1), D_PIS(2, 2), D_PIS(2, 3), + D_PIS(2, 4), D_PIS(2, 5), D_PIS(2, 6), D_PIS(2, 7), + D_PIS(3, 0), D_PIS(3, 1), D_PIS(3, 2), D_PIS(3, 3), + D_PIS(3, 4), D_PIS(3, 5), D_PIS(3, 6), D_PIS(3, 7), + D_PIS(4, 0), D_PIS(4, 1), D_PIS(4, 2), D_PIS(4, 3), + D_PIS(4, 4), D_PIS(4, 5), D_PIS(4, 6), D_PIS(4, 7), + D_PIS(5, 0), D_PIS(5, 1), D_PIS(5, 2), D_PIS(5, 3), + D_PIS(5, 4), D_PIS(5, 5), D_PIS(5, 6), D_PIS(5, 7), + D_PIS(6, 0), D_PIS(6, 1), D_PIS(6, 2), D_PIS(6, 3), + D_PIS(6, 4), D_PIS(6, 5), D_PIS(6, 6), D_PIS(6, 7), + D_PIS(7, 0), D_PIS(7, 1), D_PIS(7, 2), D_PIS(7, 3), + D_PIS(7, 4), D_PIS(7, 5), D_PIS(7, 6), D_PIS(7, 7), + D_PIS(8, 0), D_PIS(8, 1), D_PIS(8, 2), D_PIS(8, 3), + D_PIS(8, 4), D_PIS(8, 5), D_PIS(8, 6), D_PIS(8, 7), +}; + +const size_t sppctl_pmux_list_sz = ARRAY_SIZE(sppctl_pmux_list_s); + +static const unsigned int pins_spif1[] = { + D(10, 3), D(10, 4), D(10, 6), D(10, 7), +}; + +static const unsigned int pins_spif2[] = { + D(9, 4), D(9, 6), D(9, 7), D(10, 1), +}; + +static const struct sppctl_grp sp7021grps_spif[] = { + EGRP("SPI_FLASH1", 1, pins_spif1), + EGRP("SPI_FLASH2", 2, pins_spif2), +}; + +static const unsigned int pins_spi41[] = { + D(10, 2), D(10, 5), +}; + +static const unsigned int pins_spi42[] = { + D(9, 5), D(9, 8), +}; + +static const struct sppctl_grp sp7021grps_spi4[] = { + EGRP("SPI_FLASH_4BIT1", 1, pins_spi41), + EGRP("SPI_FLASH_4BIT2", 2, pins_spi42), +}; + +static const unsigned int pins_snan[] = { + D(9, 4), D(9, 5), D(9, 6), D(9, 7), D(10, 0), D(10, 1), +}; + +static const struct sppctl_grp sp7021grps_snan[] = { + EGRP("SPI_NAND", 1, pins_snan), +}; + +static const unsigned int pins_emmc[] = { + D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), + D(9, 6), D(9, 7), D(10, 0), D(10, 1), +}; + +static const struct sppctl_grp sp7021grps_emmc[] = { + EGRP("CARD0_EMMC", 1, pins_emmc), +}; + +static const unsigned int pins_sdsd[] = { + D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), +}; + +static const struct sppctl_grp sp7021grps_sdsd[] = { + EGRP("SD_CARD", 1, pins_sdsd), +}; + +static const unsigned int pins_uar0[] = { + D(11, 0), D(11, 1), +}; + +static const struct sppctl_grp sp7021grps_uar0[] = { + EGRP("UA0", 1, pins_uar0), +}; + +static const unsigned int pins_adbg1[] = { + D(10, 2), D(10, 3), +}; + +static const unsigned int pins_adbg2[] = { + D(7, 1), D(7, 2), +}; + +static const struct sppctl_grp sp7021grps_adbg[] = { + EGRP("ACHIP_DEBUG1", 1, pins_adbg1), + EGRP("ACHIP_DEBUG2", 2, pins_adbg2), +}; + +static const unsigned int pins_aua2axi1[] = { + D(2, 0), D(2, 1), D(2, 2), +}; + +static const unsigned int pins_aua2axi2[] = { + D(1, 0), D(1, 1), D(1, 2), +}; + +static const struct sppctl_grp sp7021grps_au2x[] = { + EGRP("ACHIP_UA2AXI1", 1, pins_aua2axi1), + EGRP("ACHIP_UA2AXI2", 2, pins_aua2axi2), +}; + +static const unsigned int pins_fpga[] = { + D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7), + D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), + D(1, 6), D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3), + D(2, 4), D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), + D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7), + D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), + D(4, 6), D(4, 7), D(5, 0), D(5, 1), D(5, 2), +}; + +static const struct sppctl_grp sp7021grps_fpga[] = { + EGRP("FPGA_IFX", 1, pins_fpga), +}; + +static const unsigned int pins_hdmi1[] = { + D(10, 6), D(12, 2), D(12, 1), +}; + +static const unsigned int pins_hdmi2[] = { + D(8, 3), D(8, 5), D(8, 6), +}; + +static const unsigned int pins_hdmi3[] = { + D(7, 4), D(7, 6), D(7, 7), +}; + +static const struct sppctl_grp sp7021grps_hdmi[] = { + EGRP("HDMI_TX1", 1, pins_hdmi1), + EGRP("HDMI_TX2", 2, pins_hdmi2), + EGRP("HDMI_TX3", 3, pins_hdmi3), +}; + +static const unsigned int pins_eadc[] = { + D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), +}; + +static const struct sppctl_grp sp7021grps_eadc[] = { + EGRP("AUD_EXT_ADC_IFX0", 1, pins_eadc), +}; + +static const unsigned int pins_edac[] = { + D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), D(3, 4), +}; + +static const struct sppctl_grp sp7021grps_edac[] = { + EGRP("AUD_EXT_DAC_IFX0", 1, pins_edac), +}; + +static const unsigned int pins_spdi[] = { + D(2, 4), +}; + +static const struct sppctl_grp sp7021grps_spdi[] = { + EGRP("AUD_IEC_RX0", 1, pins_spdi), +}; + +static const unsigned int pins_spdo[] = { + D(3, 6), +}; + +static const struct sppctl_grp sp7021grps_spdo[] = { + EGRP("AUD_IEC_TX0", 1, pins_spdo), +}; + +static const unsigned int pins_tdmt[] = { + D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), +}; + +static const struct sppctl_grp sp7021grps_tdmt[] = { + EGRP("TDMTX_IFX0", 1, pins_tdmt), +}; + +static const unsigned int pins_tdmr[] = { + D(1, 7), D(2, 0), D(2, 1), D(2, 2), +}; + +static const struct sppctl_grp sp7021grps_tdmr[] = { + EGRP("TDMRX_IFX0", 1, pins_tdmr), +}; + +static const unsigned int pins_pdmr[] = { + D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3), +}; + +static const struct sppctl_grp sp7021grps_pdmr[] = { + EGRP("PDMRX_IFX0", 1, pins_pdmr), +}; + +static const unsigned int pins_pcmt[] = { + D(3, 7), D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), +}; + +static const struct sppctl_grp sp7021grps_pcmt[] = { + EGRP("PCM_IEC_TX", 1, pins_pcmt), +}; + +static const unsigned int pins_lcdi[] = { + D(1, 4), D(1, 5), D(1, 6), D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3), + D(2, 4), D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), D(3, 3), + D(3, 4), D(3, 5), D(3, 6), D(3, 7), D(4, 0), D(4, 1), D(4, 2), D(4, 3), + D(4, 4), D(4, 5), D(4, 6), D(4, 7), +}; + +static const struct sppctl_grp sp7021grps_lcdi[] = { + EGRP("LCDIF", 1, pins_lcdi), +}; + +static const unsigned int pins_dvdd[] = { + D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7), + D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), +}; + +static const struct sppctl_grp sp7021grps_dvdd[] = { + EGRP("DVD_DSP_DEBUG", 1, pins_dvdd), +}; + +static const unsigned int pins_i2cd[] = { + D(1, 0), D(1, 1), +}; + +static const struct sppctl_grp sp7021grps_i2cd[] = { + EGRP("I2C_DEBUG", 1, pins_i2cd), +}; + +static const unsigned int pins_i2cs[] = { + D(0, 0), D(0, 1), +}; + +static const struct sppctl_grp sp7021grps_i2cs[] = { + EGRP("I2C_SLAVE", 1, pins_i2cs), +}; + +static const unsigned int pins_wakp[] = { + D(10, 5), +}; + +static const struct sppctl_grp sp7021grps_wakp[] = { + EGRP("WAKEUP", 1, pins_wakp), +}; + +static const unsigned int pins_u2ax[] = { + D(2, 0), D(2, 1), D(3, 0), D(3, 1), +}; + +static const struct sppctl_grp sp7021grps_u2ax[] = { + EGRP("UART2AXI", 1, pins_u2ax), +}; + +static const unsigned int pins_u0ic[] = { + D(0, 0), D(0, 1), D(0, 4), D(0, 5), D(1, 0), D(1, 1), +}; + +static const struct sppctl_grp sp7021grps_u0ic[] = { + EGRP("USB0_I2C", 1, pins_u0ic), +}; + +static const unsigned int pins_u1ic[] = { + D(0, 2), D(0, 3), D(0, 6), D(0, 7), D(1, 2), D(1, 3), +}; + +static const struct sppctl_grp sp7021grps_u1ic[] = { + EGRP("USB1_I2C", 1, pins_u1ic), +}; + +static const unsigned int pins_u0ot[] = { + D(11, 2), +}; + +static const struct sppctl_grp sp7021grps_u0ot[] = { + EGRP("USB0_OTG", 1, pins_u0ot), +}; + +static const unsigned int pins_u1ot[] = { + D(11, 3), +}; + +static const struct sppctl_grp sp7021grps_u1ot[] = { + EGRP("USB1_OTG", 1, pins_u1ot), +}; + +static const unsigned int pins_uphd[] = { + D(0, 1), D(0, 2), D(0, 3), D(7, 4), D(7, 5), D(7, 6), + D(7, 7), D(8, 0), D(8, 1), D(8, 2), D(8, 3), + D(9, 7), D(10, 2), D(10, 3), D(10, 4), +}; + +static const struct sppctl_grp sp7021grps_up0d[] = { + EGRP("UPHY0_DEBUG", 1, pins_uphd), +}; + +static const struct sppctl_grp sp7021grps_up1d[] = { + EGRP("UPHY1_DEBUG", 1, pins_uphd), +}; + +static const unsigned int pins_upex[] = { + D(0, 0), D(0, 1), D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7), + D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), + D(2, 0), D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), + D(3, 0), D(3, 1), D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7), + D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7), + D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7), + D(6, 0), D(6, 1), D(6, 2), D(6, 3), D(6, 4), D(6, 5), D(6, 6), D(6, 7), + D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7), + D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), D(8, 7), + D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), D(9, 6), D(9, 7), + D(10, 0), D(10, 1), D(10, 2), D(10, 3), D(10, 4), D(10, 5), D(10, 6), D(10, 7), +}; + +static const struct sppctl_grp sp7021grps_upex[] = { + EGRP("UPHY0_EXT", 1, pins_upex), +}; + +static const unsigned int pins_prp1[] = { + D(0, 6), D(0, 7), + D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), + D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), + D(3, 0), D(3, 1), D(3, 2), +}; + +static const unsigned int pins_prp2[] = { + D(3, 4), D(3, 6), D(3, 7), + D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7), + D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7), + D(6, 4), +}; + +static const struct sppctl_grp sp7021grps_prbp[] = { + EGRP("PROBE_PORT1", 1, pins_prp1), + EGRP("PROBE_PORT2", 2, pins_prp2), +}; + +const struct sppctl_func sppctl_list_funcs[] = { + FNCN("L2SW_CLK_OUT", pinmux_type_fpmx, 0x00, 0, 7), + FNCN("L2SW_MAC_SMI_MDC", pinmux_type_fpmx, 0x00, 8, 7), + FNCN("L2SW_LED_FLASH0", pinmux_type_fpmx, 0x01, 0, 7), + FNCN("L2SW_LED_FLASH1", pinmux_type_fpmx, 0x01, 8, 7), + FNCN("L2SW_LED_ON0", pinmux_type_fpmx, 0x02, 0, 7), + FNCN("L2SW_LED_ON1", pinmux_type_fpmx, 0x02, 8, 7), + FNCN("L2SW_MAC_SMI_MDIO", pinmux_type_fpmx, 0x03, 0, 7), + FNCN("L2SW_P0_MAC_RMII_TXEN", pinmux_type_fpmx, 0x03, 8, 7), + FNCN("L2SW_P0_MAC_RMII_TXD0", pinmux_type_fpmx, 0x04, 0, 7), + FNCN("L2SW_P0_MAC_RMII_TXD1", pinmux_type_fpmx, 0x04, 8, 7), + FNCN("L2SW_P0_MAC_RMII_CRSDV", pinmux_type_fpmx, 0x05, 0, 7), + FNCN("L2SW_P0_MAC_RMII_RXD0", pinmux_type_fpmx, 0x05, 8, 7), + FNCN("L2SW_P0_MAC_RMII_RXD1", pinmux_type_fpmx, 0x06, 0, 7), + FNCN("L2SW_P0_MAC_RMII_RXER", pinmux_type_fpmx, 0x06, 8, 7), + FNCN("L2SW_P1_MAC_RMII_TXEN", pinmux_type_fpmx, 0x07, 0, 7), + FNCN("L2SW_P1_MAC_RMII_TXD0", pinmux_type_fpmx, 0x07, 8, 7), + FNCN("L2SW_P1_MAC_RMII_TXD1", pinmux_type_fpmx, 0x08, 0, 7), + FNCN("L2SW_P1_MAC_RMII_CRSDV", pinmux_type_fpmx, 0x08, 8, 7), + FNCN("L2SW_P1_MAC_RMII_RXD0", pinmux_type_fpmx, 0x09, 0, 7), + FNCN("L2SW_P1_MAC_RMII_RXD1", pinmux_type_fpmx, 0x09, 8, 7), + FNCN("L2SW_P1_MAC_RMII_RXER", pinmux_type_fpmx, 0x0A, 0, 7), + FNCN("DAISY_MODE", pinmux_type_fpmx, 0x0A, 8, 7), + FNCN("SDIO_CLK", pinmux_type_fpmx, 0x0B, 0, 7), /* 1x SDIO */ + FNCN("SDIO_CMD", pinmux_type_fpmx, 0x0B, 8, 7), + FNCN("SDIO_D0", pinmux_type_fpmx, 0x0C, 0, 7), + FNCN("SDIO_D1", pinmux_type_fpmx, 0x0C, 8, 7), + FNCN("SDIO_D2", pinmux_type_fpmx, 0x0D, 0, 7), + FNCN("SDIO_D3", pinmux_type_fpmx, 0x0D, 8, 7), + FNCN("PWM0", pinmux_type_fpmx, 0x0E, 0, 7), /* 8x PWM */ + FNCN("PWM1", pinmux_type_fpmx, 0x0E, 8, 7), + FNCN("PWM2", pinmux_type_fpmx, 0x0F, 0, 7), + FNCN("PWM3", pinmux_type_fpmx, 0x0F, 8, 7), + + FNCN("PWM4", pinmux_type_fpmx, 0x10, 0, 7), + FNCN("PWM5", pinmux_type_fpmx, 0x10, 8, 7), + FNCN("PWM6", pinmux_type_fpmx, 0x11, 0, 7), + FNCN("PWM7", pinmux_type_fpmx, 0x11, 8, 7), + FNCN("ICM0_D", pinmux_type_fpmx, 0x12, 0, 7), /* 4x Input captures */ + FNCN("ICM1_D", pinmux_type_fpmx, 0x12, 8, 7), + FNCN("ICM2_D", pinmux_type_fpmx, 0x13, 0, 7), + FNCN("ICM3_D", pinmux_type_fpmx, 0x13, 8, 7), + FNCN("ICM0_CLK", pinmux_type_fpmx, 0x14, 0, 7), + FNCN("ICM1_CLK", pinmux_type_fpmx, 0x14, 8, 7), + FNCN("ICM2_CLK", pinmux_type_fpmx, 0x15, 0, 7), + FNCN("ICM3_CLK", pinmux_type_fpmx, 0x15, 8, 7), + FNCN("SPIM0_INT", pinmux_type_fpmx, 0x16, 0, 7), /* 4x SPI masters */ + FNCN("SPIM0_CLK", pinmux_type_fpmx, 0x16, 8, 7), + FNCN("SPIM0_EN", pinmux_type_fpmx, 0x17, 0, 7), + FNCN("SPIM0_DO", pinmux_type_fpmx, 0x17, 8, 7), + FNCN("SPIM0_DI", pinmux_type_fpmx, 0x18, 0, 7), + FNCN("SPIM1_INT", pinmux_type_fpmx, 0x18, 8, 7), + FNCN("SPIM1_CLK", pinmux_type_fpmx, 0x19, 0, 7), + FNCN("SPIM1_EN", pinmux_type_fpmx, 0x19, 8, 7), + FNCN("SPIM1_DO", pinmux_type_fpmx, 0x1A, 0, 7), + FNCN("SPIM1_DI", pinmux_type_fpmx, 0x1A, 8, 7), + FNCN("SPIM2_INT", pinmux_type_fpmx, 0x1B, 0, 7), + FNCN("SPIM2_CLK", pinmux_type_fpmx, 0x1B, 8, 7), + FNCN("SPIM2_EN", pinmux_type_fpmx, 0x1C, 0, 7), + FNCN("SPIM2_DO", pinmux_type_fpmx, 0x1C, 8, 7), + FNCN("SPIM2_DI", pinmux_type_fpmx, 0x1D, 0, 7), + FNCN("SPIM3_INT", pinmux_type_fpmx, 0x1D, 8, 7), + FNCN("SPIM3_CLK", pinmux_type_fpmx, 0x1E, 0, 7), + FNCN("SPIM3_EN", pinmux_type_fpmx, 0x1E, 8, 7), + FNCN("SPIM3_DO", pinmux_type_fpmx, 0x1F, 0, 7), + FNCN("SPIM3_DI", pinmux_type_fpmx, 0x1F, 8, 7), + + FNCN("SPI0S_INT", pinmux_type_fpmx, 0x20, 0, 7), /* 4x SPI slaves */ + FNCN("SPI0S_CLK", pinmux_type_fpmx, 0x20, 8, 7), + FNCN("SPI0S_EN", pinmux_type_fpmx, 0x21, 0, 7), + FNCN("SPI0S_DO", pinmux_type_fpmx, 0x21, 8, 7), + FNCN("SPI0S_DI", pinmux_type_fpmx, 0x22, 0, 7), + FNCN("SPI1S_INT", pinmux_type_fpmx, 0x22, 8, 7), + FNCN("SPI1S_CLK", pinmux_type_fpmx, 0x23, 0, 7), + FNCN("SPI1S_EN", pinmux_type_fpmx, 0x23, 8, 7), + FNCN("SPI1S_DO", pinmux_type_fpmx, 0x24, 0, 7), + FNCN("SPI1S_DI", pinmux_type_fpmx, 0x24, 8, 7), + FNCN("SPI2S_INT", pinmux_type_fpmx, 0x25, 0, 7), + FNCN("SPI2S_CLK", pinmux_type_fpmx, 0x25, 8, 7), + FNCN("SPI2S_EN", pinmux_type_fpmx, 0x26, 0, 7), + FNCN("SPI2S_DO", pinmux_type_fpmx, 0x26, 8, 7), + FNCN("SPI2S_DI", pinmux_type_fpmx, 0x27, 0, 7), + FNCN("SPI3S_INT", pinmux_type_fpmx, 0x27, 8, 7), + FNCN("SPI3S_CLK", pinmux_type_fpmx, 0x28, 0, 7), + FNCN("SPI3S_EN", pinmux_type_fpmx, 0x28, 8, 7), + FNCN("SPI3S_DO", pinmux_type_fpmx, 0x29, 0, 7), + FNCN("SPI3S_DI", pinmux_type_fpmx, 0x29, 8, 7), + FNCN("I2CM0_CLK", pinmux_type_fpmx, 0x2A, 0, 7), /* 4x I2C masters */ + FNCN("I2CM0_DAT", pinmux_type_fpmx, 0x2A, 8, 7), + FNCN("I2CM1_CLK", pinmux_type_fpmx, 0x2B, 0, 7), + FNCN("I2CM1_DAT", pinmux_type_fpmx, 0x2B, 8, 7), + FNCN("I2CM2_CLK", pinmux_type_fpmx, 0x2C, 0, 7), + FNCN("I2CM2_DAT", pinmux_type_fpmx, 0x2C, 8, 7), + FNCN("I2CM3_CLK", pinmux_type_fpmx, 0x2D, 0, 7), + FNCN("I2CM3_DAT", pinmux_type_fpmx, 0x2D, 8, 7), + FNCN("UA1_TX", pinmux_type_fpmx, 0x2E, 0, 7), /* 4x UARTS */ + FNCN("UA1_RX", pinmux_type_fpmx, 0x2E, 8, 7), + FNCN("UA1_CTS", pinmux_type_fpmx, 0x2F, 0, 7), + FNCN("UA1_RTS", pinmux_type_fpmx, 0x2F, 8, 7), + + FNCN("UA2_TX", pinmux_type_fpmx, 0x30, 0, 7), + FNCN("UA2_RX", pinmux_type_fpmx, 0x30, 8, 7), + FNCN("UA2_CTS", pinmux_type_fpmx, 0x31, 0, 7), + FNCN("UA2_RTS", pinmux_type_fpmx, 0x31, 8, 7), + FNCN("UA3_TX", pinmux_type_fpmx, 0x32, 0, 7), + FNCN("UA3_RX", pinmux_type_fpmx, 0x32, 8, 7), + FNCN("UA3_CTS", pinmux_type_fpmx, 0x33, 0, 7), + FNCN("UA3_RTS", pinmux_type_fpmx, 0x33, 8, 7), + FNCN("UA4_TX", pinmux_type_fpmx, 0x34, 0, 7), + FNCN("UA4_RX", pinmux_type_fpmx, 0x34, 8, 7), + FNCN("UA4_CTS", pinmux_type_fpmx, 0x35, 0, 7), + FNCN("UA4_RTS", pinmux_type_fpmx, 0x35, 8, 7), + FNCN("TIMER0_INT", pinmux_type_fpmx, 0x36, 0, 7), /* 4x timer int. */ + FNCN("TIMER1_INT", pinmux_type_fpmx, 0x36, 8, 7), + FNCN("TIMER2_INT", pinmux_type_fpmx, 0x37, 0, 7), + FNCN("TIMER3_INT", pinmux_type_fpmx, 0x37, 8, 7), + FNCN("GPIO_INT0", pinmux_type_fpmx, 0x38, 0, 7), /* 8x GPIO int. */ + FNCN("GPIO_INT1", pinmux_type_fpmx, 0x38, 8, 7), + FNCN("GPIO_INT2", pinmux_type_fpmx, 0x39, 0, 7), + FNCN("GPIO_INT3", pinmux_type_fpmx, 0x39, 8, 7), + FNCN("GPIO_INT4", pinmux_type_fpmx, 0x3A, 0, 7), + FNCN("GPIO_INT5", pinmux_type_fpmx, 0x3A, 8, 7), + FNCN("GPIO_INT6", pinmux_type_fpmx, 0x3B, 0, 7), + FNCN("GPIO_INT7", pinmux_type_fpmx, 0x3B, 8, 7), + + /* MOON1 register */ + FNCE("SPI_FLASH", pinmux_type_grp, 0x01, 0, 2, sp7021grps_spif), + FNCE("SPI_FLASH_4BIT", pinmux_type_grp, 0x01, 2, 2, sp7021grps_spi4), + FNCE("SPI_NAND", pinmux_type_grp, 0x01, 4, 1, sp7021grps_snan), + FNCE("CARD0_EMMC", pinmux_type_grp, 0x01, 5, 1, sp7021grps_emmc), + FNCE("SD_CARD", pinmux_type_grp, 0x01, 6, 1, sp7021grps_sdsd), + FNCE("UA0", pinmux_type_grp, 0x01, 7, 1, sp7021grps_uar0), + FNCE("ACHIP_DEBUG", pinmux_type_grp, 0x01, 8, 2, sp7021grps_adbg), + FNCE("ACHIP_UA2AXI", pinmux_type_grp, 0x01, 10, 2, sp7021grps_au2x), + FNCE("FPGA_IFX", pinmux_type_grp, 0x01, 12, 1, sp7021grps_fpga), + FNCE("HDMI_TX", pinmux_type_grp, 0x01, 13, 2, sp7021grps_hdmi), + + FNCE("AUD_EXT_ADC_IFX0", pinmux_type_grp, 0x01, 15, 1, sp7021grps_eadc), + FNCE("AUD_EXT_DAC_IFX0", pinmux_type_grp, 0x02, 0, 1, sp7021grps_edac), + FNCE("SPDIF_RX", pinmux_type_grp, 0x02, 2, 1, sp7021grps_spdi), + FNCE("SPDIF_TX", pinmux_type_grp, 0x02, 3, 1, sp7021grps_spdo), + FNCE("TDMTX_IFX0", pinmux_type_grp, 0x02, 4, 1, sp7021grps_tdmt), + FNCE("TDMRX_IFX0", pinmux_type_grp, 0x02, 5, 1, sp7021grps_tdmr), + FNCE("PDMRX_IFX0", pinmux_type_grp, 0x02, 6, 1, sp7021grps_pdmr), + FNCE("PCM_IEC_TX", pinmux_type_grp, 0x02, 7, 1, sp7021grps_pcmt), + FNCE("LCDIF", pinmux_type_grp, 0x04, 6, 1, sp7021grps_lcdi), + FNCE("DVD_DSP_DEBUG", pinmux_type_grp, 0x02, 8, 1, sp7021grps_dvdd), + FNCE("I2C_DEBUG", pinmux_type_grp, 0x02, 9, 1, sp7021grps_i2cd), + FNCE("I2C_SLAVE", pinmux_type_grp, 0x02, 10, 1, sp7021grps_i2cs), + FNCE("WAKEUP", pinmux_type_grp, 0x02, 11, 1, sp7021grps_wakp), + FNCE("UART2AXI", pinmux_type_grp, 0x02, 12, 2, sp7021grps_u2ax), + FNCE("USB0_I2C", pinmux_type_grp, 0x02, 14, 2, sp7021grps_u0ic), + FNCE("USB1_I2C", pinmux_type_grp, 0x03, 0, 2, sp7021grps_u1ic), + FNCE("USB0_OTG", pinmux_type_grp, 0x03, 2, 1, sp7021grps_u0ot), + FNCE("USB1_OTG", pinmux_type_grp, 0x03, 3, 1, sp7021grps_u1ot), + FNCE("UPHY0_DEBUG", pinmux_type_grp, 0x03, 4, 1, sp7021grps_up0d), + FNCE("UPHY1_DEBUG", pinmux_type_grp, 0x03, 5, 1, sp7021grps_up1d), + FNCE("UPHY0_EXT", pinmux_type_grp, 0x03, 6, 1, sp7021grps_upex), + FNCE("PROBE_PORT", pinmux_type_grp, 0x03, 7, 2, sp7021grps_prbp), +}; + +const size_t sppctl_list_funcs_sz = ARRAY_SIZE(sppctl_list_funcs); diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 1f401377ff60..d9327d7d56ee 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -784,11 +784,10 @@ static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset) snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank); reg = regulator_get(pctl->dev, supply); - if (IS_ERR(reg)) { - dev_err(pctl->dev, "Couldn't get bank P%c regulator\n", - 'A' + bank); - return PTR_ERR(reg); - } + if (IS_ERR(reg)) + return dev_err_probe(pctl->dev, PTR_ERR(reg), + "Couldn't get bank P%c regulator\n", + 'A' + bank); ret = regulator_enable(reg); if (ret) { diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c index a4fa8e3af607..65ed20bc1fa2 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c @@ -461,10 +461,18 @@ static const struct pinctrl_pin_desc uniphier_ld11_pins[] = { 166, UNIPHIER_PIN_PULL_DOWN), }; -static const unsigned ain1_pins[] = {151, 152, 153, 154, 155, 156, 157}; -static const int ain1_muxvals[] = {4, 4, 4, 4, 4, 4, 4}; -static const unsigned aout1_pins[] = {137, 138, 139, 140, 141, 142}; -static const int aout1_muxvals[] = {0, 0, 0, 0, 0, 0}; +static const unsigned ain1_pins[] = {151, 152, 153, 154}; +static const int ain1_muxvals[] = {4, 4, 4, 4}; +static const unsigned ain1_dat2_pins[] = {155}; +static const int ain1_dat2_muxvals[] = {4}; +static const unsigned ain1_dat4_pins[] = {156, 157}; +static const int ain1_dat4_muxvals[] = {4, 4}; +static const unsigned aout1_pins[] = {137, 138, 139, 140}; +static const int aout1_muxvals[] = {0, 0, 0, 0}; +static const unsigned aout1_dat2_pins[] = {141}; +static const int aout1_dat2_muxvals[] = {0}; +static const unsigned aout1_dat4_pins[] = {142, 143}; +static const int aout1_dat4_muxvals[] = {0, 3}; static const unsigned ainiec1_pins[] = {150}; static const int ainiec1_muxvals[] = {4}; static const unsigned ainiec1b_pins[] = {141}; @@ -582,7 +590,11 @@ static const unsigned int gpio_range5_pins[] = { static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = { UNIPHIER_PINCTRL_GROUP(ain1), + UNIPHIER_PINCTRL_GROUP(ain1_dat2), + UNIPHIER_PINCTRL_GROUP(ain1_dat4), UNIPHIER_PINCTRL_GROUP(aout1), + UNIPHIER_PINCTRL_GROUP(aout1_dat2), + UNIPHIER_PINCTRL_GROUP(aout1_dat4), UNIPHIER_PINCTRL_GROUP(ainiec1), UNIPHIER_PINCTRL_GROUP(ainiec1b), UNIPHIER_PINCTRL_GROUP(aoutiec1), @@ -626,8 +638,10 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = { UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range5), }; -static const char * const ain1_groups[] = {"ain1"}; -static const char * const aout1_groups[] = {"aout1"}; +static const char * const ain1_groups[] = {"ain1", "ain1_dat2", + "ain1_dat4"}; +static const char * const aout1_groups[] = {"aout1", "aout1_dat2", + "aout1_dat4"}; static const char * const ainiec1_groups[] = {"ainiec1", "ainiec1b"}; static const char * const aoutiec1_groups[] = {"aoutiec1"}; static const char * const aoutiec2_groups[] = {"aoutiec2"}; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c index 850736998206..a68b21fbd0c7 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c @@ -542,18 +542,38 @@ static const struct pinctrl_pin_desc uniphier_ld20_pins[] = { 175, UNIPHIER_PIN_PULL_DOWN), }; -static const unsigned ain1_pins[] = {150, 151, 152, 153, 154, 155, 156}; -static const int ain1_muxvals[] = {4, 4, 4, 4, 4, 4, 4}; -static const unsigned ain2_pins[] = {116, 117, 118, 119, 120, 121, 122}; -static const int ain2_muxvals[] = {26, 26, 26, 26, 26, 26, 26}; +static const unsigned ain1_pins[] = {150, 151, 152, 153}; +static const int ain1_muxvals[] = {4, 4, 4, 4}; +static const unsigned ain1_dat2_pins[] = {154}; +static const int ain1_dat2_muxvals[] = {4}; +static const unsigned ain1_dat4_pins[] = {155, 156}; +static const int ain1_dat4_muxvals[] = {4, 4}; +static const unsigned ain2_pins[] = {116, 117, 118, 119}; +static const int ain2_muxvals[] = {26, 26, 26, 26}; +static const unsigned ain2_dat2_pins[] = {120}; +static const int ain2_dat2_muxvals[] = {26}; +static const unsigned ain2_dat4_pins[] = {121, 122}; +static const int ain2_dat4_muxvals[] = {26, 26}; static const unsigned ain3_pins[] = {116, 117, 118, 119}; static const int ain3_muxvals[] = {27, 27, 27, 27}; -static const unsigned aout1_pins[] = {137, 138, 139, 140, 141, 142}; -static const int aout1_muxvals[] = {0, 0, 0, 0, 0, 0}; -static const unsigned aout1b_pins[] = {150, 151, 152, 153, 154, 155, 156}; -static const int aout1b_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; -static const unsigned aout2_pins[] = {165, 157, 162, 158, 159, 160, 161}; -static const int aout2_muxvals[] = {2, 2, 2, 1, 1, 1, 1}; +static const unsigned aout1_pins[] = {137, 138, 139, 140}; +static const int aout1_muxvals[] = {0, 0, 0, 0}; +static const unsigned aout1_dat2_pins[] = {141}; +static const int aout1_dat2_muxvals[] = {0}; +static const unsigned aout1_dat4_pins[] = {142, 156}; +static const int aout1_dat4_muxvals[] = {0, 1}; +static const unsigned aout1b_pins[] = {150, 151, 152, 153}; +static const int aout1b_muxvals[] = {1, 1, 1, 1}; +static const unsigned aout1b_dat2_pins[] = {154}; +static const int aout1b_dat2_muxvals[] = {1}; +static const unsigned aout1b_dat4_pins[] = {155, 156}; +static const int aout1b_dat4_muxvals[] = {1, 1}; +static const unsigned aout2_pins[] = {165, 157, 162, 158}; +static const int aout2_muxvals[] = {2, 2, 2, 1}; +static const unsigned aout2_dat2_pins[] = {159}; +static const int aout2_dat2_muxvals[] = {1}; +static const unsigned aout2_dat4_pins[] = {160, 161}; +static const int aout2_dat4_muxvals[] = {1, 1}; static const unsigned aout3_pins[] = {166, 167, 168, 163}; static const int aout3_muxvals[] = {2, 2, 2, 1}; static const unsigned aout4_pins[] = {169, 170, 171, 164}; @@ -682,11 +702,21 @@ static const unsigned int gpio_range2_pins[] = { static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = { UNIPHIER_PINCTRL_GROUP(ain1), + UNIPHIER_PINCTRL_GROUP(ain1_dat2), + UNIPHIER_PINCTRL_GROUP(ain1_dat4), UNIPHIER_PINCTRL_GROUP(ain2), + UNIPHIER_PINCTRL_GROUP(ain2_dat2), + UNIPHIER_PINCTRL_GROUP(ain2_dat4), UNIPHIER_PINCTRL_GROUP(ain3), UNIPHIER_PINCTRL_GROUP(aout1), + UNIPHIER_PINCTRL_GROUP(aout1_dat2), + UNIPHIER_PINCTRL_GROUP(aout1_dat4), UNIPHIER_PINCTRL_GROUP(aout1b), + UNIPHIER_PINCTRL_GROUP(aout1b_dat2), + UNIPHIER_PINCTRL_GROUP(aout1b_dat4), UNIPHIER_PINCTRL_GROUP(aout2), + UNIPHIER_PINCTRL_GROUP(aout2_dat2), + UNIPHIER_PINCTRL_GROUP(aout2_dat4), UNIPHIER_PINCTRL_GROUP(aout3), UNIPHIER_PINCTRL_GROUP(aout4), UNIPHIER_PINCTRL_GROUP(aoutiec1), @@ -734,11 +764,17 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = { UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2), }; -static const char * const ain1_groups[] = {"ain1"}; -static const char * const ain2_groups[] = {"ain2"}; +static const char * const ain1_groups[] = {"ain1", "ain1_dat2", + "ain1_dat4"}; +static const char * const ain2_groups[] = {"ain2", "ain2_dat2", + "ain2_dat4"}; static const char * const ain3_groups[] = {"ain3"}; -static const char * const aout1_groups[] = {"aout1", "aout1b"}; -static const char * const aout2_groups[] = {"aout2"}; +static const char * const aout1_groups[] = {"aout1", "aout1_dat2", + "aout1_dat4", + "aout1b", "aout1b_dat2", + "aout1b_dat4"}; +static const char * const aout2_groups[] = {"aout2", "aout2_dat2", + "aout2_dat4"}; static const char * const aout3_groups[] = {"aout3"}; static const char * const aout4_groups[] = {"aout4"}; static const char * const aoutiec1_groups[] = {"aoutiec1"}; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c index e52e65a24048..2a9dbf969f0b 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c @@ -721,12 +721,32 @@ static const struct pinctrl_pin_desc uniphier_pxs2_pins[] = { static const unsigned ain1_pins[] = {161, 162, 173, 174}; static const int ain1_muxvals[] = {8, 8, 8, 8}; -static const unsigned ain2_pins[] = {98, 99, 100, 101, 102, 103, 104}; -static const int ain2_muxvals[] = {8, 8, 8, 8, 8, 8, 8}; +static const unsigned ain1_dat2_pins[] = {127}; +static const int ain1_dat2_muxvals[] = {3}; +static const unsigned ain1_dat4_pins[] = {128, 129}; +static const int ain1_dat4_muxvals[] = {3, 3}; +static const unsigned ain2_pins[] = {98, 99, 100, 101}; +static const int ain2_muxvals[] = {8, 8, 8, 8}; +static const unsigned ain2_dat2_pins[] = {102}; +static const int ain2_dat2_muxvals[] = {8}; +static const unsigned ain2_dat4_pins[] = {103, 104}; +static const int ain2_dat4_muxvals[] = {8, 8}; +static const unsigned ain3_pins[] = {132, 133, 134, 131}; +static const int ain3_muxvals[] = {5, 5, 5, 5}; static const unsigned ainiec1_pins[] = {91}; static const int ainiec1_muxvals[] = {11}; -static const unsigned aout2_pins[] = {175, 176, 177, 178, 183, 184, 185}; -static const int aout2_muxvals[] = {8, 8, 8, 8, 9, 9, 9}; +static const unsigned aout1_pins[] = {87, 88, 89, 90}; +static const int aout1_muxvals[] = {11, 11, 11, 11}; +static const unsigned aout1_dat2_pins[] = {92}; +static const int aout1_dat2_muxvals[] = {11}; +static const unsigned aout1_dat4_pins[] = {93, 94}; +static const int aout1_dat4_muxvals[] = {11, 11}; +static const unsigned aout2_pins[] = {177, 178, 175, 176}; +static const int aout2_muxvals[] = {8, 8, 8, 8}; +static const unsigned aout2_dat2_pins[] = {183}; +static const int aout2_dat2_muxvals[] = {9}; +static const unsigned aout2_dat4_pins[] = {184, 185}; +static const int aout2_dat4_muxvals[] = {9, 9}; static const unsigned aout3_pins[] = {105, 106, 107, 108}; static const int aout3_muxvals[] = {8, 8, 8, 8}; static const unsigned aoutiec1_pins[] = {95}; @@ -797,8 +817,12 @@ static const unsigned uart3b_pins[] = {181, 182}; static const int uart3b_muxvals[] = {10, 10}; static const unsigned usb0_pins[] = {56, 57}; static const int usb0_muxvals[] = {8, 8}; +static const unsigned usb0_device_pins[] = {213}; +static const int usb0_device_muxvals[] = {9}; static const unsigned usb1_pins[] = {58, 59}; static const int usb1_muxvals[] = {8, 8}; +static const unsigned usb1_device_pins[] = {214}; +static const int usb1_device_muxvals[] = {9}; static const unsigned usb2_pins[] = {60, 61}; static const int usb2_muxvals[] = {8, 8}; static const unsigned usb3_pins[] = {62, 63}; @@ -838,9 +862,19 @@ static const unsigned int gpio_range1_pins[] = { static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = { UNIPHIER_PINCTRL_GROUP(ain1), + UNIPHIER_PINCTRL_GROUP(ain1_dat2), + UNIPHIER_PINCTRL_GROUP(ain1_dat4), UNIPHIER_PINCTRL_GROUP(ain2), + UNIPHIER_PINCTRL_GROUP(ain2_dat2), + UNIPHIER_PINCTRL_GROUP(ain2_dat4), + UNIPHIER_PINCTRL_GROUP(ain3), UNIPHIER_PINCTRL_GROUP(ainiec1), + UNIPHIER_PINCTRL_GROUP(aout1), + UNIPHIER_PINCTRL_GROUP(aout1_dat2), + UNIPHIER_PINCTRL_GROUP(aout1_dat4), UNIPHIER_PINCTRL_GROUP(aout2), + UNIPHIER_PINCTRL_GROUP(aout2_dat2), + UNIPHIER_PINCTRL_GROUP(aout2_dat4), UNIPHIER_PINCTRL_GROUP(aout3), UNIPHIER_PINCTRL_GROUP(aoutiec1), UNIPHIER_PINCTRL_GROUP(aoutiec2), @@ -871,17 +905,25 @@ static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = { UNIPHIER_PINCTRL_GROUP(uart3), UNIPHIER_PINCTRL_GROUP(uart3b), UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb0_device), UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb1_device), UNIPHIER_PINCTRL_GROUP(usb2), UNIPHIER_PINCTRL_GROUP(usb3), UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range0), UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range1), }; -static const char * const ain1_groups[] = {"ain1"}; -static const char * const ain2_groups[] = {"ain2"}; +static const char * const ain1_groups[] = {"ain1", "ain1_dat2", + "ain1_dat4"}; +static const char * const ain2_groups[] = {"ain2", "ain2_dat2", + "ain2_dat4"}; +static const char * const ain3_groups[] = {"ain3"}; static const char * const ainiec1_groups[] = {"ainiec1"}; -static const char * const aout2_groups[] = {"aout2"}; +static const char * const aout1_groups[] = {"aout1", "aout1_dat2", + "aout1_dat4"}; +static const char * const aout2_groups[] = {"aout2", "aout2_dat2", + "aout2_dat4"}; static const char * const aout3_groups[] = {"aout3"}; static const char * const aoutiec1_groups[] = {"aoutiec1"}; static const char * const aoutiec2_groups[] = {"aoutiec2"}; @@ -906,15 +948,17 @@ static const char * const uart0_groups[] = {"uart0", "uart0b", static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; static const char * const uart3_groups[] = {"uart3", "uart3b"}; -static const char * const usb0_groups[] = {"usb0"}; -static const char * const usb1_groups[] = {"usb1"}; +static const char * const usb0_groups[] = {"usb0", "usb0_device"}; +static const char * const usb1_groups[] = {"usb1", "usb1_device"}; static const char * const usb2_groups[] = {"usb2"}; static const char * const usb3_groups[] = {"usb3"}; static const struct uniphier_pinmux_function uniphier_pxs2_functions[] = { UNIPHIER_PINMUX_FUNCTION(ain1), UNIPHIER_PINMUX_FUNCTION(ain2), + UNIPHIER_PINMUX_FUNCTION(ain3), UNIPHIER_PINMUX_FUNCTION(ainiec1), + UNIPHIER_PINMUX_FUNCTION(aout1), UNIPHIER_PINMUX_FUNCTION(aout2), UNIPHIER_PINMUX_FUNCTION(aout3), UNIPHIER_PINMUX_FUNCTION(aoutiec1), diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c index 4810db6c0ee8..ab3bd2d9c6c7 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c @@ -767,14 +767,30 @@ static const struct pinctrl_pin_desc uniphier_pxs3_pins[] = { 250, UNIPHIER_PIN_PULL_DOWN), }; -static const unsigned ain1_pins[] = {186, 187, 188, 189, 237, 238, 239}; -static const int ain1_muxvals[] = {0, 0, 0, 0, 1, 1, 1}; -static const unsigned ain2_pins[] = {243, 244, 245, 246, 247, 248, 249}; -static const int ain2_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; -static const unsigned aout1_pins[] = {226, 227, 228, 229, 230, 231, 232}; -static const int aout1_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; -static const unsigned aout2_pins[] = {192, 193, 194, 195, 196, 197, 198}; -static const int aout2_muxvals[] = {0, 0, 0, 0, 0, 0, 0}; +static const unsigned ain1_pins[] = {186, 187, 188, 189}; +static const int ain1_muxvals[] = {0, 0, 0, 0}; +static const unsigned ain1_dat2_pins[] = {237}; +static const int ain1_dat2_muxvals[] = {1}; +static const unsigned ain1_dat4_pins[] = {238, 239}; +static const int ain1_dat4_muxvals[] = {1, 1}; +static const unsigned ain2_pins[] = {243, 244, 245, 246}; +static const int ain2_muxvals[] = {1, 1, 1, 1}; +static const unsigned ain2_dat2_pins[] = {247}; +static const int ain2_dat2_muxvals[] = {1}; +static const unsigned ain2_dat4_pins[] = {248, 249}; +static const int ain2_dat4_muxvals[] = {1, 1}; +static const unsigned aout1_pins[] = {226, 227, 228, 229}; +static const int aout1_muxvals[] = {1, 1, 1, 1}; +static const unsigned aout1_dat2_pins[] = {230}; +static const int aout1_dat2_muxvals[] = {1}; +static const unsigned aout1_dat4_pins[] = {231, 232}; +static const int aout1_dat4_muxvals[] = {1, 1}; +static const unsigned aout2_pins[] = {192, 193, 194, 195}; +static const int aout2_muxvals[] = {0, 0, 0, 0}; +static const unsigned aout2_dat2_pins[] = {196}; +static const int aout2_dat2_muxvals[] = {0}; +static const unsigned aout2_dat4_pins[] = {197, 198}; +static const int aout2_dat4_muxvals[] = {0, 0}; static const unsigned aout3_pins[] = {199, 200, 201, 202}; static const int aout3_muxvals[] = {0, 0, 0, 0}; static const unsigned ainiec1_pins[] = {240}; @@ -839,8 +855,12 @@ static const unsigned int uart3_pins[] = {98, 99}; static const int uart3_muxvals[] = {0, 0}; static const unsigned int usb0_pins[] = {84, 85}; static const int usb0_muxvals[] = {0, 0}; +static const unsigned int usb0_device_pins[] = {110}; +static const int usb0_device_muxvals[] = {2}; static const unsigned int usb1_pins[] = {86, 87}; static const int usb1_muxvals[] = {0, 0}; +static const unsigned int usb1_device_pins[] = {111}; +static const int usb1_device_muxvals[] = {2}; static const unsigned int usb2_pins[] = {88, 89}; static const int usb2_muxvals[] = {0, 0}; static const unsigned int usb3_pins[] = {90, 91}; @@ -888,9 +908,17 @@ static const unsigned int gpio_range2_pins[] = { static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = { UNIPHIER_PINCTRL_GROUP(ain1), + UNIPHIER_PINCTRL_GROUP(ain1_dat2), + UNIPHIER_PINCTRL_GROUP(ain1_dat4), UNIPHIER_PINCTRL_GROUP(ain2), + UNIPHIER_PINCTRL_GROUP(ain2_dat2), + UNIPHIER_PINCTRL_GROUP(ain2_dat4), UNIPHIER_PINCTRL_GROUP(aout1), + UNIPHIER_PINCTRL_GROUP(aout1_dat2), + UNIPHIER_PINCTRL_GROUP(aout1_dat4), UNIPHIER_PINCTRL_GROUP(aout2), + UNIPHIER_PINCTRL_GROUP(aout2_dat2), + UNIPHIER_PINCTRL_GROUP(aout2_dat4), UNIPHIER_PINCTRL_GROUP(aout3), UNIPHIER_PINCTRL_GROUP(ainiec1), UNIPHIER_PINCTRL_GROUP(aoutiec1), @@ -918,7 +946,9 @@ static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = { UNIPHIER_PINCTRL_GROUP(uart2), UNIPHIER_PINCTRL_GROUP(uart3), UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb0_device), UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb1_device), UNIPHIER_PINCTRL_GROUP(usb2), UNIPHIER_PINCTRL_GROUP(usb3), UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range0), @@ -926,10 +956,14 @@ static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = { UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2), }; -static const char * const ain1_groups[] = {"ain1"}; -static const char * const ain2_groups[] = {"ain2"}; -static const char * const aout1_groups[] = {"aout1"}; -static const char * const aout2_groups[] = {"aout2"}; +static const char * const ain1_groups[] = {"ain1", "ain1_dat2", + "ain1_dat4"}; +static const char * const ain2_groups[] = {"ain2", "ain2_dat2", + "ain1_dat4"}; +static const char * const aout1_groups[] = {"aout1", "aout1_dat2", + "aout1_dat4"}; +static const char * const aout2_groups[] = {"aout2", "aout2_dat2", + "aout2_dat4"}; static const char * const aout3_groups[] = {"aout3"}; static const char * const ainiec1_groups[] = {"ainiec1"}; static const char * const aoutiec1_groups[] = {"aoutiec1"}; @@ -954,8 +988,8 @@ static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts", static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; static const char * const uart3_groups[] = {"uart3"}; -static const char * const usb0_groups[] = {"usb0"}; -static const char * const usb1_groups[] = {"usb1"}; +static const char * const usb0_groups[] = {"usb0", "usb0_device"}; +static const char * const usb1_groups[] = {"usb1", "usb1_device"}; static const char * const usb2_groups[] = {"usb2"}; static const char * const usb3_groups[] = {"usb3"}; diff --git a/include/dt-bindings/gpio/meson-s4-gpio.h b/include/dt-bindings/gpio/meson-s4-gpio.h new file mode 100644 index 000000000000..35aee21b94f1 --- /dev/null +++ b/include/dt-bindings/gpio/meson-s4-gpio.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + * Author: Qianggui Song <qianggui.song@amlogic.com> + */ + +#ifndef _DT_BINDINGS_MESON_S4_GPIO_H +#define _DT_BINDINGS_MESON_S4_GPIO_H + +#define GPIOB_0 0 +#define GPIOB_1 1 +#define GPIOB_2 2 +#define GPIOB_3 3 +#define GPIOB_4 4 +#define GPIOB_5 5 +#define GPIOB_6 6 +#define GPIOB_7 7 +#define GPIOB_8 8 +#define GPIOB_9 9 +#define GPIOB_10 10 +#define GPIOB_11 11 +#define GPIOB_12 12 +#define GPIOB_13 13 + +#define GPIOC_0 14 +#define GPIOC_1 15 +#define GPIOC_2 16 +#define GPIOC_3 17 +#define GPIOC_4 18 +#define GPIOC_5 19 +#define GPIOC_6 20 +#define GPIOC_7 21 + +#define GPIOE_0 22 +#define GPIOE_1 23 + +#define GPIOD_0 24 +#define GPIOD_1 25 +#define GPIOD_2 26 +#define GPIOD_3 27 +#define GPIOD_4 28 +#define GPIOD_5 29 +#define GPIOD_6 30 +#define GPIOD_7 31 +#define GPIOD_8 32 +#define GPIOD_9 33 +#define GPIOD_10 34 +#define GPIOD_11 35 + +#define GPIOH_0 36 +#define GPIOH_1 37 +#define GPIOH_2 38 +#define GPIOH_3 39 +#define GPIOH_4 40 +#define GPIOH_5 41 +#define GPIOH_6 42 +#define GPIOH_7 43 +#define GPIOH_8 44 +#define GPIOH_9 45 +#define GPIOH_10 46 +#define GPIOH_11 47 + +#define GPIOX_0 48 +#define GPIOX_1 49 +#define GPIOX_2 50 +#define GPIOX_3 51 +#define GPIOX_4 52 +#define GPIOX_5 53 +#define GPIOX_6 54 +#define GPIOX_7 55 +#define GPIOX_8 56 +#define GPIOX_9 57 +#define GPIOX_10 58 +#define GPIOX_11 59 +#define GPIOX_12 60 +#define GPIOX_13 61 +#define GPIOX_14 62 +#define GPIOX_15 63 +#define GPIOX_16 64 +#define GPIOX_17 65 +#define GPIOX_18 66 +#define GPIOX_19 67 + +#define GPIOZ_0 68 +#define GPIOZ_1 69 +#define GPIOZ_2 70 +#define GPIOZ_3 71 +#define GPIOZ_4 72 +#define GPIOZ_5 73 +#define GPIOZ_6 74 +#define GPIOZ_7 75 +#define GPIOZ_8 76 +#define GPIOZ_9 77 +#define GPIOZ_10 78 +#define GPIOZ_11 79 +#define GPIOZ_12 80 + +#define GPIO_TEST_N 81 +#endif /* _DT_BINDINGS_MESON_S4_GPIO_H */ diff --git a/include/dt-bindings/pinctrl/mt8186-pinfunc.h b/include/dt-bindings/pinctrl/mt8186-pinfunc.h new file mode 100644 index 000000000000..18d6683c6f65 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt8186-pinfunc.h @@ -0,0 +1,1174 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Guodong Liu <Guodong.Liu@mediatek.com> + * + */ + +#ifndef __MT8186_PINFUNC_H +#define __MT8186_PINFUNC_H + +#include "mt65xx.h" + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_I2S0_MCK (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_SPI0_CLK_B (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_I2S2_MCK (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_CMFLASH0 (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_SCP_SPI0_CK (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 6) +#define PINMUX_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_I2S0_BCK (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_SPI0_CSB_B (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_I2S2_BCK (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_CMFLASH1 (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_SCP_SPI0_CS (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 6) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_I2S0_LRCK (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_SPI0_MO_B (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_I2S2_LRCK (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_CMFLASH2 (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_SCP_SPI0_MO (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 6) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_I2S0_DI (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_SPI0_MI_B (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_I2S2_DI (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_SRCLKENAI1 (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_SCP_SPI0_MI (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 6) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_I2S3_DO (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_I2S1_DO (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_I2S3_MCK (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_SPI1_CLK_B (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_I2S1_MCK (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_DPI_DATA22 (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_I2S3_BCK (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_SPI1_CSB_B (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_I2S1_BCK (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_DPI_DATA23 (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_I2S3_LRCK (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_SPI1_MO_B (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_I2S1_LRCK (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_CONN_UART0_RXD (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_SSPM_URXD_AO (MTK_PIN_NO(8) | 5) +#define PINMUX_GPIO8__FUNC_ADSP_UART_RX (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_I2S3_DO (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_SPI1_MI_B (MTK_PIN_NO(9) | 2) +#define PINMUX_GPIO9__FUNC_I2S1_DO (MTK_PIN_NO(9) | 3) +#define PINMUX_GPIO9__FUNC_CONN_UART0_TXD (MTK_PIN_NO(9) | 4) +#define PINMUX_GPIO9__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(9) | 5) +#define PINMUX_GPIO9__FUNC_ADSP_UART_TX (MTK_PIN_NO(9) | 6) +#define PINMUX_GPIO9__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(9) | 7) + +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_I2S0_MCK (MTK_PIN_NO(10) | 1) +#define PINMUX_GPIO10__FUNC_SPI4_CLK_A (MTK_PIN_NO(10) | 2) +#define PINMUX_GPIO10__FUNC_I2S2_MCK (MTK_PIN_NO(10) | 3) +#define PINMUX_GPIO10__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(10) | 4) +#define PINMUX_GPIO10__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(10) | 5) +#define PINMUX_GPIO10__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(10) | 6) +#define PINMUX_GPIO10__FUNC_CONN_MCU_TDI (MTK_PIN_NO(10) | 7) + +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_I2S0_BCK (MTK_PIN_NO(11) | 1) +#define PINMUX_GPIO11__FUNC_SPI4_CSB_A (MTK_PIN_NO(11) | 2) +#define PINMUX_GPIO11__FUNC_I2S2_BCK (MTK_PIN_NO(11) | 3) +#define PINMUX_GPIO11__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(11) | 4) +#define PINMUX_GPIO11__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(11) | 5) +#define PINMUX_GPIO11__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(11) | 6) +#define PINMUX_GPIO11__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(11) | 7) + +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_I2S0_LRCK (MTK_PIN_NO(12) | 1) +#define PINMUX_GPIO12__FUNC_SPI4_MO_A (MTK_PIN_NO(12) | 2) +#define PINMUX_GPIO12__FUNC_I2S2_LRCK (MTK_PIN_NO(12) | 3) +#define PINMUX_GPIO12__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(12) | 4) +#define PINMUX_GPIO12__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(12) | 5) +#define PINMUX_GPIO12__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(12) | 6) +#define PINMUX_GPIO12__FUNC_CONN_MCU_TCK (MTK_PIN_NO(12) | 7) + +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_I2S0_DI (MTK_PIN_NO(13) | 1) +#define PINMUX_GPIO13__FUNC_SPI4_MI_A (MTK_PIN_NO(13) | 2) +#define PINMUX_GPIO13__FUNC_I2S2_DI (MTK_PIN_NO(13) | 3) +#define PINMUX_GPIO13__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(13) | 4) +#define PINMUX_GPIO13__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(13) | 5) +#define PINMUX_GPIO13__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(13) | 6) +#define PINMUX_GPIO13__FUNC_CONN_MCU_TDO (MTK_PIN_NO(13) | 7) + +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_CLKM0 (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(14) | 4) +#define PINMUX_GPIO14__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(14) | 5) +#define PINMUX_GPIO14__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(14) | 6) +#define PINMUX_GPIO14__FUNC_CONN_MCU_TMS (MTK_PIN_NO(14) | 7) + +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(15) | 1) +#define PINMUX_GPIO15__FUNC_SRCLKENAI1 (MTK_PIN_NO(15) | 2) +#define PINMUX_GPIO15__FUNC_CLKM1 (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_PWM0 (MTK_PIN_NO(15) | 4) + +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_SRCLKENAI0 (MTK_PIN_NO(16) | 2) +#define PINMUX_GPIO16__FUNC_CLKM2 (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_PWM1 (MTK_PIN_NO(16) | 4) + +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_CLKM3 (MTK_PIN_NO(17) | 3) +#define PINMUX_GPIO17__FUNC_PWM2 (MTK_PIN_NO(17) | 4) +#define PINMUX_GPIO17__FUNC_DBG_MON_A32 (MTK_PIN_NO(17) | 7) + +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_CMVREF0 (MTK_PIN_NO(18) | 2) +#define PINMUX_GPIO18__FUNC_SPI2_CLK_B (MTK_PIN_NO(18) | 6) +#define PINMUX_GPIO18__FUNC_DBG_MON_A26 (MTK_PIN_NO(18) | 7) + +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_CMVREF1 (MTK_PIN_NO(19) | 2) +#define PINMUX_GPIO19__FUNC_ANT_SEL3 (MTK_PIN_NO(19) | 5) +#define PINMUX_GPIO19__FUNC_SPI2_CSB_B (MTK_PIN_NO(19) | 6) +#define PINMUX_GPIO19__FUNC_DBG_MON_A2 (MTK_PIN_NO(19) | 7) + +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_CMVREF2 (MTK_PIN_NO(20) | 2) +#define PINMUX_GPIO20__FUNC_ANT_SEL4 (MTK_PIN_NO(20) | 5) +#define PINMUX_GPIO20__FUNC_SPI2_MO_B (MTK_PIN_NO(20) | 6) +#define PINMUX_GPIO20__FUNC_DBG_MON_A3 (MTK_PIN_NO(20) | 7) + +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_I2S0_MCK (MTK_PIN_NO(21) | 1) +#define PINMUX_GPIO21__FUNC_I2S1_MCK (MTK_PIN_NO(21) | 2) +#define PINMUX_GPIO21__FUNC_I2S3_MCK (MTK_PIN_NO(21) | 3) +#define PINMUX_GPIO21__FUNC_ANT_SEL5 (MTK_PIN_NO(21) | 5) +#define PINMUX_GPIO21__FUNC_SPI2_MI_B (MTK_PIN_NO(21) | 6) +#define PINMUX_GPIO21__FUNC_DBG_MON_A4 (MTK_PIN_NO(21) | 7) + +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_I2S0_BCK (MTK_PIN_NO(22) | 1) +#define PINMUX_GPIO22__FUNC_I2S1_BCK (MTK_PIN_NO(22) | 2) +#define PINMUX_GPIO22__FUNC_I2S3_BCK (MTK_PIN_NO(22) | 3) +#define PINMUX_GPIO22__FUNC_TDM_RX_LRCK (MTK_PIN_NO(22) | 4) +#define PINMUX_GPIO22__FUNC_ANT_SEL6 (MTK_PIN_NO(22) | 5) +#define PINMUX_GPIO22__FUNC_DBG_MON_A5 (MTK_PIN_NO(22) | 7) + +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_I2S0_LRCK (MTK_PIN_NO(23) | 1) +#define PINMUX_GPIO23__FUNC_I2S1_LRCK (MTK_PIN_NO(23) | 2) +#define PINMUX_GPIO23__FUNC_I2S3_LRCK (MTK_PIN_NO(23) | 3) +#define PINMUX_GPIO23__FUNC_TDM_RX_BCK (MTK_PIN_NO(23) | 4) +#define PINMUX_GPIO23__FUNC_ANT_SEL7 (MTK_PIN_NO(23) | 5) +#define PINMUX_GPIO23__FUNC_DBG_MON_A6 (MTK_PIN_NO(23) | 7) + +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_I2S0_DI (MTK_PIN_NO(24) | 1) +#define PINMUX_GPIO24__FUNC_I2S1_DO (MTK_PIN_NO(24) | 2) +#define PINMUX_GPIO24__FUNC_I2S3_DO (MTK_PIN_NO(24) | 3) +#define PINMUX_GPIO24__FUNC_TDM_RX_MCK (MTK_PIN_NO(24) | 4) +#define PINMUX_GPIO24__FUNC_DBG_MON_A7 (MTK_PIN_NO(24) | 7) + +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_I2S2_MCK (MTK_PIN_NO(25) | 1) +#define PINMUX_GPIO25__FUNC_PCM_CLK (MTK_PIN_NO(25) | 2) +#define PINMUX_GPIO25__FUNC_SPI4_CLK_B (MTK_PIN_NO(25) | 3) +#define PINMUX_GPIO25__FUNC_TDM_RX_DATA0 (MTK_PIN_NO(25) | 4) +#define PINMUX_GPIO25__FUNC_DBG_MON_A8 (MTK_PIN_NO(25) | 7) + +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_I2S2_BCK (MTK_PIN_NO(26) | 1) +#define PINMUX_GPIO26__FUNC_PCM_SYNC (MTK_PIN_NO(26) | 2) +#define PINMUX_GPIO26__FUNC_SPI4_CSB_B (MTK_PIN_NO(26) | 3) +#define PINMUX_GPIO26__FUNC_TDM_RX_DATA1 (MTK_PIN_NO(26) | 4) +#define PINMUX_GPIO26__FUNC_DBG_MON_A9 (MTK_PIN_NO(26) | 7) + +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_I2S2_LRCK (MTK_PIN_NO(27) | 1) +#define PINMUX_GPIO27__FUNC_PCM_DI (MTK_PIN_NO(27) | 2) +#define PINMUX_GPIO27__FUNC_SPI4_MO_B (MTK_PIN_NO(27) | 3) +#define PINMUX_GPIO27__FUNC_TDM_RX_DATA2 (MTK_PIN_NO(27) | 4) +#define PINMUX_GPIO27__FUNC_DBG_MON_A10 (MTK_PIN_NO(27) | 7) + +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_I2S2_DI (MTK_PIN_NO(28) | 1) +#define PINMUX_GPIO28__FUNC_PCM_DO (MTK_PIN_NO(28) | 2) +#define PINMUX_GPIO28__FUNC_SPI4_MI_B (MTK_PIN_NO(28) | 3) +#define PINMUX_GPIO28__FUNC_TDM_RX_DATA3 (MTK_PIN_NO(28) | 4) + +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_ANT_SEL0 (MTK_PIN_NO(29) | 1) +#define PINMUX_GPIO29__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(29) | 2) + +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_ANT_SEL1 (MTK_PIN_NO(30) | 1) + +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_ANT_SEL2 (MTK_PIN_NO(31) | 1) +#define PINMUX_GPIO31__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(31) | 2) +#define PINMUX_GPIO31__FUNC_SRCLKENAI1 (MTK_PIN_NO(31) | 3) + +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_URXD0 (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_UTXD0 (MTK_PIN_NO(32) | 2) +#define PINMUX_GPIO32__FUNC_ADSP_UART_RX (MTK_PIN_NO(32) | 3) +#define PINMUX_GPIO32__FUNC_TP_URXD1_AO (MTK_PIN_NO(32) | 4) + +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_UTXD0 (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_URXD0 (MTK_PIN_NO(33) | 2) +#define PINMUX_GPIO33__FUNC_ADSP_UART_TX (MTK_PIN_NO(33) | 3) +#define PINMUX_GPIO33__FUNC_TP_UTXD1_AO (MTK_PIN_NO(33) | 4) + +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_URXD1 (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_TP_URXD2_AO (MTK_PIN_NO(34) | 2) +#define PINMUX_GPIO34__FUNC_SSPM_URXD_AO (MTK_PIN_NO(34) | 3) +#define PINMUX_GPIO34__FUNC_ADSP_UART_RX (MTK_PIN_NO(34) | 4) +#define PINMUX_GPIO34__FUNC_CONN_UART0_RXD (MTK_PIN_NO(34) | 5) + +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_UTXD1 (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_TP_UTXD2_AO (MTK_PIN_NO(35) | 2) +#define PINMUX_GPIO35__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(35) | 3) +#define PINMUX_GPIO35__FUNC_ADSP_UART_TX (MTK_PIN_NO(35) | 4) +#define PINMUX_GPIO35__FUNC_CONN_UART0_TXD (MTK_PIN_NO(35) | 5) +#define PINMUX_GPIO35__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(35) | 6) + +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_SPI0_CLK_A (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_CLKM0 (MTK_PIN_NO(36) | 2) +#define PINMUX_GPIO36__FUNC_SCP_SPI0_CK (MTK_PIN_NO(36) | 4) +#define PINMUX_GPIO36__FUNC_SPINOR_CK (MTK_PIN_NO(36) | 5) +#define PINMUX_GPIO36__FUNC_DBG_MON_A11 (MTK_PIN_NO(36) | 7) + +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_SPI0_CSB_A (MTK_PIN_NO(37) | 1) +#define PINMUX_GPIO37__FUNC_CLKM1 (MTK_PIN_NO(37) | 2) +#define PINMUX_GPIO37__FUNC_PWM0 (MTK_PIN_NO(37) | 3) +#define PINMUX_GPIO37__FUNC_SCP_SPI0_CS (MTK_PIN_NO(37) | 4) +#define PINMUX_GPIO37__FUNC_SPINOR_CS (MTK_PIN_NO(37) | 5) +#define PINMUX_GPIO37__FUNC_DBG_MON_A12 (MTK_PIN_NO(37) | 7) + +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_SPI0_MO_A (MTK_PIN_NO(38) | 1) +#define PINMUX_GPIO38__FUNC_CLKM2 (MTK_PIN_NO(38) | 2) +#define PINMUX_GPIO38__FUNC_PWM1 (MTK_PIN_NO(38) | 3) +#define PINMUX_GPIO38__FUNC_SCP_SPI0_MO (MTK_PIN_NO(38) | 4) +#define PINMUX_GPIO38__FUNC_SPINOR_IO0 (MTK_PIN_NO(38) | 5) +#define PINMUX_GPIO38__FUNC_DBG_MON_A13 (MTK_PIN_NO(38) | 7) + +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_SPI0_MI_A (MTK_PIN_NO(39) | 1) +#define PINMUX_GPIO39__FUNC_CLKM3 (MTK_PIN_NO(39) | 2) +#define PINMUX_GPIO39__FUNC_PWM2 (MTK_PIN_NO(39) | 3) +#define PINMUX_GPIO39__FUNC_SCP_SPI0_MI (MTK_PIN_NO(39) | 4) +#define PINMUX_GPIO39__FUNC_SPINOR_IO1 (MTK_PIN_NO(39) | 5) +#define PINMUX_GPIO39__FUNC_DBG_MON_A14 (MTK_PIN_NO(39) | 7) + +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_SPI1_CLK_A (MTK_PIN_NO(40) | 1) +#define PINMUX_GPIO40__FUNC_SCP_SPI1_CK (MTK_PIN_NO(40) | 2) +#define PINMUX_GPIO40__FUNC_UCTS0 (MTK_PIN_NO(40) | 4) +#define PINMUX_GPIO40__FUNC_SPINOR_IO2 (MTK_PIN_NO(40) | 5) +#define PINMUX_GPIO40__FUNC_TP_UCTS1_AO (MTK_PIN_NO(40) | 6) +#define PINMUX_GPIO40__FUNC_DBG_MON_A15 (MTK_PIN_NO(40) | 7) + +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_SPI1_CSB_A (MTK_PIN_NO(41) | 1) +#define PINMUX_GPIO41__FUNC_SCP_SPI1_CS (MTK_PIN_NO(41) | 2) +#define PINMUX_GPIO41__FUNC_PWM0 (MTK_PIN_NO(41) | 3) +#define PINMUX_GPIO41__FUNC_URTS0 (MTK_PIN_NO(41) | 4) +#define PINMUX_GPIO41__FUNC_SPINOR_IO3 (MTK_PIN_NO(41) | 5) +#define PINMUX_GPIO41__FUNC_TP_URTS1_AO (MTK_PIN_NO(41) | 6) +#define PINMUX_GPIO41__FUNC_DBG_MON_A16 (MTK_PIN_NO(41) | 7) + +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_SPI1_MO_A (MTK_PIN_NO(42) | 1) +#define PINMUX_GPIO42__FUNC_SCP_SPI1_MO (MTK_PIN_NO(42) | 2) +#define PINMUX_GPIO42__FUNC_PWM1 (MTK_PIN_NO(42) | 3) +#define PINMUX_GPIO42__FUNC_UCTS1 (MTK_PIN_NO(42) | 4) +#define PINMUX_GPIO42__FUNC_TP_UCTS2_AO (MTK_PIN_NO(42) | 6) +#define PINMUX_GPIO42__FUNC_DBG_MON_A17 (MTK_PIN_NO(42) | 7) + +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_SPI1_MI_A (MTK_PIN_NO(43) | 1) +#define PINMUX_GPIO43__FUNC_SCP_SPI1_MI (MTK_PIN_NO(43) | 2) +#define PINMUX_GPIO43__FUNC_PWM2 (MTK_PIN_NO(43) | 3) +#define PINMUX_GPIO43__FUNC_URTS1 (MTK_PIN_NO(43) | 4) +#define PINMUX_GPIO43__FUNC_TP_URTS2_AO (MTK_PIN_NO(43) | 6) +#define PINMUX_GPIO43__FUNC_DBG_MON_A18 (MTK_PIN_NO(43) | 7) + +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_SPI2_CLK_A (MTK_PIN_NO(44) | 1) +#define PINMUX_GPIO44__FUNC_SCP_SPI0_CK (MTK_PIN_NO(44) | 2) +#define PINMUX_GPIO44__FUNC_DBG_MON_A19 (MTK_PIN_NO(44) | 7) + +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_SPI2_CSB_A (MTK_PIN_NO(45) | 1) +#define PINMUX_GPIO45__FUNC_SCP_SPI0_CS (MTK_PIN_NO(45) | 2) +#define PINMUX_GPIO45__FUNC_DBG_MON_A20 (MTK_PIN_NO(45) | 7) + +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_SPI2_MO_A (MTK_PIN_NO(46) | 1) +#define PINMUX_GPIO46__FUNC_SCP_SPI0_MO (MTK_PIN_NO(46) | 2) +#define PINMUX_GPIO46__FUNC_DBG_MON_A21 (MTK_PIN_NO(46) | 7) + +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_SPI2_MI_A (MTK_PIN_NO(47) | 1) +#define PINMUX_GPIO47__FUNC_SCP_SPI0_MI (MTK_PIN_NO(47) | 2) +#define PINMUX_GPIO47__FUNC_DBG_MON_A22 (MTK_PIN_NO(47) | 7) + +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_SPI3_CLK (MTK_PIN_NO(48) | 1) +#define PINMUX_GPIO48__FUNC_TP_URXD1_AO (MTK_PIN_NO(48) | 2) +#define PINMUX_GPIO48__FUNC_TP_URXD2_AO (MTK_PIN_NO(48) | 3) +#define PINMUX_GPIO48__FUNC_URXD1 (MTK_PIN_NO(48) | 4) +#define PINMUX_GPIO48__FUNC_I2S2_MCK (MTK_PIN_NO(48) | 5) +#define PINMUX_GPIO48__FUNC_SCP_SPI0_CK (MTK_PIN_NO(48) | 6) + +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_SPI3_CSB (MTK_PIN_NO(49) | 1) +#define PINMUX_GPIO49__FUNC_TP_UTXD1_AO (MTK_PIN_NO(49) | 2) +#define PINMUX_GPIO49__FUNC_TP_UTXD2_AO (MTK_PIN_NO(49) | 3) +#define PINMUX_GPIO49__FUNC_UTXD1 (MTK_PIN_NO(49) | 4) +#define PINMUX_GPIO49__FUNC_I2S2_BCK (MTK_PIN_NO(49) | 5) +#define PINMUX_GPIO49__FUNC_SCP_SPI0_CS (MTK_PIN_NO(49) | 6) + +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_SPI3_MO (MTK_PIN_NO(50) | 1) +#define PINMUX_GPIO50__FUNC_I2S2_LRCK (MTK_PIN_NO(50) | 5) +#define PINMUX_GPIO50__FUNC_SCP_SPI0_MO (MTK_PIN_NO(50) | 6) + +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_SPI3_MI (MTK_PIN_NO(51) | 1) +#define PINMUX_GPIO51__FUNC_I2S2_DI (MTK_PIN_NO(51) | 5) +#define PINMUX_GPIO51__FUNC_SCP_SPI0_MI (MTK_PIN_NO(51) | 6) + +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_SPI5_CLK (MTK_PIN_NO(52) | 1) +#define PINMUX_GPIO52__FUNC_I2S2_MCK (MTK_PIN_NO(52) | 2) +#define PINMUX_GPIO52__FUNC_I2S1_MCK (MTK_PIN_NO(52) | 3) +#define PINMUX_GPIO52__FUNC_SCP_SPI1_CK (MTK_PIN_NO(52) | 4) +#define PINMUX_GPIO52__FUNC_LVTS_26M (MTK_PIN_NO(52) | 5) +#define PINMUX_GPIO52__FUNC_DFD_TCK_XI (MTK_PIN_NO(52) | 6) +#define PINMUX_GPIO52__FUNC_DBG_MON_B30 (MTK_PIN_NO(52) | 7) + +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_SPI5_CSB (MTK_PIN_NO(53) | 1) +#define PINMUX_GPIO53__FUNC_I2S2_BCK (MTK_PIN_NO(53) | 2) +#define PINMUX_GPIO53__FUNC_I2S1_BCK (MTK_PIN_NO(53) | 3) +#define PINMUX_GPIO53__FUNC_SCP_SPI1_CS (MTK_PIN_NO(53) | 4) +#define PINMUX_GPIO53__FUNC_LVTS_FOUT (MTK_PIN_NO(53) | 5) +#define PINMUX_GPIO53__FUNC_DFD_TDI (MTK_PIN_NO(53) | 6) +#define PINMUX_GPIO53__FUNC_DBG_MON_B31 (MTK_PIN_NO(53) | 7) + +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_SPI5_MO (MTK_PIN_NO(54) | 1) +#define PINMUX_GPIO54__FUNC_I2S2_LRCK (MTK_PIN_NO(54) | 2) +#define PINMUX_GPIO54__FUNC_I2S1_LRCK (MTK_PIN_NO(54) | 3) +#define PINMUX_GPIO54__FUNC_SCP_SPI1_MO (MTK_PIN_NO(54) | 4) +#define PINMUX_GPIO54__FUNC_LVTS_SCK (MTK_PIN_NO(54) | 5) +#define PINMUX_GPIO54__FUNC_DFD_TDO (MTK_PIN_NO(54) | 6) +#define PINMUX_GPIO54__FUNC_DBG_MON_A1 (MTK_PIN_NO(54) | 7) + +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_SPI5_MI (MTK_PIN_NO(55) | 1) +#define PINMUX_GPIO55__FUNC_I2S2_DI (MTK_PIN_NO(55) | 2) +#define PINMUX_GPIO55__FUNC_I2S1_DO (MTK_PIN_NO(55) | 3) +#define PINMUX_GPIO55__FUNC_SCP_SPI1_MI (MTK_PIN_NO(55) | 4) +#define PINMUX_GPIO55__FUNC_LVTS_SDO (MTK_PIN_NO(55) | 5) +#define PINMUX_GPIO55__FUNC_DFD_TMS (MTK_PIN_NO(55) | 6) +#define PINMUX_GPIO55__FUNC_DBG_MON_B32 (MTK_PIN_NO(55) | 7) + +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_I2S1_DO (MTK_PIN_NO(56) | 1) +#define PINMUX_GPIO56__FUNC_I2S3_DO (MTK_PIN_NO(56) | 2) +#define PINMUX_GPIO56__FUNC_DBG_MON_A23 (MTK_PIN_NO(56) | 7) + +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_I2S1_BCK (MTK_PIN_NO(57) | 1) +#define PINMUX_GPIO57__FUNC_I2S3_BCK (MTK_PIN_NO(57) | 2) +#define PINMUX_GPIO57__FUNC_DBG_MON_A24 (MTK_PIN_NO(57) | 7) + +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_I2S1_LRCK (MTK_PIN_NO(58) | 1) +#define PINMUX_GPIO58__FUNC_I2S3_LRCK (MTK_PIN_NO(58) | 2) +#define PINMUX_GPIO58__FUNC_DBG_MON_A25 (MTK_PIN_NO(58) | 7) + +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_I2S1_MCK (MTK_PIN_NO(59) | 1) +#define PINMUX_GPIO59__FUNC_I2S3_MCK (MTK_PIN_NO(59) | 2) +#define PINMUX_GPIO59__FUNC_DBG_MON_A27 (MTK_PIN_NO(59) | 7) + +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_TDM_RX_LRCK (MTK_PIN_NO(60) | 1) +#define PINMUX_GPIO60__FUNC_ANT_SEL3 (MTK_PIN_NO(60) | 2) +#define PINMUX_GPIO60__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(60) | 5) + +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_TDM_RX_BCK (MTK_PIN_NO(61) | 1) +#define PINMUX_GPIO61__FUNC_ANT_SEL4 (MTK_PIN_NO(61) | 2) +#define PINMUX_GPIO61__FUNC_SPINOR_CK (MTK_PIN_NO(61) | 4) +#define PINMUX_GPIO61__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(61) | 5) + +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_TDM_RX_MCK (MTK_PIN_NO(62) | 1) +#define PINMUX_GPIO62__FUNC_ANT_SEL5 (MTK_PIN_NO(62) | 2) +#define PINMUX_GPIO62__FUNC_SPINOR_CS (MTK_PIN_NO(62) | 4) +#define PINMUX_GPIO62__FUNC_CONN_MCU_TDI (MTK_PIN_NO(62) | 5) + +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_TDM_RX_DATA0 (MTK_PIN_NO(63) | 1) +#define PINMUX_GPIO63__FUNC_ANT_SEL6 (MTK_PIN_NO(63) | 2) +#define PINMUX_GPIO63__FUNC_SPINOR_IO0 (MTK_PIN_NO(63) | 4) +#define PINMUX_GPIO63__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(63) | 5) + +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_TDM_RX_DATA1 (MTK_PIN_NO(64) | 1) +#define PINMUX_GPIO64__FUNC_ANT_SEL7 (MTK_PIN_NO(64) | 2) +#define PINMUX_GPIO64__FUNC_PWM0 (MTK_PIN_NO(64) | 3) +#define PINMUX_GPIO64__FUNC_SPINOR_IO1 (MTK_PIN_NO(64) | 4) +#define PINMUX_GPIO64__FUNC_CONN_MCU_TCK (MTK_PIN_NO(64) | 5) + +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_TDM_RX_DATA2 (MTK_PIN_NO(65) | 1) +#define PINMUX_GPIO65__FUNC_UCTS0 (MTK_PIN_NO(65) | 2) +#define PINMUX_GPIO65__FUNC_PWM1 (MTK_PIN_NO(65) | 3) +#define PINMUX_GPIO65__FUNC_SPINOR_IO2 (MTK_PIN_NO(65) | 4) +#define PINMUX_GPIO65__FUNC_CONN_MCU_TDO (MTK_PIN_NO(65) | 5) +#define PINMUX_GPIO65__FUNC_TP_UCTS1_AO (MTK_PIN_NO(65) | 6) +#define PINMUX_GPIO65__FUNC_TP_UCTS2_AO (MTK_PIN_NO(65) | 7) + +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_TDM_RX_DATA3 (MTK_PIN_NO(66) | 1) +#define PINMUX_GPIO66__FUNC_URTS0 (MTK_PIN_NO(66) | 2) +#define PINMUX_GPIO66__FUNC_PWM2 (MTK_PIN_NO(66) | 3) +#define PINMUX_GPIO66__FUNC_SPINOR_IO3 (MTK_PIN_NO(66) | 4) +#define PINMUX_GPIO66__FUNC_CONN_MCU_TMS (MTK_PIN_NO(66) | 5) +#define PINMUX_GPIO66__FUNC_TP_URTS1_AO (MTK_PIN_NO(66) | 6) +#define PINMUX_GPIO66__FUNC_TP_URTS2_AO (MTK_PIN_NO(66) | 7) + +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_MSDC0_DSL (MTK_PIN_NO(67) | 1) + +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_MSDC0_CLK (MTK_PIN_NO(68) | 1) + +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_MSDC0_CMD (MTK_PIN_NO(69) | 1) + +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_MSDC0_RSTB (MTK_PIN_NO(70) | 1) + +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define PINMUX_GPIO71__FUNC_MSDC0_DAT0 (MTK_PIN_NO(71) | 1) + +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define PINMUX_GPIO72__FUNC_MSDC0_DAT1 (MTK_PIN_NO(72) | 1) + +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define PINMUX_GPIO73__FUNC_MSDC0_DAT2 (MTK_PIN_NO(73) | 1) + +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_MSDC0_DAT3 (MTK_PIN_NO(74) | 1) + +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_MSDC0_DAT4 (MTK_PIN_NO(75) | 1) + +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_MSDC0_DAT5 (MTK_PIN_NO(76) | 1) + +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_MSDC0_DAT6 (MTK_PIN_NO(77) | 1) + +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_MSDC0_DAT7 (MTK_PIN_NO(78) | 1) + +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_KPCOL0 (MTK_PIN_NO(79) | 1) + +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_KPCOL1 (MTK_PIN_NO(80) | 1) +#define PINMUX_GPIO80__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(80) | 2) +#define PINMUX_GPIO80__FUNC_PWM0 (MTK_PIN_NO(80) | 3) +#define PINMUX_GPIO80__FUNC_CLKM0 (MTK_PIN_NO(80) | 4) + +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_KPROW0 (MTK_PIN_NO(81) | 1) +#define PINMUX_GPIO81__FUNC_PWM1 (MTK_PIN_NO(81) | 3) +#define PINMUX_GPIO81__FUNC_CLKM1 (MTK_PIN_NO(81) | 4) + +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_KPROW1 (MTK_PIN_NO(82) | 1) +#define PINMUX_GPIO82__FUNC_PWM2 (MTK_PIN_NO(82) | 3) +#define PINMUX_GPIO82__FUNC_CLKM2 (MTK_PIN_NO(82) | 4) + +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_AP_GOOD (MTK_PIN_NO(83) | 1) +#define PINMUX_GPIO83__FUNC_GPS_PPS (MTK_PIN_NO(83) | 2) +#define PINMUX_GPIO83__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(83) | 4) +#define PINMUX_GPIO83__FUNC_DBG_MON_A28 (MTK_PIN_NO(83) | 7) + +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_MSDC1_CLK (MTK_PIN_NO(84) | 1) +#define PINMUX_GPIO84__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(84) | 2) +#define PINMUX_GPIO84__FUNC_UDI_TCK (MTK_PIN_NO(84) | 4) +#define PINMUX_GPIO84__FUNC_CONN_DSP_JCK (MTK_PIN_NO(84) | 5) +#define PINMUX_GPIO84__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(84) | 6) +#define PINMUX_GPIO84__FUNC_DFD_TCK_XI (MTK_PIN_NO(84) | 7) + +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_MSDC1_CMD (MTK_PIN_NO(85) | 1) +#define PINMUX_GPIO85__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(85) | 2) +#define PINMUX_GPIO85__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(85) | 3) +#define PINMUX_GPIO85__FUNC_UDI_TMS (MTK_PIN_NO(85) | 4) +#define PINMUX_GPIO85__FUNC_CONN_DSP_JMS (MTK_PIN_NO(85) | 5) +#define PINMUX_GPIO85__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(85) | 6) +#define PINMUX_GPIO85__FUNC_DFD_TMS (MTK_PIN_NO(85) | 7) + +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_MSDC1_DAT0 (MTK_PIN_NO(86) | 1) +#define PINMUX_GPIO86__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(86) | 2) +#define PINMUX_GPIO86__FUNC_UDI_TDI (MTK_PIN_NO(86) | 4) +#define PINMUX_GPIO86__FUNC_CONN_DSP_JDI (MTK_PIN_NO(86) | 5) +#define PINMUX_GPIO86__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(86) | 6) +#define PINMUX_GPIO86__FUNC_DFD_TDI (MTK_PIN_NO(86) | 7) + +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_MSDC1_DAT1 (MTK_PIN_NO(87) | 1) +#define PINMUX_GPIO87__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(87) | 2) +#define PINMUX_GPIO87__FUNC_UDI_TDO (MTK_PIN_NO(87) | 4) +#define PINMUX_GPIO87__FUNC_CONN_DSP_JDO (MTK_PIN_NO(87) | 5) +#define PINMUX_GPIO87__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(87) | 6) +#define PINMUX_GPIO87__FUNC_DFD_TDO (MTK_PIN_NO(87) | 7) + +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_MSDC1_DAT2 (MTK_PIN_NO(88) | 1) +#define PINMUX_GPIO88__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(88) | 2) +#define PINMUX_GPIO88__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(88) | 3) +#define PINMUX_GPIO88__FUNC_UDI_NTRST (MTK_PIN_NO(88) | 4) +#define PINMUX_GPIO88__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(88) | 5) +#define PINMUX_GPIO88__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(88) | 6) + +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_MSDC1_DAT3 (MTK_PIN_NO(89) | 1) +#define PINMUX_GPIO89__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(89) | 5) + +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_IDDIG_P0 (MTK_PIN_NO(90) | 1) +#define PINMUX_GPIO90__FUNC_PGD_HV_HSC_PWR4 (MTK_PIN_NO(90) | 4) +#define PINMUX_GPIO90__FUNC_GDU_SUM_TROOP2_2 (MTK_PIN_NO(90) | 5) + +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(91) | 1) +#define PINMUX_GPIO91__FUNC_PGD_HV_HSC_PWR5 (MTK_PIN_NO(91) | 4) +#define PINMUX_GPIO91__FUNC_GDU_TROOPS_DET0 (MTK_PIN_NO(91) | 5) + +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_VBUS_VALID_P0 (MTK_PIN_NO(92) | 1) +#define PINMUX_GPIO92__FUNC_PGD_DA_EFUSE_RDY (MTK_PIN_NO(92) | 4) +#define PINMUX_GPIO92__FUNC_GDU_TROOPS_DET1 (MTK_PIN_NO(92) | 5) + +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_IDDIG_P1 (MTK_PIN_NO(93) | 1) +#define PINMUX_GPIO93__FUNC_PWM0 (MTK_PIN_NO(93) | 2) +#define PINMUX_GPIO93__FUNC_CLKM0 (MTK_PIN_NO(93) | 3) +#define PINMUX_GPIO93__FUNC_PGD_DA_EFUSE_RDY_PRE (MTK_PIN_NO(93) | 4) +#define PINMUX_GPIO93__FUNC_GDU_TROOPS_DET2 (MTK_PIN_NO(93) | 5) + +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(94) | 1) +#define PINMUX_GPIO94__FUNC_PWM1 (MTK_PIN_NO(94) | 2) +#define PINMUX_GPIO94__FUNC_CLKM1 (MTK_PIN_NO(94) | 3) +#define PINMUX_GPIO94__FUNC_PGD_DA_PWRGD_RESET (MTK_PIN_NO(94) | 4) + +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_VBUS_VALID_P1 (MTK_PIN_NO(95) | 1) +#define PINMUX_GPIO95__FUNC_PWM2 (MTK_PIN_NO(95) | 2) +#define PINMUX_GPIO95__FUNC_CLKM2 (MTK_PIN_NO(95) | 3) +#define PINMUX_GPIO95__FUNC_PGD_DA_PWRGD_ENB (MTK_PIN_NO(95) | 4) + +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_DSI_TE (MTK_PIN_NO(96) | 1) +#define PINMUX_GPIO96__FUNC_DBG_MON_A29 (MTK_PIN_NO(96) | 7) + +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_DISP_PWM (MTK_PIN_NO(97) | 1) +#define PINMUX_GPIO97__FUNC_DBG_MON_A30 (MTK_PIN_NO(97) | 7) + +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_LCM_RST (MTK_PIN_NO(98) | 1) + +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_DPI_PCLK (MTK_PIN_NO(99) | 1) +#define PINMUX_GPIO99__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(99) | 2) +#define PINMUX_GPIO99__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(99) | 3) +#define PINMUX_GPIO99__FUNC_ANT_SEL0 (MTK_PIN_NO(99) | 5) +#define PINMUX_GPIO99__FUNC_TP_GPIO0_AO (MTK_PIN_NO(99) | 6) +#define PINMUX_GPIO99__FUNC_PGD_LV_LSC_PWR0 (MTK_PIN_NO(99) | 7) + +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_DPI_VSYNC (MTK_PIN_NO(100) | 1) +#define PINMUX_GPIO100__FUNC_KPCOL2 (MTK_PIN_NO(100) | 2) +#define PINMUX_GPIO100__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(100) | 3) +#define PINMUX_GPIO100__FUNC_ANT_SEL1 (MTK_PIN_NO(100) | 5) +#define PINMUX_GPIO100__FUNC_TP_GPIO1_AO (MTK_PIN_NO(100) | 6) +#define PINMUX_GPIO100__FUNC_PGD_LV_LSC_PWR1 (MTK_PIN_NO(100) | 7) + +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_DPI_HSYNC (MTK_PIN_NO(101) | 1) +#define PINMUX_GPIO101__FUNC_KPROW2 (MTK_PIN_NO(101) | 2) +#define PINMUX_GPIO101__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(101) | 3) +#define PINMUX_GPIO101__FUNC_ANT_SEL2 (MTK_PIN_NO(101) | 5) +#define PINMUX_GPIO101__FUNC_TP_GPIO2_AO (MTK_PIN_NO(101) | 6) +#define PINMUX_GPIO101__FUNC_PGD_LV_LSC_PWR2 (MTK_PIN_NO(101) | 7) + +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_DPI_DE (MTK_PIN_NO(102) | 1) +#define PINMUX_GPIO102__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(102) | 3) +#define PINMUX_GPIO102__FUNC_ANT_SEL3 (MTK_PIN_NO(102) | 5) +#define PINMUX_GPIO102__FUNC_TP_GPIO3_AO (MTK_PIN_NO(102) | 6) +#define PINMUX_GPIO102__FUNC_PGD_LV_LSC_PWR3 (MTK_PIN_NO(102) | 7) + +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_DPI_DATA0 (MTK_PIN_NO(103) | 1) +#define PINMUX_GPIO103__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(103) | 3) +#define PINMUX_GPIO103__FUNC_CLKM0 (MTK_PIN_NO(103) | 4) +#define PINMUX_GPIO103__FUNC_ANT_SEL4 (MTK_PIN_NO(103) | 5) +#define PINMUX_GPIO103__FUNC_TP_GPIO4_AO (MTK_PIN_NO(103) | 6) +#define PINMUX_GPIO103__FUNC_PGD_LV_LSC_PWR4 (MTK_PIN_NO(103) | 7) + +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_DPI_DATA1 (MTK_PIN_NO(104) | 1) +#define PINMUX_GPIO104__FUNC_GPS_PPS (MTK_PIN_NO(104) | 2) +#define PINMUX_GPIO104__FUNC_UCTS2 (MTK_PIN_NO(104) | 3) +#define PINMUX_GPIO104__FUNC_CLKM1 (MTK_PIN_NO(104) | 4) +#define PINMUX_GPIO104__FUNC_ANT_SEL5 (MTK_PIN_NO(104) | 5) +#define PINMUX_GPIO104__FUNC_TP_GPIO5_AO (MTK_PIN_NO(104) | 6) +#define PINMUX_GPIO104__FUNC_PGD_LV_LSC_PWR5 (MTK_PIN_NO(104) | 7) + +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_DPI_DATA2 (MTK_PIN_NO(105) | 1) +#define PINMUX_GPIO105__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(105) | 2) +#define PINMUX_GPIO105__FUNC_URTS2 (MTK_PIN_NO(105) | 3) +#define PINMUX_GPIO105__FUNC_CLKM2 (MTK_PIN_NO(105) | 4) +#define PINMUX_GPIO105__FUNC_ANT_SEL6 (MTK_PIN_NO(105) | 5) +#define PINMUX_GPIO105__FUNC_TP_GPIO6_AO (MTK_PIN_NO(105) | 6) +#define PINMUX_GPIO105__FUNC_PGD_LV_HSC_PWR0 (MTK_PIN_NO(105) | 7) + +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_DPI_DATA3 (MTK_PIN_NO(106) | 1) +#define PINMUX_GPIO106__FUNC_TP_UTXD1_AO (MTK_PIN_NO(106) | 2) +#define PINMUX_GPIO106__FUNC_UTXD2 (MTK_PIN_NO(106) | 3) +#define PINMUX_GPIO106__FUNC_PWM0 (MTK_PIN_NO(106) | 4) +#define PINMUX_GPIO106__FUNC_ANT_SEL7 (MTK_PIN_NO(106) | 5) +#define PINMUX_GPIO106__FUNC_TP_GPIO7_AO (MTK_PIN_NO(106) | 6) +#define PINMUX_GPIO106__FUNC_PGD_LV_HSC_PWR1 (MTK_PIN_NO(106) | 7) + +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_DPI_DATA4 (MTK_PIN_NO(107) | 1) +#define PINMUX_GPIO107__FUNC_TP_URXD1_AO (MTK_PIN_NO(107) | 2) +#define PINMUX_GPIO107__FUNC_URXD2 (MTK_PIN_NO(107) | 3) +#define PINMUX_GPIO107__FUNC_PWM1 (MTK_PIN_NO(107) | 4) +#define PINMUX_GPIO107__FUNC_GDU_SUM_TROOP0_0 (MTK_PIN_NO(107) | 6) +#define PINMUX_GPIO107__FUNC_PGD_LV_HSC_PWR2 (MTK_PIN_NO(107) | 7) + +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_DPI_DATA5 (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_TP_UCTS1_AO (MTK_PIN_NO(108) | 2) +#define PINMUX_GPIO108__FUNC_UCTS0 (MTK_PIN_NO(108) | 3) +#define PINMUX_GPIO108__FUNC_PWM2 (MTK_PIN_NO(108) | 4) +#define PINMUX_GPIO108__FUNC_GDU_SUM_TROOP0_1 (MTK_PIN_NO(108) | 6) +#define PINMUX_GPIO108__FUNC_PGD_LV_HSC_PWR3 (MTK_PIN_NO(108) | 7) + +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_DPI_DATA6 (MTK_PIN_NO(109) | 1) +#define PINMUX_GPIO109__FUNC_TP_URTS1_AO (MTK_PIN_NO(109) | 2) +#define PINMUX_GPIO109__FUNC_URTS0 (MTK_PIN_NO(109) | 3) +#define PINMUX_GPIO109__FUNC_I2S0_DI (MTK_PIN_NO(109) | 4) +#define PINMUX_GPIO109__FUNC_I2S2_DI (MTK_PIN_NO(109) | 5) +#define PINMUX_GPIO109__FUNC_GDU_SUM_TROOP0_2 (MTK_PIN_NO(109) | 6) +#define PINMUX_GPIO109__FUNC_PGD_LV_HSC_PWR4 (MTK_PIN_NO(109) | 7) + +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_DPI_DATA7 (MTK_PIN_NO(110) | 1) +#define PINMUX_GPIO110__FUNC_TP_UCTS2_AO (MTK_PIN_NO(110) | 2) +#define PINMUX_GPIO110__FUNC_UCTS1 (MTK_PIN_NO(110) | 3) +#define PINMUX_GPIO110__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 4) +#define PINMUX_GPIO110__FUNC_I2S1_BCK (MTK_PIN_NO(110) | 5) +#define PINMUX_GPIO110__FUNC_GDU_SUM_TROOP1_0 (MTK_PIN_NO(110) | 6) +#define PINMUX_GPIO110__FUNC_PGD_LV_HSC_PWR5 (MTK_PIN_NO(110) | 7) + +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_DPI_DATA8 (MTK_PIN_NO(111) | 1) +#define PINMUX_GPIO111__FUNC_TP_URTS2_AO (MTK_PIN_NO(111) | 2) +#define PINMUX_GPIO111__FUNC_URTS1 (MTK_PIN_NO(111) | 3) +#define PINMUX_GPIO111__FUNC_I2S3_MCK (MTK_PIN_NO(111) | 4) +#define PINMUX_GPIO111__FUNC_I2S1_MCK (MTK_PIN_NO(111) | 5) +#define PINMUX_GPIO111__FUNC_GDU_SUM_TROOP1_1 (MTK_PIN_NO(111) | 6) +#define PINMUX_GPIO111__FUNC_PGD_HV_HSC_PWR0 (MTK_PIN_NO(111) | 7) + +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_DPI_DATA9 (MTK_PIN_NO(112) | 1) +#define PINMUX_GPIO112__FUNC_TP_URXD2_AO (MTK_PIN_NO(112) | 2) +#define PINMUX_GPIO112__FUNC_URXD1 (MTK_PIN_NO(112) | 3) +#define PINMUX_GPIO112__FUNC_I2S3_LRCK (MTK_PIN_NO(112) | 4) +#define PINMUX_GPIO112__FUNC_I2S1_LRCK (MTK_PIN_NO(112) | 5) +#define PINMUX_GPIO112__FUNC_GDU_SUM_TROOP1_2 (MTK_PIN_NO(112) | 6) +#define PINMUX_GPIO112__FUNC_PGD_HV_HSC_PWR1 (MTK_PIN_NO(112) | 7) + +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_DPI_DATA10 (MTK_PIN_NO(113) | 1) +#define PINMUX_GPIO113__FUNC_TP_UTXD2_AO (MTK_PIN_NO(113) | 2) +#define PINMUX_GPIO113__FUNC_UTXD1 (MTK_PIN_NO(113) | 3) +#define PINMUX_GPIO113__FUNC_I2S3_DO (MTK_PIN_NO(113) | 4) +#define PINMUX_GPIO113__FUNC_I2S1_DO (MTK_PIN_NO(113) | 5) +#define PINMUX_GPIO113__FUNC_GDU_SUM_TROOP2_0 (MTK_PIN_NO(113) | 6) +#define PINMUX_GPIO113__FUNC_PGD_HV_HSC_PWR2 (MTK_PIN_NO(113) | 7) + +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_DPI_DATA11 (MTK_PIN_NO(114) | 1) +#define PINMUX_GPIO114__FUNC_GDU_SUM_TROOP2_1 (MTK_PIN_NO(114) | 6) +#define PINMUX_GPIO114__FUNC_PGD_HV_HSC_PWR3 (MTK_PIN_NO(114) | 7) + +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_PCM_CLK (MTK_PIN_NO(115) | 1) +#define PINMUX_GPIO115__FUNC_I2S0_BCK (MTK_PIN_NO(115) | 2) +#define PINMUX_GPIO115__FUNC_I2S2_BCK (MTK_PIN_NO(115) | 3) + +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_PCM_SYNC (MTK_PIN_NO(116) | 1) +#define PINMUX_GPIO116__FUNC_I2S0_LRCK (MTK_PIN_NO(116) | 2) +#define PINMUX_GPIO116__FUNC_I2S2_LRCK (MTK_PIN_NO(116) | 3) + +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_PCM_DI (MTK_PIN_NO(117) | 1) +#define PINMUX_GPIO117__FUNC_I2S0_DI (MTK_PIN_NO(117) | 2) +#define PINMUX_GPIO117__FUNC_I2S2_DI (MTK_PIN_NO(117) | 3) + +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_PCM_DO (MTK_PIN_NO(118) | 1) +#define PINMUX_GPIO118__FUNC_I2S0_MCK (MTK_PIN_NO(118) | 2) +#define PINMUX_GPIO118__FUNC_I2S2_MCK (MTK_PIN_NO(118) | 3) +#define PINMUX_GPIO118__FUNC_I2S3_DO (MTK_PIN_NO(118) | 4) +#define PINMUX_GPIO118__FUNC_I2S1_DO (MTK_PIN_NO(118) | 5) + +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_JTMS_SEL1 (MTK_PIN_NO(119) | 1) +#define PINMUX_GPIO119__FUNC_UDI_TMS (MTK_PIN_NO(119) | 2) +#define PINMUX_GPIO119__FUNC_DFD_TMS (MTK_PIN_NO(119) | 3) +#define PINMUX_GPIO119__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(119) | 4) +#define PINMUX_GPIO119__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(119) | 5) +#define PINMUX_GPIO119__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(119) | 6) + +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_JTCK_SEL1 (MTK_PIN_NO(120) | 1) +#define PINMUX_GPIO120__FUNC_UDI_TCK (MTK_PIN_NO(120) | 2) +#define PINMUX_GPIO120__FUNC_DFD_TCK_XI (MTK_PIN_NO(120) | 3) +#define PINMUX_GPIO120__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(120) | 4) +#define PINMUX_GPIO120__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(120) | 5) +#define PINMUX_GPIO120__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(120) | 6) + +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_JTDI_SEL1 (MTK_PIN_NO(121) | 1) +#define PINMUX_GPIO121__FUNC_UDI_TDI (MTK_PIN_NO(121) | 2) +#define PINMUX_GPIO121__FUNC_DFD_TDI (MTK_PIN_NO(121) | 3) +#define PINMUX_GPIO121__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(121) | 4) +#define PINMUX_GPIO121__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(121) | 5) +#define PINMUX_GPIO121__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(121) | 6) + +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_JTDO_SEL1 (MTK_PIN_NO(122) | 1) +#define PINMUX_GPIO122__FUNC_UDI_TDO (MTK_PIN_NO(122) | 2) +#define PINMUX_GPIO122__FUNC_DFD_TDO (MTK_PIN_NO(122) | 3) +#define PINMUX_GPIO122__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(122) | 4) +#define PINMUX_GPIO122__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(122) | 5) +#define PINMUX_GPIO122__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(122) | 6) + +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(123) | 1) +#define PINMUX_GPIO123__FUNC_UDI_NTRST (MTK_PIN_NO(123) | 2) +#define PINMUX_GPIO123__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(123) | 4) +#define PINMUX_GPIO123__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(123) | 5) +#define PINMUX_GPIO123__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(123) | 6) + +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_CMMCLK0 (MTK_PIN_NO(124) | 1) +#define PINMUX_GPIO124__FUNC_CLKM0 (MTK_PIN_NO(124) | 2) +#define PINMUX_GPIO124__FUNC_PWM0 (MTK_PIN_NO(124) | 3) + +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_CMMCLK1 (MTK_PIN_NO(125) | 1) +#define PINMUX_GPIO125__FUNC_CLKM1 (MTK_PIN_NO(125) | 2) +#define PINMUX_GPIO125__FUNC_PWM1 (MTK_PIN_NO(125) | 3) +#define PINMUX_GPIO125__FUNC_DBG_MON_B0 (MTK_PIN_NO(125) | 7) + +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_CMMCLK2 (MTK_PIN_NO(126) | 1) +#define PINMUX_GPIO126__FUNC_CLKM2 (MTK_PIN_NO(126) | 2) +#define PINMUX_GPIO126__FUNC_PWM2 (MTK_PIN_NO(126) | 3) +#define PINMUX_GPIO126__FUNC_DBG_MON_B1 (MTK_PIN_NO(126) | 7) + +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_SCL0 (MTK_PIN_NO(127) | 1) +#define PINMUX_GPIO127__FUNC_SCP_SCL0 (MTK_PIN_NO(127) | 4) +#define PINMUX_GPIO127__FUNC_SCP_SCL1 (MTK_PIN_NO(127) | 5) + +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_SDA0 (MTK_PIN_NO(128) | 1) +#define PINMUX_GPIO128__FUNC_SCP_SDA0 (MTK_PIN_NO(128) | 4) +#define PINMUX_GPIO128__FUNC_SCP_SDA1 (MTK_PIN_NO(128) | 5) + +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_SCL1 (MTK_PIN_NO(129) | 1) +#define PINMUX_GPIO129__FUNC_SCP_SCL0 (MTK_PIN_NO(129) | 4) +#define PINMUX_GPIO129__FUNC_SCP_SCL1 (MTK_PIN_NO(129) | 5) +#define PINMUX_GPIO129__FUNC_DBG_MON_B4 (MTK_PIN_NO(129) | 7) + +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_SDA1 (MTK_PIN_NO(130) | 1) +#define PINMUX_GPIO130__FUNC_SCP_SDA0 (MTK_PIN_NO(130) | 4) +#define PINMUX_GPIO130__FUNC_SCP_SDA1 (MTK_PIN_NO(130) | 5) +#define PINMUX_GPIO130__FUNC_DBG_MON_B5 (MTK_PIN_NO(130) | 7) + +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_SCL2 (MTK_PIN_NO(131) | 1) +#define PINMUX_GPIO131__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(131) | 2) +#define PINMUX_GPIO131__FUNC_CONN_UART0_TXD (MTK_PIN_NO(131) | 3) +#define PINMUX_GPIO131__FUNC_SCP_SCL0 (MTK_PIN_NO(131) | 4) +#define PINMUX_GPIO131__FUNC_SCP_SCL1 (MTK_PIN_NO(131) | 5) +#define PINMUX_GPIO131__FUNC_DBG_MON_B6 (MTK_PIN_NO(131) | 7) + +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_SDA2 (MTK_PIN_NO(132) | 1) +#define PINMUX_GPIO132__FUNC_SSPM_URXD_AO (MTK_PIN_NO(132) | 2) +#define PINMUX_GPIO132__FUNC_CONN_UART0_RXD (MTK_PIN_NO(132) | 3) +#define PINMUX_GPIO132__FUNC_SCP_SDA0 (MTK_PIN_NO(132) | 4) +#define PINMUX_GPIO132__FUNC_SCP_SDA1 (MTK_PIN_NO(132) | 5) +#define PINMUX_GPIO132__FUNC_DBG_MON_B7 (MTK_PIN_NO(132) | 7) + +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_SCL3 (MTK_PIN_NO(133) | 1) +#define PINMUX_GPIO133__FUNC_SCP_SCL0 (MTK_PIN_NO(133) | 4) +#define PINMUX_GPIO133__FUNC_SCP_SCL1 (MTK_PIN_NO(133) | 5) +#define PINMUX_GPIO133__FUNC_DBG_MON_B8 (MTK_PIN_NO(133) | 7) + +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_SDA3 (MTK_PIN_NO(134) | 1) +#define PINMUX_GPIO134__FUNC_GPS_PPS (MTK_PIN_NO(134) | 3) +#define PINMUX_GPIO134__FUNC_SCP_SDA0 (MTK_PIN_NO(134) | 4) +#define PINMUX_GPIO134__FUNC_SCP_SDA1 (MTK_PIN_NO(134) | 5) +#define PINMUX_GPIO134__FUNC_DBG_MON_B9 (MTK_PIN_NO(134) | 7) + +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_SCL4 (MTK_PIN_NO(135) | 1) +#define PINMUX_GPIO135__FUNC_TP_UTXD1_AO (MTK_PIN_NO(135) | 2) +#define PINMUX_GPIO135__FUNC_UTXD1 (MTK_PIN_NO(135) | 3) +#define PINMUX_GPIO135__FUNC_SCP_SCL0 (MTK_PIN_NO(135) | 4) +#define PINMUX_GPIO135__FUNC_SCP_SCL1 (MTK_PIN_NO(135) | 5) +#define PINMUX_GPIO135__FUNC_DBG_MON_B10 (MTK_PIN_NO(135) | 7) + +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_SDA4 (MTK_PIN_NO(136) | 1) +#define PINMUX_GPIO136__FUNC_TP_URXD1_AO (MTK_PIN_NO(136) | 2) +#define PINMUX_GPIO136__FUNC_URXD1 (MTK_PIN_NO(136) | 3) +#define PINMUX_GPIO136__FUNC_SCP_SDA0 (MTK_PIN_NO(136) | 4) +#define PINMUX_GPIO136__FUNC_SCP_SDA1 (MTK_PIN_NO(136) | 5) +#define PINMUX_GPIO136__FUNC_DBG_MON_B11 (MTK_PIN_NO(136) | 7) + +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_SCL5 (MTK_PIN_NO(137) | 1) +#define PINMUX_GPIO137__FUNC_UTXD2 (MTK_PIN_NO(137) | 2) +#define PINMUX_GPIO137__FUNC_UCTS1 (MTK_PIN_NO(137) | 3) +#define PINMUX_GPIO137__FUNC_SCP_SCL0 (MTK_PIN_NO(137) | 4) +#define PINMUX_GPIO137__FUNC_SCP_SCL1 (MTK_PIN_NO(137) | 5) + +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_SDA5 (MTK_PIN_NO(138) | 1) +#define PINMUX_GPIO138__FUNC_URXD2 (MTK_PIN_NO(138) | 2) +#define PINMUX_GPIO138__FUNC_URTS1 (MTK_PIN_NO(138) | 3) +#define PINMUX_GPIO138__FUNC_SCP_SDA0 (MTK_PIN_NO(138) | 4) +#define PINMUX_GPIO138__FUNC_SCP_SDA1 (MTK_PIN_NO(138) | 5) + +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_SCL6 (MTK_PIN_NO(139) | 1) +#define PINMUX_GPIO139__FUNC_UTXD1 (MTK_PIN_NO(139) | 2) +#define PINMUX_GPIO139__FUNC_TP_UTXD1_AO (MTK_PIN_NO(139) | 3) +#define PINMUX_GPIO139__FUNC_SCP_SCL0 (MTK_PIN_NO(139) | 4) +#define PINMUX_GPIO139__FUNC_SCP_SCL1 (MTK_PIN_NO(139) | 5) +#define PINMUX_GPIO139__FUNC_DBG_MON_B12 (MTK_PIN_NO(139) | 7) + +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_SDA6 (MTK_PIN_NO(140) | 1) +#define PINMUX_GPIO140__FUNC_URXD1 (MTK_PIN_NO(140) | 2) +#define PINMUX_GPIO140__FUNC_TP_URXD1_AO (MTK_PIN_NO(140) | 3) +#define PINMUX_GPIO140__FUNC_SCP_SDA0 (MTK_PIN_NO(140) | 4) +#define PINMUX_GPIO140__FUNC_SCP_SDA1 (MTK_PIN_NO(140) | 5) +#define PINMUX_GPIO140__FUNC_DBG_MON_B13 (MTK_PIN_NO(140) | 7) + +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_SCL7 (MTK_PIN_NO(141) | 1) +#define PINMUX_GPIO141__FUNC_URTS0 (MTK_PIN_NO(141) | 2) +#define PINMUX_GPIO141__FUNC_TP_URTS1_AO (MTK_PIN_NO(141) | 3) +#define PINMUX_GPIO141__FUNC_SCP_SCL0 (MTK_PIN_NO(141) | 4) +#define PINMUX_GPIO141__FUNC_SCP_SCL1 (MTK_PIN_NO(141) | 5) +#define PINMUX_GPIO141__FUNC_UDI_TCK (MTK_PIN_NO(141) | 6) +#define PINMUX_GPIO141__FUNC_DBG_MON_B14 (MTK_PIN_NO(141) | 7) + +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_SDA7 (MTK_PIN_NO(142) | 1) +#define PINMUX_GPIO142__FUNC_UCTS0 (MTK_PIN_NO(142) | 2) +#define PINMUX_GPIO142__FUNC_TP_UCTS1_AO (MTK_PIN_NO(142) | 3) +#define PINMUX_GPIO142__FUNC_SCP_SDA0 (MTK_PIN_NO(142) | 4) +#define PINMUX_GPIO142__FUNC_SCP_SDA1 (MTK_PIN_NO(142) | 5) + +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_SCL8 (MTK_PIN_NO(143) | 1) +#define PINMUX_GPIO143__FUNC_SCP_SCL0 (MTK_PIN_NO(143) | 4) +#define PINMUX_GPIO143__FUNC_SCP_SCL1 (MTK_PIN_NO(143) | 5) +#define PINMUX_GPIO143__FUNC_DBG_MON_B16 (MTK_PIN_NO(143) | 7) + +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define PINMUX_GPIO144__FUNC_SDA8 (MTK_PIN_NO(144) | 1) +#define PINMUX_GPIO144__FUNC_SCP_SDA0 (MTK_PIN_NO(144) | 4) +#define PINMUX_GPIO144__FUNC_SCP_SDA1 (MTK_PIN_NO(144) | 5) +#define PINMUX_GPIO144__FUNC_DBG_MON_B17 (MTK_PIN_NO(144) | 7) + +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define PINMUX_GPIO145__FUNC_SCL9 (MTK_PIN_NO(145) | 1) +#define PINMUX_GPIO145__FUNC_CMVREF1 (MTK_PIN_NO(145) | 2) +#define PINMUX_GPIO145__FUNC_GPS_PPS (MTK_PIN_NO(145) | 3) +#define PINMUX_GPIO145__FUNC_SCP_SCL0 (MTK_PIN_NO(145) | 4) +#define PINMUX_GPIO145__FUNC_SCP_SCL1 (MTK_PIN_NO(145) | 5) +#define PINMUX_GPIO145__FUNC_DBG_MON_B18 (MTK_PIN_NO(145) | 7) + +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define PINMUX_GPIO146__FUNC_SDA9 (MTK_PIN_NO(146) | 1) +#define PINMUX_GPIO146__FUNC_CMVREF0 (MTK_PIN_NO(146) | 2) +#define PINMUX_GPIO146__FUNC_SCP_SDA0 (MTK_PIN_NO(146) | 4) +#define PINMUX_GPIO146__FUNC_SCP_SDA1 (MTK_PIN_NO(146) | 5) +#define PINMUX_GPIO146__FUNC_DBG_MON_B19 (MTK_PIN_NO(146) | 7) + +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define PINMUX_GPIO147__FUNC_CMFLASH0 (MTK_PIN_NO(147) | 1) +#define PINMUX_GPIO147__FUNC_LVTS_SDI (MTK_PIN_NO(147) | 2) +#define PINMUX_GPIO147__FUNC_DPI_DATA12 (MTK_PIN_NO(147) | 3) +#define PINMUX_GPIO147__FUNC_TP_GPIO0_AO (MTK_PIN_NO(147) | 4) +#define PINMUX_GPIO147__FUNC_ANT_SEL3 (MTK_PIN_NO(147) | 5) +#define PINMUX_GPIO147__FUNC_DFD_TCK_XI (MTK_PIN_NO(147) | 6) +#define PINMUX_GPIO147__FUNC_DBG_MON_B20 (MTK_PIN_NO(147) | 7) + +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define PINMUX_GPIO148__FUNC_CMFLASH1 (MTK_PIN_NO(148) | 1) +#define PINMUX_GPIO148__FUNC_LVTS_SCF (MTK_PIN_NO(148) | 2) +#define PINMUX_GPIO148__FUNC_DPI_DATA13 (MTK_PIN_NO(148) | 3) +#define PINMUX_GPIO148__FUNC_TP_GPIO1_AO (MTK_PIN_NO(148) | 4) +#define PINMUX_GPIO148__FUNC_ANT_SEL4 (MTK_PIN_NO(148) | 5) +#define PINMUX_GPIO148__FUNC_DFD_TMS (MTK_PIN_NO(148) | 6) +#define PINMUX_GPIO148__FUNC_DBG_MON_B21 (MTK_PIN_NO(148) | 7) + +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define PINMUX_GPIO149__FUNC_CMFLASH2 (MTK_PIN_NO(149) | 1) +#define PINMUX_GPIO149__FUNC_CLKM0 (MTK_PIN_NO(149) | 2) +#define PINMUX_GPIO149__FUNC_DPI_DATA14 (MTK_PIN_NO(149) | 3) +#define PINMUX_GPIO149__FUNC_TP_GPIO2_AO (MTK_PIN_NO(149) | 4) +#define PINMUX_GPIO149__FUNC_ANT_SEL5 (MTK_PIN_NO(149) | 5) +#define PINMUX_GPIO149__FUNC_DFD_TDI (MTK_PIN_NO(149) | 6) +#define PINMUX_GPIO149__FUNC_DBG_MON_B22 (MTK_PIN_NO(149) | 7) + +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define PINMUX_GPIO150__FUNC_CLKM1 (MTK_PIN_NO(150) | 2) +#define PINMUX_GPIO150__FUNC_DPI_DATA15 (MTK_PIN_NO(150) | 3) +#define PINMUX_GPIO150__FUNC_TP_GPIO3_AO (MTK_PIN_NO(150) | 4) +#define PINMUX_GPIO150__FUNC_ANT_SEL6 (MTK_PIN_NO(150) | 5) +#define PINMUX_GPIO150__FUNC_DFD_TDO (MTK_PIN_NO(150) | 6) +#define PINMUX_GPIO150__FUNC_DBG_MON_B23 (MTK_PIN_NO(150) | 7) + +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define PINMUX_GPIO151__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(151) | 1) +#define PINMUX_GPIO151__FUNC_CLKM2 (MTK_PIN_NO(151) | 2) +#define PINMUX_GPIO151__FUNC_DPI_DATA16 (MTK_PIN_NO(151) | 3) +#define PINMUX_GPIO151__FUNC_TP_GPIO4_AO (MTK_PIN_NO(151) | 4) +#define PINMUX_GPIO151__FUNC_ANT_SEL7 (MTK_PIN_NO(151) | 5) +#define PINMUX_GPIO151__FUNC_UDI_TMS (MTK_PIN_NO(151) | 6) +#define PINMUX_GPIO151__FUNC_DBG_MON_B24 (MTK_PIN_NO(151) | 7) + +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define PINMUX_GPIO152__FUNC_CLKM3 (MTK_PIN_NO(152) | 2) +#define PINMUX_GPIO152__FUNC_DPI_DATA17 (MTK_PIN_NO(152) | 3) +#define PINMUX_GPIO152__FUNC_TP_GPIO5_AO (MTK_PIN_NO(152) | 4) + +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define PINMUX_GPIO153__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(153) | 1) +#define PINMUX_GPIO153__FUNC_DPI_DATA18 (MTK_PIN_NO(153) | 3) +#define PINMUX_GPIO153__FUNC_TP_GPIO6_AO (MTK_PIN_NO(153) | 4) +#define PINMUX_GPIO153__FUNC_UDI_TDI (MTK_PIN_NO(153) | 6) +#define PINMUX_GPIO153__FUNC_DBG_MON_B26 (MTK_PIN_NO(153) | 7) + +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define PINMUX_GPIO154__FUNC_PWM0 (MTK_PIN_NO(154) | 1) +#define PINMUX_GPIO154__FUNC_CMVREF2 (MTK_PIN_NO(154) | 2) +#define PINMUX_GPIO154__FUNC_DPI_DATA19 (MTK_PIN_NO(154) | 3) +#define PINMUX_GPIO154__FUNC_TP_GPIO7_AO (MTK_PIN_NO(154) | 4) +#define PINMUX_GPIO154__FUNC_UDI_TDO (MTK_PIN_NO(154) | 6) +#define PINMUX_GPIO154__FUNC_DBG_MON_B27 (MTK_PIN_NO(154) | 7) + +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define PINMUX_GPIO155__FUNC_PWM1 (MTK_PIN_NO(155) | 1) +#define PINMUX_GPIO155__FUNC_CMVREF1 (MTK_PIN_NO(155) | 2) +#define PINMUX_GPIO155__FUNC_DPI_DATA20 (MTK_PIN_NO(155) | 3) +#define PINMUX_GPIO155__FUNC_UDI_NTRST (MTK_PIN_NO(155) | 6) +#define PINMUX_GPIO155__FUNC_DBG_MON_B28 (MTK_PIN_NO(155) | 7) + +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define PINMUX_GPIO156__FUNC_PWM2 (MTK_PIN_NO(156) | 1) +#define PINMUX_GPIO156__FUNC_CMVREF0 (MTK_PIN_NO(156) | 2) +#define PINMUX_GPIO156__FUNC_DPI_DATA21 (MTK_PIN_NO(156) | 3) + +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define PINMUX_GPIO157__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(157) | 1) + +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define PINMUX_GPIO158__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(158) | 1) + +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define PINMUX_GPIO159__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(159) | 1) +#define PINMUX_GPIO159__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(159) | 2) + +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define PINMUX_GPIO160__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(160) | 1) +#define PINMUX_GPIO160__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(160) | 2) + +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define PINMUX_GPIO161__FUNC_SRCLKENA0 (MTK_PIN_NO(161) | 1) + +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define PINMUX_GPIO162__FUNC_SRCLKENA1 (MTK_PIN_NO(162) | 1) +#define PINMUX_GPIO162__FUNC_DBG_MON_A31 (MTK_PIN_NO(162) | 7) + +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define PINMUX_GPIO163__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(163) | 1) +#define PINMUX_GPIO163__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(163) | 2) + +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define PINMUX_GPIO164__FUNC_RTC32K_CK (MTK_PIN_NO(164) | 1) + +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define PINMUX_GPIO165__FUNC_WATCHDOG (MTK_PIN_NO(165) | 1) + +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define PINMUX_GPIO166__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(166) | 1) +#define PINMUX_GPIO166__FUNC_AUD_CLK_MISO (MTK_PIN_NO(166) | 2) +#define PINMUX_GPIO166__FUNC_I2S1_MCK (MTK_PIN_NO(166) | 3) + +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define PINMUX_GPIO167__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(167) | 1) +#define PINMUX_GPIO167__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(167) | 2) +#define PINMUX_GPIO167__FUNC_I2S1_BCK (MTK_PIN_NO(167) | 3) + +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define PINMUX_GPIO168__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(168) | 1) +#define PINMUX_GPIO168__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(168) | 2) +#define PINMUX_GPIO168__FUNC_I2S1_LRCK (MTK_PIN_NO(168) | 3) + +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define PINMUX_GPIO169__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(169) | 1) +#define PINMUX_GPIO169__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(169) | 2) +#define PINMUX_GPIO169__FUNC_I2S1_DO (MTK_PIN_NO(169) | 3) + +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define PINMUX_GPIO170__FUNC_AUD_CLK_MISO (MTK_PIN_NO(170) | 1) +#define PINMUX_GPIO170__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(170) | 2) +#define PINMUX_GPIO170__FUNC_I2S2_MCK (MTK_PIN_NO(170) | 3) + +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define PINMUX_GPIO171__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(171) | 1) +#define PINMUX_GPIO171__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(171) | 2) +#define PINMUX_GPIO171__FUNC_I2S2_BCK (MTK_PIN_NO(171) | 3) + +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define PINMUX_GPIO172__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(172) | 1) +#define PINMUX_GPIO172__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(172) | 2) +#define PINMUX_GPIO172__FUNC_I2S2_LRCK (MTK_PIN_NO(172) | 3) +#define PINMUX_GPIO172__FUNC_VOW_DAT_MISO (MTK_PIN_NO(172) | 4) + +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define PINMUX_GPIO173__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(173) | 1) +#define PINMUX_GPIO173__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(173) | 2) +#define PINMUX_GPIO173__FUNC_I2S2_DI (MTK_PIN_NO(173) | 3) +#define PINMUX_GPIO173__FUNC_VOW_CLK_MISO (MTK_PIN_NO(173) | 4) + +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define PINMUX_GPIO174__FUNC_CONN_TOP_CLK (MTK_PIN_NO(174) | 1) +#define PINMUX_GPIO174__FUNC_AUXIF_CLK (MTK_PIN_NO(174) | 2) +#define PINMUX_GPIO174__FUNC_DFD_TCK_XI (MTK_PIN_NO(174) | 3) +#define PINMUX_GPIO174__FUNC_DBG_MON_B3 (MTK_PIN_NO(174) | 7) + +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define PINMUX_GPIO175__FUNC_CONN_TOP_DATA (MTK_PIN_NO(175) | 1) +#define PINMUX_GPIO175__FUNC_AUXIF_ST (MTK_PIN_NO(175) | 2) +#define PINMUX_GPIO175__FUNC_DFD_TMS (MTK_PIN_NO(175) | 3) +#define PINMUX_GPIO175__FUNC_DBG_MON_B15 (MTK_PIN_NO(175) | 7) + +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define PINMUX_GPIO176__FUNC_CONN_BT_CLK (MTK_PIN_NO(176) | 1) +#define PINMUX_GPIO176__FUNC_DFD_TDI (MTK_PIN_NO(176) | 3) +#define PINMUX_GPIO176__FUNC_DBG_MON_B2 (MTK_PIN_NO(176) | 7) + +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define PINMUX_GPIO177__FUNC_CONN_BT_DATA (MTK_PIN_NO(177) | 1) +#define PINMUX_GPIO177__FUNC_DFD_TDO (MTK_PIN_NO(177) | 3) + +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define PINMUX_GPIO178__FUNC_CONN_HRST_B (MTK_PIN_NO(178) | 1) +#define PINMUX_GPIO178__FUNC_UDI_TMS (MTK_PIN_NO(178) | 3) +#define PINMUX_GPIO178__FUNC_DBG_MON_B25 (MTK_PIN_NO(178) | 7) + +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define PINMUX_GPIO179__FUNC_CONN_WB_PTA (MTK_PIN_NO(179) | 1) +#define PINMUX_GPIO179__FUNC_UDI_TCK (MTK_PIN_NO(179) | 3) +#define PINMUX_GPIO179__FUNC_DBG_MON_B29 (MTK_PIN_NO(179) | 7) + +#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define PINMUX_GPIO180__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(180) | 1) +#define PINMUX_GPIO180__FUNC_UDI_TDI (MTK_PIN_NO(180) | 3) + +#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define PINMUX_GPIO181__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(181) | 1) +#define PINMUX_GPIO181__FUNC_UDI_TDO (MTK_PIN_NO(181) | 3) + +#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define PINMUX_GPIO182__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(182) | 1) +#define PINMUX_GPIO182__FUNC_UDI_NTRST (MTK_PIN_NO(182) | 3) + +#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define PINMUX_GPIO183__FUNC_SPMI_SCL (MTK_PIN_NO(183) | 1) + +#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define PINMUX_GPIO184__FUNC_SPMI_SDA (MTK_PIN_NO(184) | 1) + +#endif /* __MT8186_PINFUNC_H */ diff --git a/include/dt-bindings/pinctrl/sppctl-sp7021.h b/include/dt-bindings/pinctrl/sppctl-sp7021.h new file mode 100644 index 000000000000..629aa9b5ffbc --- /dev/null +++ b/include/dt-bindings/pinctrl/sppctl-sp7021.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Sunplus SP7021 dt-bindings Pinctrl header file + * Copyright (C) Sunplus Tech/Tibbo Tech. + * Author: Dvorkin Dmitry <dvorkin@tibbo.com> + */ + +#ifndef __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__ +#define __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__ + +#include <dt-bindings/pinctrl/sppctl.h> + +/* + * Please don't change the order of the following defines. + * They are based on order of 'hardware' control register + * defined in MOON2 ~ MOON3 registers. + */ +#define MUXF_GPIO 0 +#define MUXF_IOP 1 +#define MUXF_L2SW_CLK_OUT 2 +#define MUXF_L2SW_MAC_SMI_MDC 3 +#define MUXF_L2SW_LED_FLASH0 4 +#define MUXF_L2SW_LED_FLASH1 5 +#define MUXF_L2SW_LED_ON0 6 +#define MUXF_L2SW_LED_ON1 7 +#define MUXF_L2SW_MAC_SMI_MDIO 8 +#define MUXF_L2SW_P0_MAC_RMII_TXEN 9 +#define MUXF_L2SW_P0_MAC_RMII_TXD0 10 +#define MUXF_L2SW_P0_MAC_RMII_TXD1 11 +#define MUXF_L2SW_P0_MAC_RMII_CRSDV 12 +#define MUXF_L2SW_P0_MAC_RMII_RXD0 13 +#define MUXF_L2SW_P0_MAC_RMII_RXD1 14 +#define MUXF_L2SW_P0_MAC_RMII_RXER 15 +#define MUXF_L2SW_P1_MAC_RMII_TXEN 16 +#define MUXF_L2SW_P1_MAC_RMII_TXD0 17 +#define MUXF_L2SW_P1_MAC_RMII_TXD1 18 +#define MUXF_L2SW_P1_MAC_RMII_CRSDV 19 +#define MUXF_L2SW_P1_MAC_RMII_RXD0 20 +#define MUXF_L2SW_P1_MAC_RMII_RXD1 21 +#define MUXF_L2SW_P1_MAC_RMII_RXER 22 +#define MUXF_DAISY_MODE 23 +#define MUXF_SDIO_CLK 24 +#define MUXF_SDIO_CMD 25 +#define MUXF_SDIO_D0 26 +#define MUXF_SDIO_D1 27 +#define MUXF_SDIO_D2 28 +#define MUXF_SDIO_D3 29 +#define MUXF_PWM0 30 +#define MUXF_PWM1 31 +#define MUXF_PWM2 32 +#define MUXF_PWM3 33 +#define MUXF_PWM4 34 +#define MUXF_PWM5 35 +#define MUXF_PWM6 36 +#define MUXF_PWM7 37 +#define MUXF_ICM0_D 38 +#define MUXF_ICM1_D 39 +#define MUXF_ICM2_D 40 +#define MUXF_ICM3_D 41 +#define MUXF_ICM0_CLK 42 +#define MUXF_ICM1_CLK 43 +#define MUXF_ICM2_CLK 44 +#define MUXF_ICM3_CLK 45 +#define MUXF_SPIM0_INT 46 +#define MUXF_SPIM0_CLK 47 +#define MUXF_SPIM0_EN 48 +#define MUXF_SPIM0_DO 49 +#define MUXF_SPIM0_DI 50 +#define MUXF_SPIM1_INT 51 +#define MUXF_SPIM1_CLK 52 +#define MUXF_SPIM1_EN 53 +#define MUXF_SPIM1_DO 54 +#define MUXF_SPIM1_DI 55 +#define MUXF_SPIM2_INT 56 +#define MUXF_SPIM2_CLK 57 +#define MUXF_SPIM2_EN 58 +#define MUXF_SPIM2_DO 59 +#define MUXF_SPIM2_DI 60 +#define MUXF_SPIM3_INT 61 +#define MUXF_SPIM3_CLK 62 +#define MUXF_SPIM3_EN 63 +#define MUXF_SPIM3_DO 64 +#define MUXF_SPIM3_DI 65 +#define MUXF_SPI0S_INT 66 +#define MUXF_SPI0S_CLK 67 +#define MUXF_SPI0S_EN 68 +#define MUXF_SPI0S_DO 69 +#define MUXF_SPI0S_DI 70 +#define MUXF_SPI1S_INT 71 +#define MUXF_SPI1S_CLK 72 +#define MUXF_SPI1S_EN 73 +#define MUXF_SPI1S_DO 74 +#define MUXF_SPI1S_DI 75 +#define MUXF_SPI2S_INT 76 +#define MUXF_SPI2S_CLK 77 +#define MUXF_SPI2S_EN 78 +#define MUXF_SPI2S_DO 79 +#define MUXF_SPI2S_DI 80 +#define MUXF_SPI3S_INT 81 +#define MUXF_SPI3S_CLK 82 +#define MUXF_SPI3S_EN 83 +#define MUXF_SPI3S_DO 84 +#define MUXF_SPI3S_DI 85 +#define MUXF_I2CM0_CLK 86 +#define MUXF_I2CM0_DAT 87 +#define MUXF_I2CM1_CLK 88 +#define MUXF_I2CM1_DAT 89 +#define MUXF_I2CM2_CLK 90 +#define MUXF_I2CM2_DAT 91 +#define MUXF_I2CM3_CLK 92 +#define MUXF_I2CM3_DAT 93 +#define MUXF_UA1_TX 94 +#define MUXF_UA1_RX 95 +#define MUXF_UA1_CTS 96 +#define MUXF_UA1_RTS 97 +#define MUXF_UA2_TX 98 +#define MUXF_UA2_RX 99 +#define MUXF_UA2_CTS 100 +#define MUXF_UA2_RTS 101 +#define MUXF_UA3_TX 102 +#define MUXF_UA3_RX 103 +#define MUXF_UA3_CTS 104 +#define MUXF_UA3_RTS 105 +#define MUXF_UA4_TX 106 +#define MUXF_UA4_RX 107 +#define MUXF_UA4_CTS 108 +#define MUXF_UA4_RTS 109 +#define MUXF_TIMER0_INT 110 +#define MUXF_TIMER1_INT 111 +#define MUXF_TIMER2_INT 112 +#define MUXF_TIMER3_INT 113 +#define MUXF_GPIO_INT0 114 +#define MUXF_GPIO_INT1 115 +#define MUXF_GPIO_INT2 116 +#define MUXF_GPIO_INT3 117 +#define MUXF_GPIO_INT4 118 +#define MUXF_GPIO_INT5 119 +#define MUXF_GPIO_INT6 120 +#define MUXF_GPIO_INT7 121 + +/* + * Please don't change the order of the following defines. + * They are based on order of items in array 'sppctl_list_funcs' + * in Sunplus pinctrl driver. + */ +#define GROP_SPI_FLASH 122 +#define GROP_SPI_FLASH_4BIT 123 +#define GROP_SPI_NAND 124 +#define GROP_CARD0_EMMC 125 +#define GROP_SD_CARD 126 +#define GROP_UA0 127 +#define GROP_ACHIP_DEBUG 128 +#define GROP_ACHIP_UA2AXI 129 +#define GROP_FPGA_IFX 130 +#define GROP_HDMI_TX 131 +#define GROP_AUD_EXT_ADC_IFX0 132 +#define GROP_AUD_EXT_DAC_IFX0 133 +#define GROP_SPDIF_RX 134 +#define GROP_SPDIF_TX 135 +#define GROP_TDMTX_IFX0 136 +#define GROP_TDMRX_IFX0 137 +#define GROP_PDMRX_IFX0 138 +#define GROP_PCM_IEC_TX 139 +#define GROP_LCDIF 140 +#define GROP_DVD_DSP_DEBUG 141 +#define GROP_I2C_DEBUG 142 +#define GROP_I2C_SLAVE 143 +#define GROP_WAKEUP 144 +#define GROP_UART2AXI 145 +#define GROP_USB0_I2C 146 +#define GROP_USB1_I2C 147 +#define GROP_USB0_OTG 148 +#define GROP_USB1_OTG 149 +#define GROP_UPHY0_DEBUG 150 +#define GROP_UPHY1_DEBUG 151 +#define GROP_UPHY0_EXT 152 +#define GROP_PROBE_PORT 153 + +#endif diff --git a/include/dt-bindings/pinctrl/sppctl.h b/include/dt-bindings/pinctrl/sppctl.h new file mode 100644 index 000000000000..50557265dbfc --- /dev/null +++ b/include/dt-bindings/pinctrl/sppctl.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Sunplus dt-bindings Pinctrl header file + * Copyright (C) Sunplus Tech / Tibbo Tech. + * Author: Dvorkin Dmitry <dvorkin@tibbo.com> + */ + +#ifndef __DT_BINDINGS_PINCTRL_SPPCTL_H__ +#define __DT_BINDINGS_PINCTRL_SPPCTL_H__ + +#define IOP_G_MASTE (0x01 << 0) +#define IOP_G_FIRST (0x01 << 1) + +#define SPPCTL_PCTL_G_PMUX (0x00 | IOP_G_MASTE) +#define SPPCTL_PCTL_G_GPIO (IOP_G_FIRST | IOP_G_MASTE) +#define SPPCTL_PCTL_G_IOPP (IOP_G_FIRST | 0x00) + +#define SPPCTL_PCTL_L_OUT (0x01 << 0) /* Output LOW */ +#define SPPCTL_PCTL_L_OU1 (0x01 << 1) /* Output HIGH */ +#define SPPCTL_PCTL_L_INV (0x01 << 2) /* Input Invert */ +#define SPPCTL_PCTL_L_ONV (0x01 << 3) /* Output Invert */ +#define SPPCTL_PCTL_L_ODR (0x01 << 4) /* Output Open Drain */ + +/* + * pack into 32-bit value: + * pin# (8bit), typ (8bit), function (8bit), flag (8bit) + */ +#define SPPCTL_IOPAD(pin, typ, fun, flg) (((pin) << 24) | ((typ) << 16) | \ + ((fun) << 8) | (flg)) + +#endif |