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author | Guo Ren <ren_guo@c-sky.com> | 2018-11-02 17:51:29 +0100 |
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committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2018-11-02 19:41:05 +0100 |
commit | 732e5dca374d764bd9711c8c121b0e18ff92985e (patch) | |
tree | 4fc3014905e3c7978a77839d3c3ca2a8991cad62 | |
parent | clocksource/drivers/c-sky: Add C-SKY SMP timer (diff) | |
download | linux-732e5dca374d764bd9711c8c121b0e18ff92985e.tar.xz linux-732e5dca374d764bd9711c8c121b0e18ff92985e.zip |
dt-bindings: timer: C-SKY Multi-processor timer
Dt-bingdings doc for C-SKY SMP system setting.
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-rw-r--r-- | Documentation/devicetree/bindings/timer/csky,mptimer.txt | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/timer/csky,mptimer.txt b/Documentation/devicetree/bindings/timer/csky,mptimer.txt new file mode 100644 index 000000000000..15cfec08fbb8 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/csky,mptimer.txt @@ -0,0 +1,42 @@ +============================ +C-SKY Multi-processors Timer +============================ + +C-SKY multi-processors timer is designed for C-SKY SMP system and the +regs is accessed by cpu co-processor 4 registers with mtcr/mfcr. + + - PTIM_CTLR "cr<0, 14>" Control reg to start reset timer. + - PTIM_TSR "cr<1, 14>" Interrupt cleanup status reg. + - PTIM_CCVR "cr<3, 14>" Current counter value reg. + - PTIM_LVR "cr<6, 14>" Window value reg to triger next event. + +============================== +timer node bindings definition +============================== + + Description: Describes SMP timer + + PROPERTIES + + - compatible + Usage: required + Value type: <string> + Definition: must be "csky,mptimer" + - clocks + Usage: required + Value type: <node> + Definition: must be input clk node + - interrupts + Usage: required + Value type: <u32> + Definition: must be timer irq num defined by soc + +Examples: +--------- + + timer: timer { + compatible = "csky,mptimer"; + clocks = <&dummy_apb_clk>; + interrupts = <16>; + interrupt-parent = <&intc>; + }; |