diff options
| author | Thiemo Seufer <ths@networkno.de> | 2007-09-05 18:44:50 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-12 00:46:03 +0200 |
| commit | bcb0fd94633afde9c1f4f8aca43141ba2c78f04b (patch) | |
| tree | 690cb6b8f61e05eaa50ea36ce809507fbacdf1ae | |
| parent | [MIPS] floppy: Rewrite fd_cacheflush() to use dma_cache_sync(). (diff) | |
| download | linux-bcb0fd94633afde9c1f4f8aca43141ba2c78f04b.tar.xz linux-bcb0fd94633afde9c1f4f8aca43141ba2c78f04b.zip | |
[MIPS] Define known MIPS ISA overrides for Sibyte and Excite boards.
Signed-Off-By: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | include/asm-mips/mach-excite/cpu-feature-overrides.h | 5 | ||||
| -rw-r--r-- | include/asm-mips/mach-sibyte/cpu-feature-overrides.h | 7 |
2 files changed, 11 insertions, 1 deletions
diff --git a/include/asm-mips/mach-excite/cpu-feature-overrides.h b/include/asm-mips/mach-excite/cpu-feature-overrides.h index 07f4322c235d..107104c3cd12 100644 --- a/include/asm-mips/mach-excite/cpu-feature-overrides.h +++ b/include/asm-mips/mach-excite/cpu-feature-overrides.h @@ -34,6 +34,11 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + #define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h index 63d5bf649af1..1c1f92415b9a 100644 --- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h +++ b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h @@ -9,7 +9,7 @@ #define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H /* - * Sibyte are MIPS64 processors weired to a specific configuration + * Sibyte are MIPS64 processors wired to a specific configuration */ #define cpu_has_watch 1 #define cpu_has_mips16 0 @@ -33,6 +33,11 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 1 +#define cpu_has_mips64r2 0 + #define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 |