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| author | Guoxiong Yan <yanguoxiong@huawei.com> | 2014-06-17 11:04:17 +0200 |
|---|---|---|
| committer | Wei Xu <xuwei5@hisilicon.com> | 2014-09-28 04:27:04 +0200 |
| commit | 1463fba39c2e95803147e1d6e159ea402d965e6f (patch) | |
| tree | e840afc00db1d1c6ddcd5a0a6c64c144ac449481 | |
| parent | clk: hix5hd2: add sd clk (diff) | |
| download | linux-1463fba39c2e95803147e1d6e159ea402d965e6f.tar.xz linux-1463fba39c2e95803147e1d6e159ea402d965e6f.zip | |
clk: hix5hd2: add watchdog0 clocks
hix5hd2 add watchdog0 clocks
Signed-off-by: Guoxiong Yan <yanguoxiong@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| -rw-r--r-- | drivers/clk/hisilicon/clk-hix5hd2.c | 5 | ||||
| -rw-r--r-- | include/dt-bindings/clock/hix5hd2-clock.h | 2 |
2 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c b/drivers/clk/hisilicon/clk-hix5hd2.c index 13d6ec24af12..6e97e54b869c 100644 --- a/drivers/clk/hisilicon/clk-hix5hd2.c +++ b/drivers/clk/hisilicon/clk-hix5hd2.c @@ -95,6 +95,11 @@ static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata = { { HIX5HD2_FWD_SYS_CLK, "clk_fwd_sys", "clk_fwd_bus", 0, 0xcc, 5, 0, }, { HIX5HD2_MAC0_PHY_CLK, "clk_fephy", "clk_fwd_sys", CLK_SET_RATE_PARENT, 0x120, 0, 0, }, + /* wdg0 */ + { HIX5HD2_WDG0_CLK, "clk_wdg0", "24m", + CLK_SET_RATE_PARENT, 0x178, 0, 0, }, + { HIX5HD2_WDG0_RST, "rst_wdg0", "clk_wdg0", + CLK_SET_RATE_PARENT, 0x178, 4, CLK_GATE_SET_TO_DISABLE, }, }; enum hix5hd2_clk_type { diff --git a/include/dt-bindings/clock/hix5hd2-clock.h b/include/dt-bindings/clock/hix5hd2-clock.h index 5bd4135c9544..b8e3c9deda20 100644 --- a/include/dt-bindings/clock/hix5hd2-clock.h +++ b/include/dt-bindings/clock/hix5hd2-clock.h @@ -60,6 +60,8 @@ #define HIX5HD2_SD_CIU_CLK 136 #define HIX5HD2_SD_BIU_CLK 137 #define HIX5HD2_SD_CIU_RST 138 +#define HIX5HD2_WDG0_CLK 139 +#define HIX5HD2_WDG0_RST 140 /* complex */ #define HIX5HD2_MAC0_CLK 192 |