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authorColin Cross <ccross@android.com>2011-06-06 22:38:17 +0200
committerKevin Hilman <khilman@ti.com>2011-06-07 01:12:23 +0200
commit0622b25bf071fd83c6eef6b61fb5f3f12a418528 (patch)
treeb94745ded735e4347ee37b51e5e382e3a6d81432
parentGPIO: OMAP: fix section mismatch warnings (diff)
downloadlinux-0622b25bf071fd83c6eef6b61fb5f3f12a418528.tar.xz
linux-0622b25bf071fd83c6eef6b61fb5f3f12a418528.zip
GPIO: OMAP: fix setting IRQWAKEN bits for OMAP4
Setting the IRQWAKEN bit was overwriting previous IRQWAKEN bits, causing only the last bit set to take effect, resulting in lost wakeups when the GPIO controller is in idle. Replace direct writes to IRQWAKEN with MOD_REG_BIT calls to perform a read-modify-write on the register. Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
-rw-r--r--drivers/gpio/gpio-omap.c12
1 files changed, 2 insertions, 10 deletions
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 76709b03572e..5ad827a1a3e8 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -432,7 +432,6 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
{
void __iomem *base = bank->base;
u32 gpio_bit = 1 << gpio;
- u32 val;
if (cpu_is_omap44xx()) {
MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
@@ -455,15 +454,8 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
}
if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
if (cpu_is_omap44xx()) {
- if (trigger != 0)
- __raw_writel(1 << gpio, bank->base+
- OMAP4_GPIO_IRQWAKEN0);
- else {
- val = __raw_readl(bank->base +
- OMAP4_GPIO_IRQWAKEN0);
- __raw_writel(val & (~(1 << gpio)), bank->base +
- OMAP4_GPIO_IRQWAKEN0);
- }
+ MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
+ trigger != 0);
} else {
/*
* GPIO wakeup request can only be generated on edge