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authorRandy Dunlap <rdunlap@infradead.org>2023-01-27 07:39:57 +0100
committerMark Brown <broonie@kernel.org>2023-01-27 13:14:17 +0100
commit0f6d2cee58f1ff2ebf66f0bceb113d79f66ecb07 (patch)
tree932dd6f8717ec5da8da5b8160965544835976079
parentspi: Kconfig: fix a spelling mistake & hyphenation (diff)
downloadlinux-0f6d2cee58f1ff2ebf66f0bceb113d79f66ecb07.tar.xz
linux-0f6d2cee58f1ff2ebf66f0bceb113d79f66ecb07.zip
spi: correct spelling
Correct spelling problems for Documentation/spi/ as reported by codespell. Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Link: https://lore.kernel.org/r/20230127064005.1558-28-rdunlap@infradead.org Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--Documentation/spi/pxa2xx.rst12
-rw-r--r--Documentation/spi/spi-lm70llp.rst2
-rw-r--r--Documentation/spi/spi-summary.rst2
3 files changed, 8 insertions, 8 deletions
diff --git a/Documentation/spi/pxa2xx.rst b/Documentation/spi/pxa2xx.rst
index 716f65d87d04..04f2a3856c40 100644
--- a/Documentation/spi/pxa2xx.rst
+++ b/Documentation/spi/pxa2xx.rst
@@ -141,15 +141,15 @@ field. Below is a sample configuration using the PXA255 NSSP.
::
static struct pxa2xx_spi_chip cs8415a_chip_info = {
- .tx_threshold = 8, /* SSP hardward FIFO threshold */
- .rx_threshold = 8, /* SSP hardward FIFO threshold */
+ .tx_threshold = 8, /* SSP hardware FIFO threshold */
+ .rx_threshold = 8, /* SSP hardware FIFO threshold */
.dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
.timeout = 235, /* See Intel documentation */
};
static struct pxa2xx_spi_chip cs8405a_chip_info = {
- .tx_threshold = 8, /* SSP hardward FIFO threshold */
- .rx_threshold = 8, /* SSP hardward FIFO threshold */
+ .tx_threshold = 8, /* SSP hardware FIFO threshold */
+ .rx_threshold = 8, /* SSP hardware FIFO threshold */
.dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
.timeout = 235, /* See Intel documentation */
};
@@ -157,7 +157,7 @@ field. Below is a sample configuration using the PXA255 NSSP.
static struct spi_board_info streetracer_spi_board_info[] __initdata = {
{
.modalias = "cs8415a", /* Name of spi_driver for this device */
- .max_speed_hz = 3686400, /* Run SSP as fast a possbile */
+ .max_speed_hz = 3686400, /* Run SSP as fast a possible */
.bus_num = 2, /* Framework bus number */
.chip_select = 0, /* Framework chip select */
.platform_data = NULL; /* No spi_driver specific config */
@@ -166,7 +166,7 @@ field. Below is a sample configuration using the PXA255 NSSP.
},
{
.modalias = "cs8405a", /* Name of spi_driver for this device */
- .max_speed_hz = 3686400, /* Run SSP as fast a possbile */
+ .max_speed_hz = 3686400, /* Run SSP as fast a possible */
.bus_num = 2, /* Framework bus number */
.chip_select = 1, /* Framework chip select */
.controller_data = &cs8405a_chip_info, /* Master chip config */
diff --git a/Documentation/spi/spi-lm70llp.rst b/Documentation/spi/spi-lm70llp.rst
index 07631aef4343..0144e12d95bb 100644
--- a/Documentation/spi/spi-lm70llp.rst
+++ b/Documentation/spi/spi-lm70llp.rst
@@ -57,7 +57,7 @@ devices might share the same SI/SO pin.
The bitbanger routine in this driver (lm70_txrx) is called back from
the bound "hwmon/lm70" protocol driver through its sysfs hook, using a
spi_write_then_read() call. It performs Mode 0 (SPI/Microwire) bitbanging.
-The lm70 driver then inteprets the resulting digital temperature value
+The lm70 driver then interprets the resulting digital temperature value
and exports it through sysfs.
A "gotcha": National Semiconductor's LM70 LLP eval board circuit schematic
diff --git a/Documentation/spi/spi-summary.rst b/Documentation/spi/spi-summary.rst
index aab5d07cb3d7..3c95ae322fb1 100644
--- a/Documentation/spi/spi-summary.rst
+++ b/Documentation/spi/spi-summary.rst
@@ -105,7 +105,7 @@ find isn't necessarily helpful. The four modes combine two mode bits:
- CPHA indicates the clock phase used to sample data; CPHA=0 says
sample on the leading edge, CPHA=1 means the trailing edge.
- Since the signal needs to stablize before it's sampled, CPHA=0
+ Since the signal needs to stabilize before it's sampled, CPHA=0
implies that its data is written half a clock before the first
clock edge. The chipselect may have made it become available.