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| author | Will Deacon <will.deacon@arm.com> | 2018-11-07 23:58:24 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2018-12-10 15:55:58 +0100 |
| commit | a868e8530441286342f90c1fd9c5f24de3aa2880 (patch) | |
| tree | e7cdacc6b471fb766357a0a842b8f5dd1bcba33e | |
| parent | iommu/arm-smmu-v3: Avoid memory corruption from Hisilicon MSI payloads (diff) | |
| download | linux-a868e8530441286342f90c1fd9c5f24de3aa2880.tar.xz linux-a868e8530441286342f90c1fd9c5f24de3aa2880.zip | |
iommu/arm-smmu-v3: Use explicit mb() when moving cons pointer
After removing an entry from a queue (e.g. reading an event in
arm_smmu_evtq_thread()) it is necessary to advance the MMIO consumer
pointer to free the queue slot back to the SMMU. A memory barrier is
required here so that all reads targetting the queue entry have
completed before the consumer pointer is updated.
The implementation of queue_inc_cons() relies on a writel() to complete
the previous reads, but this is incorrect because writel() is only
guaranteed to complete prior writes. This patch replaces the call to
writel() with an mb(); writel_relaxed() sequence, which gives us the
read->write ordering which we require.
Cc: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
| -rw-r--r-- | drivers/iommu/arm-smmu-v3.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 62ef4afc9ee5..11f528e727a1 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -679,7 +679,13 @@ static void queue_inc_cons(struct arm_smmu_queue *q) u32 cons = (Q_WRP(q, q->cons) | Q_IDX(q, q->cons)) + 1; q->cons = Q_OVF(q, q->cons) | Q_WRP(q, cons) | Q_IDX(q, cons); - writel(q->cons, q->cons_reg); + + /* + * Ensure that all CPU accesses (reads and writes) to the queue + * are complete before we update the cons pointer. + */ + mb(); + writel_relaxed(q->cons, q->cons_reg); } static int queue_sync_prod(struct arm_smmu_queue *q) |