diff options
| author | Ben Widawsky <benjamin.widawsky@intel.com> | 2013-11-25 18:54:32 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-11-26 09:59:05 +0100 |
| commit | d595bd4bbd853106e3926176fa8a677963337d38 (patch) | |
| tree | 116545905aa61458da93b2b2476cedea650fa088 | |
| parent | drm/i915: Don't set the fence number in DPFC_CTL on SNB (diff) | |
| download | linux-d595bd4bbd853106e3926176fa8a677963337d38.tar.xz linux-d595bd4bbd853106e3926176fa8a677963337d38.zip | |
drm/i915: Fix BDW PPGTT error path
When we fail for some reason on loading the PDPs, it would be wise to
disable the PPGTT in the ring registers. If we do not do this, we have
undefined results.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_gtt.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index efb5dab61c81..1a5272c172c8 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -238,10 +238,16 @@ static int gen8_ppgtt_enable(struct drm_device *dev) for_each_ring(ring, dev_priv, j) { ret = gen8_write_pdp(ring, i, addr); if (ret) - return ret; + goto err_out; } } return 0; + +err_out: + for_each_ring(ring, dev_priv, j) + I915_WRITE(RING_MODE_GEN7(ring), + _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE)); + return ret; } static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |