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authorMarkos Chandras <markos.chandras@imgtec.com>2014-11-24 15:40:11 +0100
committerMarkos Chandras <markos.chandras@imgtec.com>2015-02-17 16:37:28 +0100
commitacac4108df6029c03195513ead7073bbb0cb9718 (patch)
treeb30726d60d92ea454fd94fcd8c479fe7c07ac257
parentMIPS: kernel: genex: Set correct ISA level (diff)
downloadlinux-acac4108df6029c03195513ead7073bbb0cb9718.tar.xz
linux-acac4108df6029c03195513ead7073bbb0cb9718.zip
MIPS: kernel: cps-vec: Replace "addi" with "addiu"
The "addi" instruction will trap on overflows which is not something we need in this code, so we replace that with "addiu". Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00430.html Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: <stable@vger.kernel.org> # v3.15+ Cc: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
-rw-r--r--arch/mips/kernel/cps-vec.S16
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 0384b05ab5a0..55b759a0019e 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -99,11 +99,11 @@ not_nmi:
xori t2, t1, 0x7
beqz t2, 1f
li t3, 32
- addi t1, t1, 1
+ addiu t1, t1, 1
sllv t1, t3, t1
1: /* At this point t1 == I-cache sets per way */
_EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
- addi t2, t2, 1
+ addiu t2, t2, 1
mul t1, t1, t0
mul t1, t1, t2
@@ -126,11 +126,11 @@ icache_done:
xori t2, t1, 0x7
beqz t2, 1f
li t3, 32
- addi t1, t1, 1
+ addiu t1, t1, 1
sllv t1, t3, t1
1: /* At this point t1 == D-cache sets per way */
_EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
- addi t2, t2, 1
+ addiu t2, t2, 1
mul t1, t1, t0
mul t1, t1, t2
@@ -250,7 +250,7 @@ LEAF(mips_cps_core_init)
mfc0 t0, CP0_MVPCONF0
srl t0, t0, MVPCONF0_PVPE_SHIFT
andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
- addi t7, t0, 1
+ addiu t7, t0, 1
/* If there's only 1, we're done */
beqz t0, 2f
@@ -280,7 +280,7 @@ LEAF(mips_cps_core_init)
mttc0 t0, CP0_TCHALT
/* Next VPE */
- addi t5, t5, 1
+ addiu t5, t5, 1
slt t0, t5, t7
bnez t0, 1b
nop
@@ -317,7 +317,7 @@ LEAF(mips_cps_boot_vpes)
mfc0 t1, CP0_MVPCONF0
srl t1, t1, MVPCONF0_PVPE_SHIFT
andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
- addi t1, t1, 1
+ addiu t1, t1, 1
/* Calculate a mask for the VPE ID from EBase.CPUNum */
clz t1, t1
@@ -424,7 +424,7 @@ LEAF(mips_cps_boot_vpes)
/* Next VPE */
2: srl t6, t6, 1
- addi t5, t5, 1
+ addiu t5, t5, 1
bnez t6, 1b
nop