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authorChen-Yu Tsai <wens@csie.org>2018-09-06 17:33:04 +0200
committerUlf Hansson <ulf.hansson@linaro.org>2018-10-08 11:40:43 +0200
commit07bafc1e3536a4e3c422dbd13341688b54f159bb (patch)
treebce8700fe068325b9c317ae3d1782b637adf5706
parentmmc: sunxi: Clarify new timing mode usage and implementation (diff)
downloadlinux-07bafc1e3536a4e3c422dbd13341688b54f159bb.tar.xz
linux-07bafc1e3536a4e3c422dbd13341688b54f159bb.zip
mmc: sunxi: Use new timing mode for A64 eMMC controller
The eMMC controller is also a new timing mode controller, but it doesn't have the timing mode switch. It does however have signal delay and calibration controls, typical of Allwinner MMC controllers that support the new timing mode. Enable the new timing mode setting for the A64 eMMC controller. This also enables MMC HS-DDR modes, which gives higher throughput for eMMC chips that support it, and can deliver such throughput. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
-rw-r--r--drivers/mmc/host/sunxi-mmc.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 5f8d3ea0a0f8..279e326e397e 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -1177,6 +1177,7 @@ static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
.idma_des_size_bits = 13,
.clk_delays = NULL,
.can_calibrate = true,
+ .needs_new_timings = true,
};
static const struct of_device_id sunxi_mmc_of_match[] = {