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| author | Hui Tang <tanghui20@huawei.com> | 2022-03-16 12:26:03 +0100 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2022-04-08 10:13:30 +0200 |
| commit | 4cda2f4a0ee68a23cadfa8cc0fce9af548c29fe2 (patch) | |
| tree | ebb0d797ad7c57872e78a3a19a10693a40d188fa | |
| parent | crypto: engine - Add parameter description in crypto_transfer_request() kerne... (diff) | |
| download | linux-4cda2f4a0ee68a23cadfa8cc0fce9af548c29fe2.tar.xz linux-4cda2f4a0ee68a23cadfa8cc0fce9af548c29fe2.zip | |
crypto: hisilicon/qm - optimize the barrier operation
A 'dma_wmb' barrier is enough to guarantee previous writes
before accessing by acc device in the outer shareable domain.
A 'smp_wmb' barrier is enough to guarantee previous writes
before accessing by other cpus in the inner shareble domain.
Signed-off-by: Hui Tang <tanghui20@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| -rw-r--r-- | drivers/crypto/hisilicon/qm.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index 009132333d2b..c5c507f2d779 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -687,13 +687,13 @@ static void qm_mb_write(struct hisi_qm *qm, const void *src) if (!IS_ENABLED(CONFIG_ARM64)) { memcpy_toio(fun_base, src, 16); - wmb(); + dma_wmb(); return; } asm volatile("ldp %0, %1, %3\n" "stp %0, %1, %2\n" - "dsb sy\n" + "dmb oshst\n" : "=&r" (tmp0), "=&r" (tmp1), "+Q" (*((char __iomem *)fun_base)) @@ -982,7 +982,7 @@ static void qm_set_qp_disable(struct hisi_qp *qp, int offset) *addr = 1; /* make sure setup is completed */ - mb(); + smp_wmb(); } static void qm_disable_qp(struct hisi_qm *qm, u32 qp_id) |