diff options
| author | Jian Shen <shenjian15@huawei.com> | 2018-08-14 18:13:15 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2018-08-14 18:54:23 +0200 |
| commit | 60081dcc4fce385ade26d3145b2479789df0b7e5 (patch) | |
| tree | 723d59fd8f96f7307c83c494e646b3c1f1a574be | |
| parent | net: hns3: Fix for information of phydev lost problem when down/up (diff) | |
| download | linux-60081dcc4fce385ade26d3145b2479789df0b7e5.tar.xz linux-60081dcc4fce385ade26d3145b2479789df0b7e5.zip | |
net: hns3: Fix for phy link issue when using marvell phy driver
For marvell phy m88e1510, bit SUPPORTED_FIBRE of phydev->supported
is default on. Both phy_resume() and phy_suspend() will check the
SUPPORTED_FIBRE bit and write register of fibre page.
Currently in hns3 driver, the SUPPORTED_FIBRE bit will be cleared
after phy_connect_direct() finished. Because phy_resume() is called
in phy_connect_direct(), and phy_suspend() is called when disconnect
phy device, so the operation for fibre page register is not symmetrical.
It will cause phy link issue when reload hns3 driver.
This patch fixes it by disable the SUPPORTED_FIBRE before connecting
phy.
Fixes: 256727da7395 ("net: hns3: Add MDIO support to HNS3 Ethernet driver for hip08 SoC")
Signed-off-by: Jian Shen <shenjian15@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c index 85a123d40e8b..398971a062f4 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c @@ -202,6 +202,8 @@ int hclge_mac_connect_phy(struct hclge_dev *hdev) if (!phydev) return 0; + phydev->supported &= ~SUPPORTED_FIBRE; + ret = phy_connect_direct(netdev, phydev, hclge_mac_adjust_link, PHY_INTERFACE_MODE_SGMII); |