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| author | Damien Le Moal <dlemoal@kernel.org> | 2024-10-17 03:58:37 +0200 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2024-11-25 20:18:35 +0100 |
| commit | 739e25f51aedaebf20496fbc99c6ef43fc6d6ca1 (patch) | |
| tree | 6192fb2a55e13ce07b3cf3faf5bef1b5ee0e5193 | |
| parent | PCI: rockchip-ep: Fix address translation unit programming (diff) | |
| download | linux-739e25f51aedaebf20496fbc99c6ef43fc6d6ca1.tar.xz linux-739e25f51aedaebf20496fbc99c6ef43fc6d6ca1.zip | |
PCI: rockchip-ep: Use a macro to define EP controller .align feature
Introduce the macro ROCKCHIP_PCIE_AT_SIZE_ALIGN to initialize the .align
field of the controller epc_features structure to 256. This is defined
as a shift using the macro ROCKCHIP_PCIE_AT_MIN_NUM_BITS (to avoid
using the "magic" value 8 directly).
Link: https://lore.kernel.org/r/20241017015849.190271-3-dlemoal@kernel.org
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
| -rw-r--r-- | drivers/pci/controller/pcie-rockchip-ep.c | 2 | ||||
| -rw-r--r-- | drivers/pci/controller/pcie-rockchip.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index a6805b005798..65014681d859 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -449,7 +449,7 @@ static const struct pci_epc_features rockchip_pcie_epc_features = { .linkup_notifier = false, .msi_capable = true, .msix_capable = false, - .align = 256, + .align = ROCKCHIP_PCIE_AT_SIZE_ALIGN, }; static const struct pci_epc_features* diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 15ee949f2485..02368ce9bd54 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -248,6 +248,7 @@ #define ROCKCHIP_PCIE_AT_MIN_NUM_BITS 8 #define ROCKCHIP_PCIE_AT_MAX_NUM_BITS 20 +#define ROCKCHIP_PCIE_AT_SIZE_ALIGN (1UL << ROCKCHIP_PCIE_AT_MIN_NUM_BITS) #define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ (PCIE_CORE_AXI_CONF_BASE + 0x0828 + (fn) * 0x0040 + (bar) * 0x0008) |