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authorStephen Warren <swarren@nvidia.com>2012-09-11 01:05:01 +0200
committerStephen Warren <swarren@nvidia.com>2012-09-11 18:06:14 +0200
commitce32ddaa7087da7c9d43751db423281711a1ff2e (patch)
tree4918a9517b5e0175e2dbdf2a75b542f712d30aa7 /CREDITS
parentARM: tegra: fix overflow in tegra20_pll_clk_round_rate() (diff)
downloadlinux-ce32ddaa7087da7c9d43751db423281711a1ff2e.tar.xz
linux-ce32ddaa7087da7c9d43751db423281711a1ff2e.zip
ARM: tegra: cpu-tegra: explicitly manage re-parenting
When changing a PLL's rate, it must have no active children. The CPU clock cannot be stopped, and CPU clock's divider is not used. The old clock driver used to handle this by internally reparenting the CPU clock onto a different PLL when changing the CPU clock rate. However, the new common-clock based clock driver does not do this, and probably cannot do this due to the locking issues it would cause. To solve this, have the Tegra cpufreq driver explicitly perform the reparenting operations itself. This is probably reasonable anyway, since such reparenting is somewhat a matter of policy (e.g. which alternate clock source to use, whether to leave the CPU clock a child of the alternate clock source if it's running at the desired rate), and hence is something more appropriate for the cpufreq driver than the core clock driver anyway. Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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