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authorJean Pihet <jean.pihet@newoldbits.com>2012-06-01 17:11:07 +0200
committerKevin Hilman <khilman@ti.com>2012-06-25 20:24:24 +0200
commit13d65c897e93dfeaed6fe28233559239f9676164 (patch)
tree0e68226def4d9b927ef44abbf6ac742a42680496 /Documentation/DMA-ISA-LPC.txt
parentARM: OMAP3: PM: cpuidle: default to C1 in next_valid_state (diff)
downloadlinux-13d65c897e93dfeaed6fe28233559239f9676164.tar.xz
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ARM: OMAP3: PM: cpuidle: optimize the PER latency in C1 state
One of the main contributors of the low power code latency is the PER power domain. To optimize the high-performance and low-latency C1 state, prevent any PER state which is lower than the CORE state in C1. Reported and suggested by Kevin Hilman. Reported-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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