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authorKedareswara rao Appana <appana.durga.rao@xilinx.com>2016-07-09 10:39:48 +0200
committerVinod Koul <vinod.koul@intel.com>2016-07-12 06:31:36 +0200
commite598e6eb46dd448d9b77a564e4d9664da52e3e1f (patch)
tree18c321dfa37a0be4732ef555f554b802bf68c855 /Documentation/VGA-softcursor.txt
parentdmaengine: Add Xilinx zynqmp dma engine driver support (diff)
downloadlinux-e598e6eb46dd448d9b77a564e4d9664da52e3e1f.tar.xz
linux-e598e6eb46dd448d9b77a564e4d9664da52e3e1f.zip
dmaengine: xilinx: Fix race condition in axi dma cyclic dma mode
In cyclic DMA mode need to link the tail bd segment with the head bd segment to process bd's in cyclic. Current driver is doing this only for tx channel needs to update the same for rx channel case also. This patch fixes the same. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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