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| author | Tom Lendacky <thomas.lendacky@amd.com> | 2023-02-09 16:22:25 +0100 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2023-02-10 13:27:37 +0100 |
| commit | 6f0f2d5ef895d66a3f2b32dd05189ec34afa5a55 (patch) | |
| tree | f48d5b64cf7eae1d37b1668ac46ec4987b2defd7 /Documentation/admin-guide/hw-vuln | |
| parent | x86/speculation: Identify processors vulnerable to SMT RSB predictions (diff) | |
| download | linux-6f0f2d5ef895d66a3f2b32dd05189ec34afa5a55.tar.xz linux-6f0f2d5ef895d66a3f2b32dd05189ec34afa5a55.zip | |
KVM: x86: Mitigate the cross-thread return address predictions bug
By default, KVM/SVM will intercept attempts by the guest to transition
out of C0. However, the KVM_CAP_X86_DISABLE_EXITS capability can be used
by a VMM to change this behavior. To mitigate the cross-thread return
address predictions bug (X86_BUG_SMT_RSB), a VMM must not be allowed to
override the default behavior to intercept C0 transitions.
Use a module parameter to control the mitigation on processors that are
vulnerable to X86_BUG_SMT_RSB. If the processor is vulnerable to the
X86_BUG_SMT_RSB bug and the module parameter is set to mitigate the bug,
KVM will not allow the disabling of the HLT, MWAIT and CSTATE exits.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <4019348b5e07148eb4d593380a5f6713b93c9a16.1675956146.git.thomas.lendacky@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'Documentation/admin-guide/hw-vuln')
0 files changed, 0 insertions, 0 deletions