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| author | Dave Martin <dave.martin@linaro.org> | 2011-07-13 16:53:30 +0200 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-07-19 13:00:53 +0200 |
| commit | 540b573875bd26dfe39aa18d22dc195f275fc0df (patch) | |
| tree | d4fc0c012ef109d601e28814b3806eb44ce357c7 /Documentation/arm/Booting | |
| parent | ARM: 6995/2: mm: remove unnecessary cache flush on v6 copypage (diff) | |
| download | linux-540b573875bd26dfe39aa18d22dc195f275fc0df.tar.xz linux-540b573875bd26dfe39aa18d22dc195f275fc0df.zip | |
ARM: 6999/1: head, zImage: Always Enter the kernel in ARM state
Currently, the documented kernel entry requirements are not
explicit about whether the kernel should be entered in ARM or
Thumb, leading to an ambiguitity about how to enter Thumb-2
kernels. As a result, the kernel is reliant on the zImage
decompressor to enter the kernel proper in the correct instruction
set state.
This patch changes the boot entry protocol for head.S and Image to
be the same as for zImage: in all cases, the kernel is now entered
in ARM.
Documentation/arm/Booting is updated to reflect this new policy.
A different rule will be needed for Cortex-M class CPUs as and when
support for those lands in mainline, since these CPUs don't support
the ARM instruction set at all: a note is added to the effect that
the kernel must be entered in Thumb on such systems.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'Documentation/arm/Booting')
| -rw-r--r-- | Documentation/arm/Booting | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/arm/Booting b/Documentation/arm/Booting index 4e686a2ed91e..a341d87d276e 100644 --- a/Documentation/arm/Booting +++ b/Documentation/arm/Booting @@ -164,3 +164,8 @@ In either case, the following conditions must be met: - The boot loader is expected to call the kernel image by jumping directly to the first instruction of the kernel image. + On CPUs supporting the ARM instruction set, the entry must be + made in ARM state, even for a Thumb-2 kernel. + + On CPUs supporting only the Thumb instruction set such as + Cortex-M class CPUs, the entry must be made in Thumb state. |