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| author | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-04-14 18:48:38 +0200 |
|---|---|---|
| committer | Jonathan Corbet <corbet@lwn.net> | 2020-04-20 23:45:22 +0200 |
| commit | d91589556b6a096d53f47ed3d91172a2788d4cdb (patch) | |
| tree | c9f96127e6c8c55b927503006a971d4b3d39d97e /Documentation/arm64/amu.rst | |
| parent | docs: filesystems: fix renamed references (diff) | |
| download | linux-d91589556b6a096d53f47ed3d91172a2788d4cdb.tar.xz linux-d91589556b6a096d53f47ed3d91172a2788d4cdb.zip | |
docs: amu: supress some Sphinx warnings
Add extra blank lines on some places, in order to avoid those
warnings when building the docs:
Documentation/arm64/amu.rst:26: WARNING: Unexpected indentation.
Documentation/arm64/amu.rst:60: WARNING: Unexpected indentation.
Documentation/arm64/amu.rst:81: WARNING: Unexpected indentation.
Documentation/arm64/amu.rst:108: WARNING: Unexpected indentation.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Link: https://lore.kernel.org/r/ab0881638fc41ed790b3307a8e022ec84b7cce7e.1586881715.git.mchehab+huawei@kernel.org
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Diffstat (limited to 'Documentation/arm64/amu.rst')
| -rw-r--r-- | Documentation/arm64/amu.rst | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/arm64/amu.rst b/Documentation/arm64/amu.rst index 5057b11100ed..452ec8b115c2 100644 --- a/Documentation/arm64/amu.rst +++ b/Documentation/arm64/amu.rst @@ -23,6 +23,7 @@ optional external memory-mapped interface. Version 1 of the Activity Monitors architecture implements a counter group of four fixed and architecturally defined 64-bit event counters. + - CPU cycle counter: increments at the frequency of the CPU. - Constant counter: increments at the fixed frequency of the system clock. @@ -57,6 +58,7 @@ counters, only the presence of the extension. Firmware (code running at higher exception levels, e.g. arm-tf) support is needed to: + - Enable access for lower exception levels (EL2 and EL1) to the AMU registers. - Enable the counters. If not enabled these will read as 0. @@ -78,6 +80,7 @@ are not trapped in EL2/EL3. The fixed counters of AMUv1 are accessible though the following system register definitions: + - SYS_AMEVCNTR0_CORE_EL0 - SYS_AMEVCNTR0_CONST_EL0 - SYS_AMEVCNTR0_INST_RET_EL0 @@ -93,6 +96,7 @@ Userspace access ---------------- Currently, access from userspace to the AMU registers is disabled due to: + - Security reasons: they might expose information about code executed in secure mode. - Purpose: AMU counters are intended for system management use. @@ -105,6 +109,7 @@ Virtualization Currently, access from userspace (EL0) and kernelspace (EL1) on the KVM guest side is disabled due to: + - Security reasons: they might expose information about code executed by other guests or the host. |