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| author | Catalin Marinas <catalin.marinas@arm.com> | 2014-03-26 19:25:55 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2014-04-05 11:06:18 +0200 |
| commit | c218bca74eeafa2f8528b6bbb34d112075fcf40a (patch) | |
| tree | 29b3e350efca77e073436df3cf78b818bf57cc34 /Documentation/arm64/booting.txt | |
| parent | arm64: Update the TCR_EL1 translation granule definitions for 16K pages (diff) | |
| download | linux-c218bca74eeafa2f8528b6bbb34d112075fcf40a.tar.xz linux-c218bca74eeafa2f8528b6bbb34d112075fcf40a.zip | |
arm64: Relax the kernel cache requirements for boot
With system caches for the host OS or architected caches for guest OS we
cannot easily guarantee that there are no dirty or stale cache lines for
the areas of memory written by the kernel during boot with the MMU off
(therefore non-cacheable accesses).
This patch adds the necessary cache maintenance during boot and relaxes
the booting requirements.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'Documentation/arm64/booting.txt')
| -rw-r--r-- | Documentation/arm64/booting.txt | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt index a9691cc48fe3..beb754e87c65 100644 --- a/Documentation/arm64/booting.txt +++ b/Documentation/arm64/booting.txt @@ -111,8 +111,14 @@ Before jumping into the kernel, the following conditions must be met: - Caches, MMUs The MMU must be off. Instruction cache may be on or off. - Data cache must be off and invalidated. - External caches (if present) must be configured and disabled. + The address range corresponding to the loaded kernel image must be + cleaned to the PoC. In the presence of a system cache or other + coherent masters with caches enabled, this will typically require + cache maintenance by VA rather than set/way operations. + System caches which respect the architected cache maintenance by VA + operations must be configured and may be enabled. + System caches which do not respect architected cache maintenance by VA + operations (not recommended) must be configured and disabled. - Architected timers CNTFRQ must be programmed with the timer frequency and CNTVOFF must |