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| author | Dave Martin <Dave.Martin@arm.com> | 2017-10-31 16:51:19 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2017-11-03 16:24:21 +0100 |
| commit | 43994d824e8443263dc98b151e6326bf677be52e (patch) | |
| tree | ef769d01442f52999428d241b02b0c849489842b /Documentation/arm64/cpu-feature-registers.txt | |
| parent | arm64/sve: KVM: Hide SVE from CPU features exposed to guests (diff) | |
| download | linux-43994d824e8443263dc98b151e6326bf677be52e.tar.xz linux-43994d824e8443263dc98b151e6326bf677be52e.zip | |
arm64/sve: Detect SVE and activate runtime support
This patch enables detection of hardware SVE support via the
cpufeatures framework, and reports its presence to the kernel and
userspace via the new ARM64_SVE cpucap and HWCAP_SVE hwcap
respectively.
Userspace can also detect SVE using ID_AA64PFR0_EL1, using the
cpufeatures MRS emulation.
When running on hardware that supports SVE, this enables runtime
kernel support for SVE, and allows user tasks to execute SVE
instructions and make of the of the SVE-specific user/kernel
interface extensions implemented by this series.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'Documentation/arm64/cpu-feature-registers.txt')
| -rw-r--r-- | Documentation/arm64/cpu-feature-registers.txt | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/Documentation/arm64/cpu-feature-registers.txt b/Documentation/arm64/cpu-feature-registers.txt index 011ddfc1e570..bd9b3faab2c4 100644 --- a/Documentation/arm64/cpu-feature-registers.txt +++ b/Documentation/arm64/cpu-feature-registers.txt @@ -142,7 +142,11 @@ infrastructure: x--------------------------------------------------x | Name | bits | visible | |--------------------------------------------------| - | RES0 | [63-28] | n | + | RES0 | [63-36] | n | + |--------------------------------------------------| + | SVE | [35-32] | y | + |--------------------------------------------------| + | RES0 | [31-28] | n | |--------------------------------------------------| | GIC | [27-24] | n | |--------------------------------------------------| |