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authorshameer <shameerali.kolothum.thodi@huawei.com>2017-05-17 11:12:05 +0200
committerWill Deacon <will.deacon@arm.com>2017-06-23 18:58:04 +0200
commit99caf177f6fd3e67575f6ce05b36e8e041bcef60 (patch)
tree1e0df3e173263c726b8883b452505fde07b8ed4f /Documentation/arm64
parentiommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 (diff)
downloadlinux-99caf177f6fd3e67575f6ce05b36e8e041bcef60.tar.xz
linux-99caf177f6fd3e67575f6ce05b36e8e041bcef60.zip
iommu/arm-smmu-v3: Enable ACPI based HiSilicon CMD_PREFETCH quirk(erratum 161010701)
HiSilicon SMMUv3 on Hip06/Hip07 platforms doesn't support CMD_PREFETCH command. The dt based support for this quirk is already present in the driver(hisilicon,broken-prefetch-cmd). This adds ACPI support for the quirk using the IORT smmu model number. Signed-off-by: shameer <shameerali.kolothum.thodi@huawei.com> Signed-off-by: hanjun <guohanjun@huawei.com> [will: rewrote patch] Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'Documentation/arm64')
-rw-r--r--Documentation/arm64/silicon-errata.txt1
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 4693a328947a..ef4e43590685 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -67,6 +67,7 @@ stable kernels.
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
| | | | |
| Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |
+| Hisilicon | Hip0{6,7} | #161010701 | N/A |
| | | | |
| Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
| Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |