diff options
| author | Marc Zyngier <maz@kernel.org> | 2021-10-17 14:42:25 +0200 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2021-10-19 11:56:20 +0200 |
| commit | fee29f008aa3f2aff01117f28b57b1145d92cb9b (patch) | |
| tree | c8e8ea36d8cb73ced0b6557d7e862cf9571408bb /Documentation/arm64 | |
| parent | arm64: Add handling of CNTVCTSS traps (diff) | |
| download | linux-fee29f008aa3f2aff01117f28b57b1145d92cb9b.tar.xz linux-fee29f008aa3f2aff01117f28b57b1145d92cb9b.zip | |
arm64: Add HWCAP for self-synchronising virtual counter
Since userspace can make use of the CNTVSS_EL0 instruction, expose
it via a HWCAP.
Suggested-by: Will Deacon <will@kernel.org>
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-18-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'Documentation/arm64')
| -rw-r--r-- | Documentation/arm64/cpu-feature-registers.rst | 12 | ||||
| -rw-r--r-- | Documentation/arm64/elf_hwcaps.rst | 4 |
2 files changed, 14 insertions, 2 deletions
diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst index 328e0c454fbd..9f9b8fd06089 100644 --- a/Documentation/arm64/cpu-feature-registers.rst +++ b/Documentation/arm64/cpu-feature-registers.rst @@ -235,7 +235,15 @@ infrastructure: | DPB | [3-0] | y | +------------------------------+---------+---------+ - 6) ID_AA64MMFR2_EL1 - Memory model feature register 2 + 6) ID_AA64MMFR0_EL1 - Memory model feature register 0 + + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | ECV | [63-60] | y | + +------------------------------+---------+---------+ + + 7) ID_AA64MMFR2_EL1 - Memory model feature register 2 +------------------------------+---------+---------+ | Name | bits | visible | @@ -243,7 +251,7 @@ infrastructure: | AT | [35-32] | y | +------------------------------+---------+---------+ - 7) ID_AA64ZFR0_EL1 - SVE feature ID register 0 + 8) ID_AA64ZFR0_EL1 - SVE feature ID register 0 +------------------------------+---------+---------+ | Name | bits | visible | diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst index ec1a5a63c1d0..af106af8e1c0 100644 --- a/Documentation/arm64/elf_hwcaps.rst +++ b/Documentation/arm64/elf_hwcaps.rst @@ -247,6 +247,10 @@ HWCAP2_MTE Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described by Documentation/arm64/memory-tagging-extension.rst. +HWCAP2_ECV + + Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001. + 4. Unused AT_HWCAP bits ----------------------- |