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authorJames Morse <james.morse@arm.com>2022-09-30 15:19:59 +0200
committerCatalin Marinas <catalin.marinas@arm.com>2022-10-07 15:42:20 +0200
commit171df58028bf4649460fb146a56a58dcb0c8f75a (patch)
treef2d404265dbde354b2f6768c8c66e3eab4015e19 /Documentation/arm64
parentarm64/sysreg: Fix typo in SCTR_EL1.SPINTMASK (diff)
downloadlinux-171df58028bf4649460fb146a56a58dcb0c8f75a.tar.xz
linux-171df58028bf4649460fb146a56a58dcb0c8f75a.zip
arm64: errata: Add Cortex-A55 to the repeat tlbi list
Cortex-A55 is affected by an erratum where in rare circumstances the CPUs may not handle a race between a break-before-make sequence on one CPU, and another CPU accessing the same page. This could allow a store to a page that has been unmapped. Work around this by adding the affected CPUs to the list that needs TLB sequences to be done twice. Signed-off-by: James Morse <james.morse@arm.com> Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20220930131959.3082594-1-james.morse@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'Documentation/arm64')
-rw-r--r--Documentation/arm64/silicon-errata.rst2
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index 17d9fc5d14fb..808ade4cc008 100644
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -76,6 +76,8 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A55 | #1530923 | ARM64_ERRATUM_1530923 |
+----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-A55 | #2441007 | ARM64_ERRATUM_2441007 |
++----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A57 | #852523 | N/A |