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| author | Chen-Yu Tsai <wens@csie.org> | 2014-09-16 12:04:01 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2014-09-27 09:05:43 +0200 |
| commit | 9c8176bfb67f98ed9a521b624dcb6ab7fa254aa7 (patch) | |
| tree | 52bf5988af67aa1c7423010c09dbccfe9ab40671 /Documentation/cachetlb.txt | |
| parent | clk: sunxi: mod0: Introduce MMC proper phase handling (diff) | |
| download | linux-9c8176bfb67f98ed9a521b624dcb6ab7fa254aa7.tar.xz linux-9c8176bfb67f98ed9a521b624dcb6ab7fa254aa7.zip | |
clk: sunxi: Add sun8i MBUS clock support
The MBUS clock on sun8i is slightly different from the old mod0 clocks.
The divider is 3 bits wider, while also needing a divider table for the
higher 4 values, which all set the same divider.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'Documentation/cachetlb.txt')
0 files changed, 0 insertions, 0 deletions