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authorHeiko Stuebner <heiko@sntech.de>2014-10-15 19:23:01 +0200
committerHeiko Stuebner <heiko@sntech.de>2014-11-05 22:18:36 +0100
commit6de2d21adaf05b7a456077625b6e311feabd3718 (patch)
tree2e49cd6325051c13dd43e21652f9a8362581c308 /Documentation/devicetree/bindings/arm/cpus.txt
parentARM: rockchip: convert to regmap and use pmu syscon if available (diff)
downloadlinux-6de2d21adaf05b7a456077625b6e311feabd3718.tar.xz
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ARM: rockchip: add option to access the pmu via a phandle in smp_operations
Makes it possible to define a rockchip,pmu phandle in the cpus node directly referencing the pmu syscon instead of searching for specific compatible. The old way of finding the pmu stays of course available. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index fc446347ab6d..b2aacbe16ed9 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -227,6 +227,15 @@ nodes to be present and contain the properties described below.
# List of phandles to idle state nodes supported
by this cpu [3].
+ - rockchip,pmu
+ Usage: optional for systems that have an "enable-method"
+ property value of "rockchip,rk3066-smp"
+ While optional, it is the preferred way to get access to
+ the cpu-core power-domains.
+ Value type: <phandle>
+ Definition: Specifies the syscon node controlling the cpu core
+ power domains.
+
Example 1 (dual-cluster big.LITTLE system 32-bit):
cpus {